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[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [devl/] [projnav/] [ipcore_dir/] [spiloopmem_ste/] [implement/] [implement.sh] - Blame information for rev 14

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Line No. Rev Author Line
1 14 mjlyons
#!/bin/sh
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# Clean up the results directory
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rm -rf results
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mkdir results
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#Synthesize the Wrapper Files
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echo 'Synthesizing XST wrapper file (core_top.vhd) with XST';
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echo 'Synthesizing example design with XST';
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xst -ifn xst.scr
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cp spiloopmem_top.ngc ./results/
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# Copy the netlist generated by Coregen
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echo 'Copying files from the netlist directory to the results directory'
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cp ../../spiloopmem.ngc results/
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#  Copy the constraints files generated by Coregen
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echo 'Copying files from constraints directory to results directory'
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cp ../example_design/spiloopmem_top.ucf results/
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cd results
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echo 'Running ngdbuild'
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ngdbuild -p xc6slx45-csg324-2 spiloopmem_top
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echo 'Running map'
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map spiloopmem_top -o mapped.ncd -pr i
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echo 'Running par'
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par mapped.ncd routed.ncd
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echo 'Running trce'
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trce -e 10 routed.ncd mapped.pcf -o routed
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echo 'Running design through bitgen'
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bitgen -w routed
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echo 'Running netgen to create gate level Verilog model'
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netgen -ofmt verilog -sim -tm spiloopmem_top -pcf mapped.pcf -w routed.ncd routed.v
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cp routed.sdf ../../production/timing/

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