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1 14 mjlyons
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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# 
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# This file contains confidential and proprietary information
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# of Xilinx, Inc. and is protected under U.S. and
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# international copyright and other intellectual property
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# laws.
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# 
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# DISCLAIMER
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# This disclaimer is not a license and does not grant any
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# rights to the materials distributed herewith. Except as
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# otherwise provided in a valid license issued to you by
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# Xilinx, and to the maximum extent permitted by applicable
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# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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# (2) Xilinx shall not be liable (whether in contract or tort,
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# including negligence, or under any other theory of
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# liability) for any loss or damage of any kind or nature
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# related to, arising under or in connection with these
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# materials, including for any direct, or any indirect,
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# special, incidental, or consequential loss or damage
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# (including loss of data, profits, goodwill, or any type of
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# loss or damage suffered as a result of any action brought
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# by a third party) even if such damage or loss was
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# reasonably foreseeable or Xilinx had been advised of the
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# possibility of the same.
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# 
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# CRITICAL APPLICATIONS
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# Xilinx products are not designed or intended to be fail-
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# safe, or for use in any application requiring fail-safe
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# performance, such as life-support or safety devices or
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# systems, Class III medical devices, nuclear facilities,
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# applications related to the deployment of airbags, or any
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# other applications that could lead to death, personal
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# injury, or severe property or environmental damage
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# (individually and collectively, "Critical
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# Applications"). Customer assumes the sole risk and
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# liability of any use of Xilinx products in Critical
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# Applications, subject only to applicable laws and
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# regulations governing limitations on product liability.
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# 
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# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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# PART OF THIS FILE AT ALL TIMES.
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set device xc6slx45csg324-2
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set projName spiloopmem
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set design spiloopmem
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set projDir [file dirname [info script]]
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create_project $projName $projDir/results/$projName -part $device -force
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set_property design_mode RTL [current_fileset -srcset]
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set top_module spiloopmem_top
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add_files -norecurse {../../example_design/spiloopmem_top.vhd}
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add_files -norecurse {./spiloopmem.edf}
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import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/spiloopmem_top.xdc}
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set_property top spiloopmem_top [get_property srcset [current_run]]
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synth_design
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opt_design
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place_design
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route_design
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write_sdf -rename_top_module spiloopmem_top -file routed.sdf
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write_verilog -nolib -mode sim -sdf_anno false -rename_top_module spiloopmem_top routed.v
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report_timing -nworst 30 -path_type full -file routed.twr
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report_drc -file routed.drc
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#write_bitstream

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