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[/] [vspi/] [trunk/] [projnav/] [xps/] [pcores/] [spiifc_v1_00_a/] [hdl/] [vhdl/] [spiifc.vhd] - Blame information for rev 14

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1 14 mjlyons
------------------------------------------------------------------------------
2
-- spiifc.vhd - entity/architecture pair
3
------------------------------------------------------------------------------
4
-- IMPORTANT:
5
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
6
--
7
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
8
--
9
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
10
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
11
-- OF THE USER_LOGIC ENTITY.
12
------------------------------------------------------------------------------
13
--
14
-- ***************************************************************************
15
-- ** Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.            **
16
-- **                                                                       **
17
-- ** Xilinx, Inc.                                                          **
18
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
19
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
20
-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
21
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
22
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
23
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
24
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
25
-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
26
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
27
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
28
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
29
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
30
-- ** FOR A PARTICULAR PURPOSE.                                             **
31
-- **                                                                       **
32
-- ***************************************************************************
33
--
34
------------------------------------------------------------------------------
35
-- Filename:          spiifc.vhd
36
-- Version:           1.00.a
37
-- Description:       Top level design, instantiates library components and user logic.
38
-- Date:              Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
39
-- VHDL Standard:     VHDL'93
40
------------------------------------------------------------------------------
41
-- Naming Conventions:
42
--   active low signals:                    "*_n"
43
--   clock signals:                         "clk", "clk_div#", "clk_#x"
44
--   reset signals:                         "rst", "rst_n"
45
--   generics:                              "C_*"
46
--   user defined types:                    "*_TYPE"
47
--   state machine next state:              "*_ns"
48
--   state machine current state:           "*_cs"
49
--   combinatorial signals:                 "*_com"
50
--   pipelined or register delay signals:   "*_d#"
51
--   counter signals:                       "*cnt*"
52
--   clock enable signals:                  "*_ce"
53
--   internal version of output port:       "*_i"
54
--   device pins:                           "*_pin"
55
--   ports:                                 "- Names begin with Uppercase"
56
--   processes:                             "*_PROCESS"
57
--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
58
------------------------------------------------------------------------------
59
 
60
library ieee;
61
use ieee.std_logic_1164.all;
62
use ieee.std_logic_arith.all;
63
use ieee.std_logic_unsigned.all;
64
 
65
library proc_common_v3_00_a;
66
use proc_common_v3_00_a.proc_common_pkg.all;
67
use proc_common_v3_00_a.ipif_pkg.all;
68
 
69
library interrupt_control_v2_01_a;
70
use interrupt_control_v2_01_a.interrupt_control;
71
 
72
library plbv46_slave_burst_v1_01_a;
73
use plbv46_slave_burst_v1_01_a.plbv46_slave_burst;
74
 
75
------------------------------------------------------------------------------
76
-- Entity section
77
------------------------------------------------------------------------------
78
-- Definition of Generics:
79
--   C_BASEADDR                   -- PLBv46 slave: base address
80
--   C_HIGHADDR                   -- PLBv46 slave: high address
81
--   C_SPLB_AWIDTH                -- PLBv46 slave: address bus width
82
--   C_SPLB_DWIDTH                -- PLBv46 slave: data bus width
83
--   C_SPLB_NUM_MASTERS           -- PLBv46 slave: Number of masters
84
--   C_SPLB_MID_WIDTH             -- PLBv46 slave: master ID bus width
85
--   C_SPLB_NATIVE_DWIDTH         -- PLBv46 slave: internal native data bus width
86
--   C_SPLB_P2P                   -- PLBv46 slave: point to point interconnect scheme
87
--   C_SPLB_SUPPORT_BURSTS        -- PLBv46 slave: support bursts
88
--   C_SPLB_SMALLEST_MASTER       -- PLBv46 slave: width of the smallest master
89
--   C_SPLB_CLK_PERIOD_PS         -- PLBv46 slave: bus clock in picoseconds
90
--   C_INCLUDE_DPHASE_TIMER       -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
91
--   C_FAMILY                     -- Xilinx FPGA family
92
--   C_MEM0_BASEADDR              -- User memory space 0 base address
93
--   C_MEM0_HIGHADDR              -- User memory space 0 high address
94
--   C_MEM1_BASEADDR              -- User memory space 1 base address
95
--   C_MEM1_HIGHADDR              -- User memory space 1 high address
96
--
97
-- Definition of Ports:
98
--   SPLB_Clk                     -- PLB main bus clock
99
--   SPLB_Rst                     -- PLB main bus reset
100
--   PLB_ABus                     -- PLB address bus
101
--   PLB_UABus                    -- PLB upper address bus
102
--   PLB_PAValid                  -- PLB primary address valid indicator
103
--   PLB_SAValid                  -- PLB secondary address valid indicator
104
--   PLB_rdPrim                   -- PLB secondary to primary read request indicator
105
--   PLB_wrPrim                   -- PLB secondary to primary write request indicator
106
--   PLB_masterID                 -- PLB current master identifier
107
--   PLB_abort                    -- PLB abort request indicator
108
--   PLB_busLock                  -- PLB bus lock
109
--   PLB_RNW                      -- PLB read/not write
110
--   PLB_BE                       -- PLB byte enables
111
--   PLB_MSize                    -- PLB master data bus size
112
--   PLB_size                     -- PLB transfer size
113
--   PLB_type                     -- PLB transfer type
114
--   PLB_lockErr                  -- PLB lock error indicator
115
--   PLB_wrDBus                   -- PLB write data bus
116
--   PLB_wrBurst                  -- PLB burst write transfer indicator
117
--   PLB_rdBurst                  -- PLB burst read transfer indicator
118
--   PLB_wrPendReq                -- PLB write pending bus request indicator
119
--   PLB_rdPendReq                -- PLB read pending bus request indicator
120
--   PLB_wrPendPri                -- PLB write pending request priority
121
--   PLB_rdPendPri                -- PLB read pending request priority
122
--   PLB_reqPri                   -- PLB current request priority
123
--   PLB_TAttribute               -- PLB transfer attribute
124
--   Sl_addrAck                   -- Slave address acknowledge
125
--   Sl_SSize                     -- Slave data bus size
126
--   Sl_wait                      -- Slave wait indicator
127
--   Sl_rearbitrate               -- Slave re-arbitrate bus indicator
128
--   Sl_wrDAck                    -- Slave write data acknowledge
129
--   Sl_wrComp                    -- Slave write transfer complete indicator
130
--   Sl_wrBTerm                   -- Slave terminate write burst transfer
131
--   Sl_rdDBus                    -- Slave read data bus
132
--   Sl_rdWdAddr                  -- Slave read word address
133
--   Sl_rdDAck                    -- Slave read data acknowledge
134
--   Sl_rdComp                    -- Slave read transfer complete indicator
135
--   Sl_rdBTerm                   -- Slave terminate read burst transfer
136
--   Sl_MBusy                     -- Slave busy indicator
137
--   Sl_MWrErr                    -- Slave write error indicator
138
--   Sl_MRdErr                    -- Slave read error indicator
139
--   Sl_MIRQ                      -- Slave interrupt indicator
140
--   IP2INTC_Irpt                 -- Interrupt output to processor
141
------------------------------------------------------------------------------
142
 
143
entity spiifc is
144
  generic
145
  (
146
    -- ADD USER GENERICS BELOW THIS LINE ---------------
147
    --USER generics added here
148
    -- ADD USER GENERICS ABOVE THIS LINE ---------------
149
 
150
    -- DO NOT EDIT BELOW THIS LINE ---------------------
151
    -- Bus protocol parameters, do not add to or delete
152
    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
153
    C_HIGHADDR                     : std_logic_vector     := X"00000000";
154
    C_SPLB_AWIDTH                  : integer              := 32;
155
    C_SPLB_DWIDTH                  : integer              := 128;
156
    C_SPLB_NUM_MASTERS             : integer              := 8;
157
    C_SPLB_MID_WIDTH               : integer              := 3;
158
    C_SPLB_NATIVE_DWIDTH           : integer              := 32;
159
    C_SPLB_P2P                     : integer              := 0;
160
    C_SPLB_SUPPORT_BURSTS          : integer              := 1;
161
    C_SPLB_SMALLEST_MASTER         : integer              := 32;
162
    C_SPLB_CLK_PERIOD_PS           : integer              := 10000;
163
    C_INCLUDE_DPHASE_TIMER         : integer              := 1;
164
    C_FAMILY                       : string               := "virtex6";
165
    C_MEM0_BASEADDR                : std_logic_vector     := X"FFFFFFFF";
166
    C_MEM0_HIGHADDR                : std_logic_vector     := X"00000000";
167
    C_MEM1_BASEADDR                : std_logic_vector     := X"FFFFFFFF";
168
    C_MEM1_HIGHADDR                : std_logic_vector     := X"00000000"
169
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
170
  );
171
  port
172
  (
173
    -- ADD USER PORTS BELOW THIS LINE ------------------
174
    SPI_CLK                        : in  std_logic;
175
    SPI_MOSI                       : in  std_logic;
176
    SPI_MISO                       : out std_logic;
177
    SPI_SS                         : in  std_logic;
178
    -- ADD USER PORTS ABOVE THIS LINE ------------------
179
 
180
    -- DO NOT EDIT BELOW THIS LINE ---------------------
181
    -- Bus protocol ports, do not add to or delete
182
    SPLB_Clk                       : in  std_logic;
183
    SPLB_Rst                       : in  std_logic;
184
    PLB_ABus                       : in  std_logic_vector(0 to 31);
185
    PLB_UABus                      : in  std_logic_vector(0 to 31);
186
    PLB_PAValid                    : in  std_logic;
187
    PLB_SAValid                    : in  std_logic;
188
    PLB_rdPrim                     : in  std_logic;
189
    PLB_wrPrim                     : in  std_logic;
190
    PLB_masterID                   : in  std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
191
    PLB_abort                      : in  std_logic;
192
    PLB_busLock                    : in  std_logic;
193
    PLB_RNW                        : in  std_logic;
194
    PLB_BE                         : in  std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
195
    PLB_MSize                      : in  std_logic_vector(0 to 1);
196
    PLB_size                       : in  std_logic_vector(0 to 3);
197
    PLB_type                       : in  std_logic_vector(0 to 2);
198
    PLB_lockErr                    : in  std_logic;
199
    PLB_wrDBus                     : in  std_logic_vector(0 to C_SPLB_DWIDTH-1);
200
    PLB_wrBurst                    : in  std_logic;
201
    PLB_rdBurst                    : in  std_logic;
202
    PLB_wrPendReq                  : in  std_logic;
203
    PLB_rdPendReq                  : in  std_logic;
204
    PLB_wrPendPri                  : in  std_logic_vector(0 to 1);
205
    PLB_rdPendPri                  : in  std_logic_vector(0 to 1);
206
    PLB_reqPri                     : in  std_logic_vector(0 to 1);
207
    PLB_TAttribute                 : in  std_logic_vector(0 to 15);
208
    Sl_addrAck                     : out std_logic;
209
    Sl_SSize                       : out std_logic_vector(0 to 1);
210
    Sl_wait                        : out std_logic;
211
    Sl_rearbitrate                 : out std_logic;
212
    Sl_wrDAck                      : out std_logic;
213
    Sl_wrComp                      : out std_logic;
214
    Sl_wrBTerm                     : out std_logic;
215
    Sl_rdDBus                      : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
216
    Sl_rdWdAddr                    : out std_logic_vector(0 to 3);
217
    Sl_rdDAck                      : out std_logic;
218
    Sl_rdComp                      : out std_logic;
219
    Sl_rdBTerm                     : out std_logic;
220
    Sl_MBusy                       : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
221
    Sl_MWrErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
222
    Sl_MRdErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
223
    Sl_MIRQ                        : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
224
    IP2INTC_Irpt                   : out std_logic
225
    -- DO NOT EDIT ABOVE THIS LINE ---------------------
226
  );
227
 
228
  attribute MAX_FANOUT : string;
229
  attribute SIGIS : string;
230
 
231
  attribute SIGIS of SPLB_Clk      : signal is "CLK";
232
  attribute SIGIS of SPLB_Rst      : signal is "RST";
233
  attribute SIGIS of IP2INTC_Irpt  : signal is "INTR_LEVEL_HIGH";
234
 
235
end entity spiifc;
236
 
237
------------------------------------------------------------------------------
238
-- Architecture section
239
------------------------------------------------------------------------------
240
 
241
architecture IMP of spiifc is
242
 
243
  ------------------------------------------
244
  -- Array of base/high address pairs for each address range
245
  ------------------------------------------
246
  constant ZERO_ADDR_PAD                  : std_logic_vector(0 to 31) := (others => '0');
247
  constant USER_SLV_BASEADDR              : std_logic_vector     := C_BASEADDR or X"00000000";
248
  constant USER_SLV_HIGHADDR              : std_logic_vector     := C_BASEADDR or X"000000FF";
249
  constant INTR_BASEADDR                  : std_logic_vector     := C_BASEADDR or X"00000100";
250
  constant INTR_HIGHADDR                  : std_logic_vector     := C_BASEADDR or X"000001FF";
251
 
252
  constant IPIF_ARD_ADDR_RANGE_ARRAY      : SLV64_ARRAY_TYPE     :=
253
    (
254
      ZERO_ADDR_PAD & USER_SLV_BASEADDR,  -- user logic slave space base address
255
      ZERO_ADDR_PAD & USER_SLV_HIGHADDR,  -- user logic slave space high address
256
      ZERO_ADDR_PAD & INTR_BASEADDR,      -- interrupt control space base address
257
      ZERO_ADDR_PAD & INTR_HIGHADDR,      -- interrupt control space high address
258
      ZERO_ADDR_PAD & C_MEM0_BASEADDR,    -- user logic memory space 0 base address
259
      ZERO_ADDR_PAD & C_MEM0_HIGHADDR,    -- user logic memory space 0 high address
260
      ZERO_ADDR_PAD & C_MEM1_BASEADDR,    -- user logic memory space 1 base address
261
      ZERO_ADDR_PAD & C_MEM1_HIGHADDR     -- user logic memory space 1 high address
262
    );
263
 
264
  ------------------------------------------
265
  -- Array of desired number of chip enables for each address range
266
  ------------------------------------------
267
  constant USER_SLV_NUM_REG               : integer              := 16;
268
  constant USER_NUM_REG                   : integer              := USER_SLV_NUM_REG;
269
  constant INTR_NUM_CE                    : integer              := 16;
270
  constant USER_NUM_MEM                   : integer              := 2;
271
 
272
  constant IPIF_ARD_NUM_CE_ARRAY          : INTEGER_ARRAY_TYPE   :=
273
    (
274
 
275
      1  => INTR_NUM_CE,                  -- number of ce for interrupt control space
276
      2  => 1,                            -- number of ce for user logic memory space 0 (always 1 chip enable)
277
      3  => 1                             -- number of ce for user logic memory space 1 (always 1 chip enable)
278
    );
279
 
280
  ------------------------------------------
281
  -- Cache line addressing mode (for cacheline read operations)
282
  -- 0 = target word first on reads
283
  -- 1 = line word first on reads
284
  ------------------------------------------
285
  constant IPIF_CACHLINE_ADDR_MODE        : integer              := 0;
286
 
287
  ------------------------------------------
288
  -- Number of storage locations for the write buffer
289
  -- Valid depths are 0, 16, 32, or 64
290
  -- 0 = no write buffer implemented
291
  ------------------------------------------
292
  constant IPIF_WR_BUFFER_DEPTH           : integer              := 16;
293
 
294
  ------------------------------------------
295
  -- The type out of the Bus2IP_BurstLength signal
296
  -- 0 = length is in actual byte number
297
  -- 1 = length is in data beats - 1
298
  ------------------------------------------
299
  constant IPIF_BURSTLENGTH_TYPE          : integer              := 0;
300
 
301
  ------------------------------------------
302
  -- Width of the slave data bus (32, 64, or 128)
303
  ------------------------------------------
304
  constant USER_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;
305
 
306
  constant IPIF_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;
307
 
308
  ------------------------------------------
309
  -- Number of device level interrupts
310
  ------------------------------------------
311
  constant INTR_NUM_IPIF_IRPT_SRC         : integer              := 4;
312
 
313
  ------------------------------------------
314
  -- Capture mode for each IP interrupt (generated by user logic)
315
  -- 1 = pass through (non-inverting)
316
  -- 2 = pass through (inverting)
317
  -- 3 = registered level (non-inverting)
318
  -- 4 = registered level (inverting)
319
  -- 5 = positive edge detect
320
  -- 6 = negative edge detect
321
  ------------------------------------------
322
  constant USER_NUM_INTR                  : integer              := 1;
323
  constant USER_INTR_CAPTURE_MODE         : integer              := 1;
324
 
325
  constant INTR_IP_INTR_MODE_ARRAY        : INTEGER_ARRAY_TYPE   :=
326
    (
327
 
328
    );
329
 
330
  ------------------------------------------
331
  -- Device priority encoder feature inclusion/omission
332
  -- true  = include priority encoder
333
  -- false = omit priority encoder
334
  ------------------------------------------
335
  constant INTR_INCLUDE_DEV_PENCODER      : boolean              := false;
336
 
337
  ------------------------------------------
338
  -- Device ISC feature inclusion/omission
339
  -- true  = include device ISC
340
  -- false = omit device ISC
341
  ------------------------------------------
342
  constant INTR_INCLUDE_DEV_ISC           : boolean              := false;
343
 
344
  ------------------------------------------
345
  -- Width of the slave address bus (32 only)
346
  ------------------------------------------
347
  constant USER_SLV_AWIDTH                : integer              := C_SPLB_AWIDTH;
348
 
349
  ------------------------------------------
350
  -- Index for CS/CE
351
  ------------------------------------------
352
  constant USER_SLV_CS_INDEX              : integer              := 0;
353
  constant USER_SLV_CE_INDEX              : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
354
  constant INTR_CS_INDEX                  : integer              := 1;
355
  constant INTR_CE_INDEX                  : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
356
  constant USER_MEM0_CS_INDEX             : integer              := 2;
357
  constant USER_CS_INDEX                  : integer              := USER_MEM0_CS_INDEX;
358
 
359
  constant USER_CE_INDEX                  : integer              := USER_SLV_CE_INDEX;
360
 
361
  ------------------------------------------
362
  -- IP Interconnect (IPIC) signal declarations
363
  ------------------------------------------
364
  signal ipif_Bus2IP_Clk                : std_logic;
365
  signal ipif_Bus2IP_Reset              : std_logic;
366
  signal ipif_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
367
  signal ipif_IP2Bus_WrAck              : std_logic;
368
  signal ipif_IP2Bus_RdAck              : std_logic;
369
  signal ipif_IP2Bus_AddrAck            : std_logic;
370
  signal ipif_IP2Bus_Error              : std_logic;
371
  signal ipif_Bus2IP_Addr               : std_logic_vector(0 to C_SPLB_AWIDTH-1);
372
  signal ipif_Bus2IP_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
373
  signal ipif_Bus2IP_RNW                : std_logic;
374
  signal ipif_Bus2IP_BE                 : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
375
  signal ipif_Bus2IP_Burst              : std_logic;
376
  signal ipif_Bus2IP_BurstLength        : std_logic_vector(0 to log2(16*(C_SPLB_DWIDTH/8)));
377
  signal ipif_Bus2IP_WrReq              : std_logic;
378
  signal ipif_Bus2IP_RdReq              : std_logic;
379
  signal ipif_Bus2IP_CS                 : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
380
  signal ipif_Bus2IP_RdCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
381
  signal ipif_Bus2IP_WrCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
382
  signal intr_IPIF_Reg_Interrupts       : std_logic_vector(0 to 1);
383
  signal intr_IPIF_Lvl_Interrupts       : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
384
  signal intr_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
385
  signal intr_IP2Bus_WrAck              : std_logic;
386
  signal intr_IP2Bus_RdAck              : std_logic;
387
  signal intr_IP2Bus_Error              : std_logic;
388
  signal user_Bus2IP_RdCE               : std_logic_vector(0 to USER_NUM_REG-1);
389
  signal user_Bus2IP_WrCE               : std_logic_vector(0 to USER_NUM_REG-1);
390
  signal user_Bus2IP_BurstLength        : std_logic_vector(0 to 8)   := (others => '0');
391
  signal user_IP2Bus_AddrAck            : std_logic;
392
  signal user_IP2Bus_Data               : std_logic_vector(0 to USER_SLV_DWIDTH-1);
393
  signal user_IP2Bus_RdAck              : std_logic;
394
  signal user_IP2Bus_WrAck              : std_logic;
395
  signal user_IP2Bus_Error              : std_logic;
396
  signal user_IP2Bus_IntrEvent          : std_logic_vector(0 to USER_NUM_INTR-1);
397
 
398
  ------------------------------------------
399
  -- Component declaration for verilog user logic
400
  ------------------------------------------
401
  component user_logic is
402
    generic
403
    (
404
      -- ADD USER GENERICS BELOW THIS LINE ---------------
405
      --USER generics added here
406
      -- ADD USER GENERICS ABOVE THIS LINE ---------------
407
 
408
      -- DO NOT EDIT BELOW THIS LINE ---------------------
409
      -- Bus protocol parameters, do not add to or delete
410
      C_SLV_AWIDTH                   : integer              := 32;
411
      C_SLV_DWIDTH                   : integer              := 32;
412
      C_NUM_REG                      : integer              := 16;
413
      C_NUM_MEM                      : integer              := 2;
414
      C_NUM_INTR                     : integer              := 1
415
      -- DO NOT EDIT ABOVE THIS LINE ---------------------
416
    );
417
    port
418
    (
419
      -- ADD USER PORTS BELOW THIS LINE ------------------
420
      SPI_CLK                        : in  std_logic;
421
      SPI_MOSI                       : in  std_logic;
422
      SPI_MISO                       : out std_logic;
423
      SPI_SS                         : in  std_logic;
424
      -- ADD USER PORTS ABOVE THIS LINE ------------------
425
 
426
      -- DO NOT EDIT BELOW THIS LINE ---------------------
427
      -- Bus protocol ports, do not add to or delete
428
      Bus2IP_Clk                     : in  std_logic;
429
      Bus2IP_Reset                   : in  std_logic;
430
      Bus2IP_Addr                    : in  std_logic_vector(0 to C_SLV_AWIDTH-1);
431
      Bus2IP_CS                      : in  std_logic_vector(0 to C_NUM_MEM-1);
432
      Bus2IP_RNW                     : in  std_logic;
433
      Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
434
      Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
435
      Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
436
      Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
437
      Bus2IP_Burst                   : in  std_logic;
438
      Bus2IP_BurstLength             : in  std_logic_vector(0 to 8);
439
      Bus2IP_RdReq                   : in  std_logic;
440
      Bus2IP_WrReq                   : in  std_logic;
441
      IP2Bus_AddrAck                 : out std_logic;
442
      IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
443
      IP2Bus_RdAck                   : out std_logic;
444
      IP2Bus_WrAck                   : out std_logic;
445
      IP2Bus_Error                   : out std_logic;
446
      IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)
447
      -- DO NOT EDIT ABOVE THIS LINE ---------------------
448
    );
449
  end component user_logic;
450
 
451
begin
452
 
453
  ------------------------------------------
454
  -- instantiate plbv46_slave_burst
455
  ------------------------------------------
456
  PLBV46_SLAVE_BURST_I : entity plbv46_slave_burst_v1_01_a.plbv46_slave_burst
457
    generic map
458
    (
459
      C_ARD_ADDR_RANGE_ARRAY         => IPIF_ARD_ADDR_RANGE_ARRAY,
460
      C_ARD_NUM_CE_ARRAY             => IPIF_ARD_NUM_CE_ARRAY,
461
      C_SPLB_P2P                     => C_SPLB_P2P,
462
      C_CACHLINE_ADDR_MODE           => IPIF_CACHLINE_ADDR_MODE,
463
      C_WR_BUFFER_DEPTH              => IPIF_WR_BUFFER_DEPTH,
464
      C_BURSTLENGTH_TYPE             => IPIF_BURSTLENGTH_TYPE,
465
      C_SPLB_MID_WIDTH               => C_SPLB_MID_WIDTH,
466
      C_SPLB_NUM_MASTERS             => C_SPLB_NUM_MASTERS,
467
      C_SPLB_SMALLEST_MASTER         => C_SPLB_SMALLEST_MASTER,
468
      C_SPLB_AWIDTH                  => C_SPLB_AWIDTH,
469
      C_SPLB_DWIDTH                  => C_SPLB_DWIDTH,
470
      C_SIPIF_DWIDTH                 => IPIF_SLV_DWIDTH,
471
      C_INCLUDE_DPHASE_TIMER         => C_INCLUDE_DPHASE_TIMER,
472
      C_FAMILY                       => C_FAMILY
473
    )
474
    port map
475
    (
476
      SPLB_Clk                       => SPLB_Clk,
477
      SPLB_Rst                       => SPLB_Rst,
478
      PLB_ABus                       => PLB_ABus,
479
      PLB_UABus                      => PLB_UABus,
480
      PLB_PAValid                    => PLB_PAValid,
481
      PLB_SAValid                    => PLB_SAValid,
482
      PLB_rdPrim                     => PLB_rdPrim,
483
      PLB_wrPrim                     => PLB_wrPrim,
484
      PLB_masterID                   => PLB_masterID,
485
      PLB_abort                      => PLB_abort,
486
      PLB_busLock                    => PLB_busLock,
487
      PLB_RNW                        => PLB_RNW,
488
      PLB_BE                         => PLB_BE,
489
      PLB_MSize                      => PLB_MSize,
490
      PLB_size                       => PLB_size,
491
      PLB_type                       => PLB_type,
492
      PLB_lockErr                    => PLB_lockErr,
493
      PLB_wrDBus                     => PLB_wrDBus,
494
      PLB_wrBurst                    => PLB_wrBurst,
495
      PLB_rdBurst                    => PLB_rdBurst,
496
      PLB_wrPendReq                  => PLB_wrPendReq,
497
      PLB_rdPendReq                  => PLB_rdPendReq,
498
      PLB_wrPendPri                  => PLB_wrPendPri,
499
      PLB_rdPendPri                  => PLB_rdPendPri,
500
      PLB_reqPri                     => PLB_reqPri,
501
      PLB_TAttribute                 => PLB_TAttribute,
502
      Sl_addrAck                     => Sl_addrAck,
503
      Sl_SSize                       => Sl_SSize,
504
      Sl_wait                        => Sl_wait,
505
      Sl_rearbitrate                 => Sl_rearbitrate,
506
      Sl_wrDAck                      => Sl_wrDAck,
507
      Sl_wrComp                      => Sl_wrComp,
508
      Sl_wrBTerm                     => Sl_wrBTerm,
509
      Sl_rdDBus                      => Sl_rdDBus,
510
      Sl_rdWdAddr                    => Sl_rdWdAddr,
511
      Sl_rdDAck                      => Sl_rdDAck,
512
      Sl_rdComp                      => Sl_rdComp,
513
      Sl_rdBTerm                     => Sl_rdBTerm,
514
      Sl_MBusy                       => Sl_MBusy,
515
      Sl_MWrErr                      => Sl_MWrErr,
516
      Sl_MRdErr                      => Sl_MRdErr,
517
      Sl_MIRQ                        => Sl_MIRQ,
518
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
519
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
520
      IP2Bus_Data                    => ipif_IP2Bus_Data,
521
      IP2Bus_WrAck                   => ipif_IP2Bus_WrAck,
522
      IP2Bus_RdAck                   => ipif_IP2Bus_RdAck,
523
      IP2Bus_AddrAck                 => ipif_IP2Bus_AddrAck,
524
      IP2Bus_Error                   => ipif_IP2Bus_Error,
525
      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
526
      Bus2IP_Data                    => ipif_Bus2IP_Data,
527
      Bus2IP_RNW                     => ipif_Bus2IP_RNW,
528
      Bus2IP_BE                      => ipif_Bus2IP_BE,
529
      Bus2IP_Burst                   => ipif_Bus2IP_Burst,
530
      Bus2IP_BurstLength             => ipif_Bus2IP_BurstLength,
531
      Bus2IP_WrReq                   => ipif_Bus2IP_WrReq,
532
      Bus2IP_RdReq                   => ipif_Bus2IP_RdReq,
533
      Bus2IP_CS                      => ipif_Bus2IP_CS,
534
      Bus2IP_RdCE                    => ipif_Bus2IP_RdCE,
535
      Bus2IP_WrCE                    => ipif_Bus2IP_WrCE
536
    );
537
 
538
  ------------------------------------------
539
  -- instantiate interrupt_control
540
  ------------------------------------------
541
  INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
542
    generic map
543
    (
544
      C_NUM_CE                       => INTR_NUM_CE,
545
      C_NUM_IPIF_IRPT_SRC            => INTR_NUM_IPIF_IRPT_SRC,
546
      C_IP_INTR_MODE_ARRAY           => INTR_IP_INTR_MODE_ARRAY,
547
      C_INCLUDE_DEV_PENCODER         => INTR_INCLUDE_DEV_PENCODER,
548
      C_INCLUDE_DEV_ISC              => INTR_INCLUDE_DEV_ISC,
549
      C_IPIF_DWIDTH                  => IPIF_SLV_DWIDTH
550
    )
551
    port map
552
    (
553
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
554
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
555
      Bus2IP_Data                    => ipif_Bus2IP_Data,
556
      Bus2IP_BE                      => ipif_Bus2IP_BE,
557
      Interrupt_RdCE                 => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
558
      Interrupt_WrCE                 => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
559
      IPIF_Reg_Interrupts            => intr_IPIF_Reg_Interrupts,
560
      IPIF_Lvl_Interrupts            => intr_IPIF_Lvl_Interrupts,
561
      IP2Bus_IntrEvent               => user_IP2Bus_IntrEvent,
562
      Intr2Bus_DevIntr               => IP2INTC_Irpt,
563
      Intr2Bus_DBus                  => intr_IP2Bus_Data,
564
      Intr2Bus_WrAck                 => intr_IP2Bus_WrAck,
565
      Intr2Bus_RdAck                 => intr_IP2Bus_RdAck,
566
      Intr2Bus_Error                 => intr_IP2Bus_Error,
567
      Intr2Bus_Retry                 => open,
568
      Intr2Bus_ToutSup               => open
569
    );
570
 
571
  -- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
572
  intr_IPIF_Reg_Interrupts(0) <= '0';
573
  intr_IPIF_Reg_Interrupts(1) <= '0';
574
  intr_IPIF_Lvl_Interrupts(0) <= '0';
575
  intr_IPIF_Lvl_Interrupts(1) <= '0';
576
  intr_IPIF_Lvl_Interrupts(2) <= '0';
577
  intr_IPIF_Lvl_Interrupts(3) <= '0';
578
 
579
  ------------------------------------------
580
  -- instantiate User Logic
581
  ------------------------------------------
582
  USER_LOGIC_I : component user_logic
583
    generic map
584
    (
585
      -- MAP USER GENERICS BELOW THIS LINE ---------------
586
      --USER generics mapped here
587
      -- MAP USER GENERICS ABOVE THIS LINE ---------------
588
 
589
      C_SLV_AWIDTH                   => USER_SLV_AWIDTH,
590
      C_SLV_DWIDTH                   => USER_SLV_DWIDTH,
591
      C_NUM_REG                      => USER_NUM_REG,
592
      C_NUM_MEM                      => USER_NUM_MEM,
593
      C_NUM_INTR                     => USER_NUM_INTR
594
    )
595
    port map
596
    (
597
      -- MAP USER PORTS BELOW THIS LINE ------------------
598
      SPI_CLK                        => SPI_CLK,
599
      SPI_MOSI                       => SPI_MOSI,
600
      SPI_MISO                       => SPI_MISO,
601
      SPI_SS                         => SPI_SS,
602
      -- MAP USER PORTS ABOVE THIS LINE ------------------
603
 
604
      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
605
      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
606
      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
607
      Bus2IP_CS                      => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
608
      Bus2IP_RNW                     => ipif_Bus2IP_RNW,
609
      Bus2IP_Data                    => ipif_Bus2IP_Data,
610
      Bus2IP_BE                      => ipif_Bus2IP_BE,
611
      Bus2IP_RdCE                    => user_Bus2IP_RdCE,
612
      Bus2IP_WrCE                    => user_Bus2IP_WrCE,
613
      Bus2IP_Burst                   => ipif_Bus2IP_Burst,
614
      Bus2IP_BurstLength             => user_Bus2IP_BurstLength,
615
      Bus2IP_RdReq                   => ipif_Bus2IP_RdReq,
616
      Bus2IP_WrReq                   => ipif_Bus2IP_WrReq,
617
      IP2Bus_AddrAck                 => user_IP2Bus_AddrAck,
618
      IP2Bus_Data                    => user_IP2Bus_Data,
619
      IP2Bus_RdAck                   => user_IP2Bus_RdAck,
620
      IP2Bus_WrAck                   => user_IP2Bus_WrAck,
621
      IP2Bus_Error                   => user_IP2Bus_Error,
622
      IP2Bus_IntrEvent               => user_IP2Bus_IntrEvent
623
    );
624
 
625
  ------------------------------------------
626
  -- connect internal signals
627
  ------------------------------------------
628
  IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data ) is
629
  begin
630
 
631
    case ipif_Bus2IP_CS is
632
      when "1000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
633
      when "0100" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
634
      when "0010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
635
      when "0001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
636
      when others => ipif_IP2Bus_Data <= (others => '0');
637
    end case;
638
 
639
  end process IP2BUS_DATA_MUX_PROC;
640
 
641
  ipif_IP2Bus_AddrAck <= ipif_Bus2IP_Burst and user_IP2Bus_AddrAck;
642
  ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or intr_IP2Bus_WrAck;
643
  ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck;
644
  ipif_IP2Bus_Error <= user_IP2Bus_Error or intr_IP2Bus_Error;
645
 
646
  user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
647
  user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
648
 
649
  user_Bus2IP_BurstLength(8-log2(16*(C_SPLB_DWIDTH/8)) to 8) <= ipif_Bus2IP_BurstLength;
650
 
651
end IMP;

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