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[/] [vspi/] [trunk/] [src/] [spi_base/] [spiifc_twoclock.v] - Blame information for rev 14

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Line No. Rev Author Line
1 14 mjlyons
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: 
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// 
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// Create Date:    19:24:33 10/18/2011 
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// Design Name: 
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// Module Name:    spiifc 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module spiifc(
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  Reset,
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  SysClk,
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  SPI_CLK,
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  SPI_MISO,
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  SPI_MOSI,
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  SPI_SS,
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  txMemAddr,
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  txMemData,
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  rcMemAddr,
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  rcMemData,
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  rcMemWE,
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  debug_out
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  );
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  //
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  // Parameters
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  //
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  parameter AddrBits = 12;
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  // Defines
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  `define  CMD_READ_START   8'd1
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  `define  CMD_READ_MORE    8'd2
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  `define  CMD_WRITE_START  8'd3
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  `define  STATE_GET_CMD    8'd0
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  `define  STATE_READING    8'd1
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  `define  STATE_WRITING    8'd2
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  //
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  // Input/Output defs
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  //
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  input  Reset;
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  input  SysClk;
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  input  SPI_CLK;
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  output SPI_MISO;
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  input  SPI_MOSI;
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  input  SPI_SS;
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  output [AddrBits-1:0] txMemAddr;
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  input  [7:0]          txMemData;
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  output  [AddrBits-1:0] rcMemAddr;
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  output  [7:0]          rcMemData;
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  output                 rcMemWE;
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  output  [7:0]          debug_out;
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  //
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  // Registers
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  // 
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  reg  [ 7: 0] debug_reg;
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  reg  [ 7: 0] rcByteReg;
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  reg          rcStarted;
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  reg  [ 2: 0] rcBitIndexReg;
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  reg  [11: 0] rcMemAddrReg;
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  reg  [11: 0] rcMemAddrNext;
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  reg  [ 7: 0] rcMemDataReg;
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  reg          rcMemWEReg;
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  reg          ssPrev;
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  reg          ssFastToggleReg;
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  reg          ssSlowToggle;
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  reg          ssTurnOnReg;
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  reg          ssTurnOnHandled;
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  reg  [ 7: 0] cmd;
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  reg  [ 7: 0] stateReg;
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  reg  [11: 0] txMemAddrReg;
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  reg  [ 2: 0] txBitAddr;
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  //
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  // Wires
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  //
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  wire         rcByteValid;
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  wire [ 7: 0] rcByte;
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  wire         rcStarting;
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  wire [ 2: 0] rcBitIndex;
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  wire         ssTurnOn;
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  wire         ssFastToggle;
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  wire [ 7: 0] state;
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  wire         txMemAddrReset;
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  //
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  // Output assigns
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  //
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  assign debug_out = debug_reg;
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  assign rcMemAddr = rcMemAddrReg;
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  assign rcMemData = rcMemDataReg;
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  assign rcMemWE = rcMemWEReg;
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  assign txMemAddrReset = (rcByteValid && rcByte == `CMD_WRITE_START ? 1 : 0);
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  assign txMemAddr = (txMemAddrReset ? 0 : txMemAddrReg);
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  assign SPI_MISO = txMemData[txBitAddr];
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  assign ssFastToggle =
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      (ssPrev == 1 && SPI_SS == 0 ? ~ssFastToggleReg : ssFastToggleReg);
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  //
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  // Wire assigns
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  //
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  assign rcByteValid = rcStarted && rcBitIndex == 0;
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  assign rcByte = {rcByteReg[7:1], SPI_MOSI};
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  assign rcStarting = ssTurnOn;
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  assign rcBitIndex = (rcStarting ? 3'd7 : rcBitIndexReg);
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  assign ssTurnOn = ssSlowToggle ^ ssFastToggle;
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  assign state = (rcStarting ? `STATE_GET_CMD : stateReg);
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  initial begin
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    ssSlowToggle <= 0;
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  end
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  always @(posedge SysClk) begin
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    ssPrev <= SPI_SS;
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    if (Reset) begin
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      ssTurnOnReg <= 0;
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      ssFastToggleReg <= 0;
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    end else begin
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      if (ssPrev & (~SPI_SS)) begin
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        ssTurnOnReg <= 1;
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        ssFastToggleReg <= ~ssFastToggleReg;
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      end else if (ssTurnOnHandled) begin
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        ssTurnOnReg <= 0;
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      end
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    end
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  end
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  always @(posedge SPI_CLK) begin
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    ssSlowToggle <= ssFastToggle;
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    if (Reset) begin
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      // Resetting
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      rcByteReg <= 8'h00;
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      rcStarted <= 0;
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      rcBitIndexReg <= 3'd7;
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      ssTurnOnHandled <= 0;
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      debug_reg <= 8'hFF;
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    end else begin
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      // Not resetting
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      ssTurnOnHandled <= ssTurnOn;
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      stateReg <= state;
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      rcMemAddrReg <= rcMemAddrNext;
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      if (~SPI_SS) begin
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        rcByteReg[rcBitIndex] <= SPI_MOSI;
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        rcBitIndexReg <= rcBitIndex - 3'd1;
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        rcStarted <= 1;
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        // Update txBitAddr if writing out
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        if (`STATE_WRITING == state) begin
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          if (txBitAddr == 3'd1) begin
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            txMemAddrReg <= txMemAddr + 1;
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          end
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          txBitAddr <= txBitAddr - 1;
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        end
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      end
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      // We've just received a byte (well, currently receiving the last bit)
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      if (rcByteValid) begin
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        // For now, just display on LEDs
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        debug_reg <= rcByte;
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        if (`STATE_GET_CMD == state) begin
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          cmd <= rcByte;    // Will take effect next cycle
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          if (`CMD_READ_START == rcByte) begin
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            rcMemAddrNext <= 0;
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            stateReg <= `STATE_READING;
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          end else if (`CMD_READ_MORE == rcByte) begin
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            stateReg <= `STATE_READING;
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          end else if (`CMD_WRITE_START == rcByte) begin
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            txBitAddr <= 3'd7;
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            stateReg <= `STATE_WRITING;
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            txMemAddrReg <= txMemAddr;  // Keep at 0
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          end
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        end else if (`STATE_READING == state) begin
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          rcMemDataReg <= rcByte;
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          rcMemAddrNext <= rcMemAddr + 1;
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          rcMemWEReg <= 1;
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        end else if (`STATE_WRITING == state) begin
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          txBitAddr <= 3'd7;
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          stateReg <= `STATE_WRITING;
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        end
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      end else begin
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        // Not a valid byte
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        rcMemWEReg <= 0;
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      end // valid/valid' byte
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    end // Reset/Reset'
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  end
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endmodule

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