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[/] [vspi/] [trunk/] [test/] [spi_base/] [spiifc_tb_tx.v] - Blame information for rev 14

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Line No. Rev Author Line
1 14 mjlyons
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer:
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//
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// Create Date:   11:08:12 02/15/2012
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// Design Name:   spiifc
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// Module Name:   C:/workspace/robobees/hbp/fpga/spitest/pcores/spi_v1_00_a/hdl/verilog/spiifc_tb2.v
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// Project Name:  spi
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// Target Device:  
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// Tool versions:  
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// Description: 
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//
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// Verilog Test Fixture created by ISE for module: spiifc
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//
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// Dependencies:
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// 
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// 
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// This testbench tests sending data from the SPI IFC module to a 
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// master device, such as the Cheetah SPI/USB adapter.
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//
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////////////////////////////////////////////////////////////////////////////////
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module spiifc_tb_tx;
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        // Inputs
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        reg Reset;
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  reg SysClk;
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        reg SPI_CLK;
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        reg SPI_MOSI;
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        reg SPI_SS;
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        reg [7:0] txMemData;
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        // Outputs
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        wire SPI_MISO;
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        wire [11:0] txMemAddr;
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        wire [11:0] rcMemAddr;
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        wire [7:0] rcMemData;
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        wire rcMemWE;
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  wire [7:0] debug_out;
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        // Instantiate the Unit Under Test (UUT)
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        spiifc uut (
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                .Reset(Reset),
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    .SysClk(SysClk),
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                .SPI_CLK(SPI_CLK),
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                .SPI_MISO(SPI_MISO),
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                .SPI_MOSI(SPI_MOSI),
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                .SPI_SS(SPI_SS),
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                .txMemAddr(txMemAddr),
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                .txMemData(txMemData),
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                .rcMemAddr(rcMemAddr),
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                .rcMemData(rcMemData),
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                .rcMemWE(rcMemWE),
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    .debug_out(debug_out)
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        );
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  task recvByte;
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    input   [7:0] rcByte;
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    integer       rcBitIndex;
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    begin
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      $display("%g - spiifc receiving byte '0x%h'", $time, rcByte);
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      for (rcBitIndex = 0; rcBitIndex < 8; rcBitIndex = rcBitIndex + 1) begin
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        SPI_MOSI = rcByte[7 - rcBitIndex];
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        #100;
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      end
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    end
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  endtask
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  always begin
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    #20 SysClk = ~SysClk;
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  end
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  reg SPI_CLK_en;
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  initial begin
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    #310
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    SPI_CLK_en = 1;
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  end
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  always begin
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    #10
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    if (SPI_CLK_en) begin
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      #40 SPI_CLK = ~SPI_CLK;
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    end
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  end
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  integer fdRcBytes;
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  integer fdTxBytes;
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  integer dummy;
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  integer currRcByte;
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  integer rcBytesNotEmpty;
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  reg [8*10:1] rcBytesStr;
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        initial begin
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                // Initialize Inputs
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                Reset = 0;
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    SysClk = 0;
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                SPI_CLK = 0;
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    SPI_CLK_en = 0;
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                SPI_MOSI = 0;
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                SPI_SS = 1;
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                txMemData = 0;
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                // Wait 100 ns for global reset to finish
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                #100;
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    Reset = 1;
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    #100;
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    Reset = 0;
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    #100;
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                // Add stimulus here
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    SPI_SS = 0;
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    // For each byte, transmit its bits
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    fdRcBytes = $fopen("rc-bytes-tx-test.txt", "r");
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    rcBytesNotEmpty = 1;
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    while (rcBytesNotEmpty) begin
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      rcBytesNotEmpty = $fgets(rcBytesStr, fdRcBytes);
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      if (rcBytesNotEmpty) begin
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        dummy = $sscanf(rcBytesStr, "%x", currRcByte);
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        recvByte(currRcByte);
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      end
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    end
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    // Wrap it up.
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    SPI_SS = 1;
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    #1000;
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    $finish;
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        end
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endmodule
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