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[/] [wb2axi4/] [trunk/] [rtl/] [ifaces/] [axi_if.sv] - Blame information for rev 2

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Line No. Rev Author Line
1 2 alzhang
interface axi_if
2
  #(AXI_WID_WIDTH              = 8,
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    AXI_ADDR_WIDTH             = 32,
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    AXI_DATA_WIDTH             = 32,
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    AXI_PROT_WIDTH             = 3,
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    AXI_STB_WIDTH              = 4,
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    AXI_LEN_W                  = 4,
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    AXI_ASIZE_W                = 3,
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    AXI_ABURST_W               = 2,
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    AXI_ALOCK_W                = 2,
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    AXI_ACACHE_W               = 4,
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    AXI_RESP_W                 = 2
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  )
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  ();
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  //Write control channel signals
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  logic [AXI_WID_WIDTH  - 1:0] AWID    ;
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  logic [AXI_ADDR_WIDTH - 1:0] AWADDR  ;
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  logic [AXI_LEN_W      - 1:0] AWLEN   ;
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  logic [AXI_ASIZE_W    - 1:0] AWSIZE  ;
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  logic [AXI_ABURST_W   - 1:0] AWBURST ;
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  logic [AXI_ALOCK_W    - 1:0] AWLOCK  ;
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  logic [AXI_ACACHE_W   - 1:0] AWCACHE ;
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  logic [AXI_PROT_WIDTH - 1:0] AWPROT  ;
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  logic                        AWVALID ;
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  logic                        AWREADY ;
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  //write data channel signals
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  logic [AXI_WID_WIDTH  - 1:0] WID     ;
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  logic [AXI_DATA_WIDTH - 1:0] WDATA   ;
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  logic [AXI_STB_WIDTH  - 1:0] WSTRB   ;
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  logic                        WLAST   ;
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  logic                        WVALID  ;
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  logic                        WREADY  ;
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  //write response channel
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  logic [AXI_WID_WIDTH  - 1:0] BID     ;
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  logic [AXI_RESP_W     - 1:0] BRESP   ;
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  logic                        BVALID  ;
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  logic                        BREADY  ;
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  //Read control channel signals
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  logic [AXI_WID_WIDTH   - 1:0] ARID    ;
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  logic [AXI_ADDR_WIDTH  - 1:0] ARADDR  ;
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  logic [AXI_LEN_W       - 1:0] ARLEN   ;
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  logic [AXI_ASIZE_W     - 1:0] ARSIZE  ;
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  logic [AXI_ABURST_W    - 1:0] ARBURST ;
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  logic [AXI_ALOCK_W     - 1:0] ARLOCK  ;
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  logic [AXI_ACACHE_W    - 1:0] ARCACHE ;
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  logic [AXI_PROT_WIDTH  - 1:0] ARPROT  ;
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  logic                         ARVALID ;
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  logic                         ARREADY ;
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  //Read data channel signals
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  logic [AXI_WID_WIDTH  - 1:0] RID     ;
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  logic [AXI_DATA_WIDTH - 1:0] RDATA   ;
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  logic [AXI_RESP_W     - 1:0] RRESP   ;
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  logic                        RLAST   ;
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  logic                        RVALID  ;
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  logic                        RREADY  ;
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modport initiator (
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  //Write control channel signals
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  output AWID    ,
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  output AWADDR  ,
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  output AWLEN   ,
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  output AWSIZE  ,
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  output AWBURST ,
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  output AWLOCK  ,
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  output AWCACHE ,
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  output AWPROT  ,
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  output AWVALID ,
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  input  AWREADY ,
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  //write data channel signals
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  output WID     ,
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  output WDATA   ,
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  output WSTRB   ,
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  output WLAST   ,
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  output WVALID  ,
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  input  WREADY  ,
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  //write response channel
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  input  BID     ,
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  input  BRESP   ,
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  input  BVALID  ,
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  output BREADY  ,
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  //Read control channel signals
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  output ARID    ,
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  output ARADDR  ,
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  output ARLEN   ,
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  output ARSIZE  ,
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  output ARBURST ,
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  output ARLOCK  ,
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  output ARCACHE ,
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  output ARPROT  ,
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  output ARVALID ,
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  input  ARREADY ,
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  //Read data channel signals
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  input  RID     ,
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  input  RDATA   ,
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  input  RRESP   ,
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  input  RLAST   ,
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  input  RVALID  ,
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  output RREADY
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);
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modport target (
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  //Write control channel signals
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  input  AWID    ,
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  input  AWADDR  ,
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  input  AWLEN   ,
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  input  AWSIZE  ,
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  input  AWBURST ,
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  input  AWLOCK  ,
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  input  AWCACHE ,
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  input  AWPROT  ,
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  input  AWVALID ,
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  output AWREADY ,
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  //write data channel signals
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  input  WID     ,
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  input  WDATA   ,
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  input  WSTRB   ,
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  input  WLAST   ,
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  input  WVALID  ,
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  output WREADY  ,
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  //write response channel
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  output BID     ,
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  output BRESP   ,
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  output BVALID  ,
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  input  BREADY  ,
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  //Read control channel signals
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  input  ARID    ,
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  input  ARADDR  ,
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  input  ARLEN   ,
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  input  ARSIZE  ,
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  input  ARBURST ,
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  input  ARLOCK  ,
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  input  ARCACHE ,
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  input  ARPROT  ,
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  input  ARVALID ,
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  output ARREADY ,
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  //Read data channel signals
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  output RID     ,
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  output RDATA   ,
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  output RRESP   ,
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  output RLAST   ,
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  output RVALID  ,
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  input  RREADY
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);
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endinterface
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