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<h1>WisboneTK</h1>

<h2>Asyncronous master interface</h2>

<h3>Description</h3>

<strong>Asyncronous master interface</strong> is a simple parametrized bus converter. It acts as a slave device

for an asyncron CPU-like master device and converts cycles to wishbone compatible bus access cycles. That

type of bus interface is very common between slow to middle speed CPUs and MCUs available on the

market. With this core it is possible to use those Wishbone peripherials from those device. The core is 100% Wishbone compatible

with the <a href="wb_extensions.shtml">WishboneTK extensions</a>. The address and data bus-width can be configured

through compile-time parameters. The speed of the asyncronous bus is controled by the wait signal.

<h3>Wishbone datasheet</h3>

<table border>

<tr><th>Description</th><th>Specification</th></tr>

<tr><td>General Description             </td><td>Asyncronous master interface</td></tr>

<tr><td>Supported cycles                </td><td>Master read/write<br>Master block read/write<br>Master rmw</td></tr>

<tr><td>Data port size                  </td><td>variable</td></tr>

<tr><td>Data port granularity           </td><td>8-bit</td></tr>

<tr><td>Data port maximum operand size  </td><td>same as data port size</td></tr>

<tr><td>Data transfer ordering          </td><td>n/a</td></tr>

<tr><td>Data transfer sequencing        </td><td>n/a</td></tr>

<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>

        <table>

        <tr><th>Signal name</th><th>Wishbone equiv.</th></tr>

        <!-- SLAVE SIGNALS -->

        <tr><td>S_CLK_I       </td><td>CLK_I</td></tr>

        <tr><td>S_RST_I       </td><td>RST_I</td></tr>

        <tr><td>S_CYC_O       </td><td>CYC_O</td></tr>

        <tr><td>S_STB_O       </td><td>STB_O</td></tr>

        <tr><td>S_WE_O        </td><td>WE_O </td></tr>

        <tr><td>S_ACK_I       </td><td>ACK_I</td></tr>

        <tr><td>S_RTY_I       </td><td>RTY_I</td></tr>

        <tr><td>S_ERR_I       </td><td>ERR_I</td></tr>

        <tr><td>S_SEL_O(..)   </td><td>SEL_O()</td></tr>

        <tr><td>S_ADR_O(..)   </td><td>ADR_O()</td></tr>

        <tr><td>S_DAT_I(..)   </td><td>DAT_I()</td></tr>

        <tr><td>S_DAT_O(..)   </td><td>DAT_O()</td></tr>

        </table>

</table>

<h3>Parameter description</h3>

<table border>

<tr><th>Parameter name</th><th>Description</th></tr>

<tr><td>width</td><td>Data bus width</td></tr>

<tr><td>addr_width</td><td>Address bus width</td></tr>

</table>

<h3>Signal description</h3>

<table border>

<tr><th>Signal name</th><th>Description</th></tr>

<tr><td>S_CYC_O       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>

<tr><td>S_STB_O       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>

<tr><td>S_WE_O        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>

<tr><td>S_ACK_I       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>

<tr><td>S_RTY_I       </td><td>Wishbone retry signal. High indicates that slave requests retry of the <strong>last cycle in the block</strong>.</td></tr>

<tr><td>S_ERR_I       </td><td>Wishbone error signal. High indicates that slave cannot complete the <strong>last cycle in the block</strong>.</td></tr>

<tr><td>S_ADR_O(addr_width-2..0)  </td><td>Wishbone address bus signals</td></tr>

<tr><td>S_SEL_O(width/8-1..0) </td><td>Wishbone byte-selection signals</td></tr>

<tr><td>S_DAT_I(width-1..0)   </td><td>Wishbone data bus input (to slave direction) signals</td></tr>

<tr><td>S_DAT_O(width-1..0)   </td><td>Wishbone data bus output (to master direction) signals</td></tr>

<tr><th colspan="2">Aysncronous interfce signals</th></tr>

<tr><td>A_DATA(width-1..0)</td><td>Bidirectional data bus signals</td></tr>

<tr><td>A_ADDR(addr_width-1..0)</td><td>Address bus output signals</td></tr>

<tr><td>A_RDN</td><td>Active low read signal</td></tr>

<tr><td>A_WRN</td><td>Active low write signal</td></tr>

<tr><td>A_CEN</td><td>Active low chip-select signal</td></tr>

<tr><td>A_BYEN(addr_width/8-1..0)</td><td>Active-low byte-enable signals</td></tr>

<tr><td>A_WAITN</td><td>Active low wait signal</td></tr>

</td></tr></table>

<h2>Author & Maintainer</h2>

<p>

<a href="/people/tantos">Andras Tantos</a>

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