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<h1>WisboneTK</h1>

<h2>Asyncronous slave interface</h2>

<h3>Description</h3>

<strong>Asyncronous (SRAM-like) slave interface</strong> is a simple parametrized bus converter. It acts as a slave device

for a Wishbone bus master device and converts cycles on the wishbone bus to asyncronous access cycles, very similar to SRAM

access cycles. That type of bus interface is very common between slow to middle speed peripherial chips available on the

market. With this core it is possible to use those peripherials from a Wishbone master device. It is also possible to drive

high-speed SRAM devices and use them as off-core memory. The core is 100% Wishbone compatible

with the <a href="wb_extensions.shtml">WishboneTK extensions</a>. The address and data bus-width can be configured through compile-time

parameters. The speed of the external device can be set using input signals. A deactivation cycle is inserted after each access to

the core thus the maximum access speed is half of the speed of the Whisbone bus. Becouse deactivation cycle is completed after the

finish of the access cycle if the next access on the Whisbone bus is to another device zero wait-state operation can be achieved.

<h3>Wishbone datasheet</h3>

<table border>

<tr><th>Description</th><th>Specification</th></tr>

<tr><td>General Description             </td><td>Asyncronous (SRAM-like) slave interface</td></tr>

<tr><td>Supported cycles                </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw</td></tr>

<tr><td>Data port size                  </td><td>variable</td></tr>

<tr><td>Data port granularity           </td><td>8-bit</td></tr>

<tr><td>Data port maximum operand size  </td><td>same as data port size</td></tr>

<tr><td>Data transfer ordering          </td><td>n/a</td></tr>

<tr><td>Data transfer sequencing        </td><td>n/a</td></tr>

<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>

        <table>

        <tr><th>Signal name</th><th>Wishbone equiv.</th></tr>

        <!-- SLAVE SIGNALS -->

        <tr><td>CLK_I       </td><td>CLK_I</td></tr>

        <tr><td>RST_I       </td><td>RST_I</td></tr>

        <tr><td>STB_I       </td><td>STB_I</td></tr>

        <tr><td>WE_I        </td><td>WE_I </td></tr>

        <tr><td>ACK_O       </td><td>ACK_O</td></tr>

        <tr><td>SEL_I(..)   </td><td>SEL_I()</td></tr>

        <tr><td>ADR_I(..)   </td><td>ADR_I()</td></tr>

        <tr><td>DAT_I(..)   </td><td>DAT_I()</td></tr>

        <tr><td>DAT_O(..)   </td><td>DAT_O()</td></tr>

        </table>

</table>

<h3>Parameter description</h3>

<table border>

<tr><th>Parameter name</th><th>Description</th></tr>

<tr><td>width</td><td>Data bus width</td></tr>

<tr><td>addr_width</td><td>Address bus width</td></tr>

</table>

<h3>Signal description</h3>

<table border>

<tr><th>Signal name</th><th>Description</th></tr>

<tr><td>WAIT_STATE(3..0)</td><td>Number of wait-states to generate. 0 means 1 access and one deactivation cycle, no wait-states.</td></tr>

<tr><td>CLK_I       </td><td>Wishbone clock signal</td></tr>

<tr><td>RST_I       </td><td>Wishbone reset signal</td></tr>

<tr><td>STB_I       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>

<tr><td>WE_I        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>

<tr><td>ACK_O       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>

<tr><td>ACK_OI      </td><td>WhisboneTK acknowledge chain input signal</td></tr>

<tr><td>ADR_I(addr_width-1..0)     </td><td>Wishbone address bus signals</td></tr>

<tr><td>DAT_I(width-1..0)          </td><td>Wishbone data bus input (to slave direction) signals</td></tr>

<tr><td>DAT_O(width-1..0)          </td><td>Wishbone data bus output (to master direction) signals</td></tr>

<tr><td>DAT_OI(width-1..0)         </td><td>WhisboneTK data bus chain input signal</td></tr>

<tr><td>SEL_I(addr_width/8-1..0)   </td><td>Wishbone byte-selection signals</td></tr>

<tr><th colspan="2">Aysncronous interfce signals</th></tr>

<tr><td>A_DATA(width-1..0)</td><td>Bidirectional data bus signals</td></tr>

<tr><td>A_ADDR(addr_width-1..0)</td><td>Address bus output signals</td></tr>

<tr><td>A_RDN</td><td>Active low read signal</td></tr>

<tr><td>A_WRN</td><td>Active low write signal</td></tr>

<tr><td>A_CEN</td><td>Active low chip-select signal</td></tr>

<tr><td>A_BYEN(addr_width/8-1..0)</td><td>Active-low byte-enable signals</td></tr>

</td></tr></table>

<h2>Author & Maintainer</h2>

<p>

<a href="/people/tantos">Andras Tantos</a>

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