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<h1>WisboneTK</h1>

<h2>WishboneTK bus resizer</h2>

<h3>Description</h3>

<strong>WishboneTK bus resizer</strong> converts an X-bit Wishbone bus access to an Y-bit bus access.

The conversion is done by asserting the correct byte select signals and multiplex the data-bus according to the access.

The core cannot change the granularity of the access. It is 100% Wishbone compatible with the

<a href="wb_extensions.shtml">WishboneTK extensions</a>. The device contains only simple logic with no feed-back thus it is

asyncronous without any state. For this reason the CLK_I and RST_I signals, required for most Wishbone devies are not used.

The core can do up- and down-size. If master and slave interface has the same size, the core compiles into a bunch of wires

except for Wishbone extension gates.

<h3>Wishbone datasheet</h3>

<table border>

<tr><th>Description</th><th>Specification</th></tr>

<tr><td>General Description             </td><td>Bus up-sizer.</td></tr>

<tr><td>Supported cycles                </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw<br>

                                                                                                 Master read/write<br>Master block read/write<br>Master rmw<br></td></tr>

<tr><td>Data port size                  </td><td>Configurable on both slave and master side</td></tr>

<tr><td>Data port granularity           </td><td>8-bit</td></tr>

<tr><td>Data port maximum operand size  </td><td>Bus size</td></tr>

<tr><td>Data transfer ordering          </td><td>Little and big endien</td></tr>

<tr><td>Data transfer sequencing        </td><td>n/a</td></tr>

<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>

        <table>

        <tr><th>Signal name</th><th>Wishbone equiv.</th></tr>

        <tr><th colspan="2">Signals to connect to master</th></tr>

        <tr><td>M_CYC_I       </td><td>CYC_I</td></tr>

        <tr><td>M_STB_I       </td><td>STB_I</td></tr>

        <tr><td>M_WE_I        </td><td>WE_I </td></tr>

        <tr><td>M_ACK_O       </td><td>ACK_O</td></tr>

        <tr><td>M_RTY_O       </td><td>RTY_O</td></tr>

        <tr><td>M_ERR_O       </td><td>ERR_O</td></tr>

        <tr><td>M_SEL_I(..)   </td><td>SEL_I()</td></tr>

        <tr><td>M_ADR_I(..)   </td><td>ADR_I()</td></tr>

        <tr><td>M_DAT_I(..)   </td><td>DAT_I()</td></tr>

        <tr><td>M_DAT_O(..)   </td><td>DAT_O()</td></tr>

        <tr><th colspan="2">Signals to connect to slave</th></tr>

        <tr><td>S_CYC_O       </td><td>CYC_O</td></tr>

        <tr><td>S_STB_O       </td><td>STB_O</td></tr>

        <tr><td>S_WE_O        </td><td>WE_O </td></tr>

        <tr><td>S_ACK_I       </td><td>ACK_I</td></tr>

        <tr><td>S_RTY_I       </td><td>RTY_I</td></tr>

        <tr><td>S_ERR_I       </td><td>ERR_I</td></tr>

        <tr><td>S_SEL_O(..)   </td><td>SEL_O()</td></tr>

        <tr><td>S_ADR_O(..)   </td><td>ADR_O()</td></tr>

        <tr><td>S_DAT_I(..)   </td><td>DAT_I()</td></tr>

        <tr><td>S_DAT_O(..)   </td><td>DAT_O()</td></tr>

        </table>

</table>

<h3>Parameter description</h3>

<table border>

<tr><th>Parameter name</th><th>Description</th></tr>

<tr><td>m_bus_width   </td><td>Master data bus width.</td></tr>

<tr><td>m_addr_width  </td><td>Master address bus width</td></tr>

<tr><td>s_bus_width   </td><td>Slave data bus width.</td></tr>

<tr><td>little_endien </td><td>True for little endien, False for big endien address decoding</td></tr>

</table>

<h3>Signal description</h3>

<table border>

<tr><th>Signal name</th><th>Description</th></tr>

<tr><th colspan="2">Signals to connect to master</th></tr>

<tr><td>M_CYC_I       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>

<tr><td>M_STB_I       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>

<tr><td>M_WE_I        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>

<tr><td>M_ACK_O       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>

<tr><td>M_ACK_OI      </td><td>WhisboneTK acknowledge chain input signal</td></tr>

<tr><td>M_RTY_O       </td><td>Wishbone retry signal. High indicates that slave requests retry of the <strong>last cycle in the block</strong>.</td></tr>

<tr><td>M_RTY_OI      </td><td>WhisboneTK retry chain input signal</td></tr>

<tr><td>M_ERR_O       </td><td>Wishbone error signal. High indicates that slave cannot complete the <strong>last cycle in the block</strong>.</td></tr>

<tr><td>M_ERR_OI      </td><td>WhisboneTK error chain input signal</td></tr>

<tr><td>M_ADR_I(m_addr_width-1..0)  </td><td>Wishbone address bus signals</td></tr>

<tr><td>M_SEL_I(m_bus_width/8-1..0) </td><td>Wishbone byte-selection signals</td></tr>

<tr><td>M_DAT_I(m_bus_width-1..0)   </td><td>Wishbone data bus input (to slave direction) signals</td></tr>

<tr><td>M_DAT_O(m_bus_width-1..0)   </td><td>Wishbone data bus output (to master direction) signals</td></tr>

<tr><td>M_DAT_OI(m_bus_width-1..0)  </td><td>WhisboneTK data bus chain input signal</td></tr>

<tr><th colspan="2">Signals to connect to slave</th></tr>

<tr><td>S_CYC_O       </td><td>Wishbone cycle signal. High value frames blocks of access</td></tr>

<tr><td>S_STB_O       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>

<tr><td>S_WE_O        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>

<tr><td>S_ACK_I       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>

<tr><td>S_RTY_I       </td><td>Wishbone retry signal. High indicates that slave requests retry of the <strong>last cycle in the block</strong>.</td></tr>

<tr><td>S_ERR_I       </td><td>Wishbone error signal. High indicates that slave cannot complete the <strong>last cycle in the block</strong>.</td></tr>

<tr><td>S_ADR_O(m_addr_width-2..0)  </td><td>Wishbone address bus signals</td></tr>

<tr><td>S_SEL_O(s_bus_width/8-1..0) </td><td>Wishbone byte-selection signals</td></tr>

<tr><td>S_DAT_I(s_bus_width-1..0)   </td><td>Wishbone data bus input (to slave direction) signals</td></tr>

<tr><td>S_DAT_O(s_bus_width-1..0)   </td><td>Wishbone data bus output (to master direction) signals</td></tr>

</td></tr></table>

<h2>Author & Maintainer</h2>

<p>

<a href="/people/tantos">Andras Tantos</a>

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