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<h1>WisboneTK</h1>

<h2>Single-port RAM</h2>

<h3>Description</h3>

The <strong>Single-port RAM</strong> is a small, fast, on-chip RAM implementation utilizing the embedded RAM blocks

available in many FPGA architectures. Although it can be paramerized to arbitrary size and width it won't fit into

a physical device if larger than a few K-bits. If you need larger memories for your design consider using an

external memory chip and interfacing it to the Wishbone bus with one of the many interface circuits available.

Also you can consider using another Wishbone-compatible single- and dual-ported RAM implementation by

<a href="mailto:khatib@ieee.org_NOSPAM">Jamil Khatib</a> which you can find

<a href="/cores/memory_cores/">here</a>.

The core is 100% Wishbone compatible with the <a href="wb_extensions.shtml">WishboneTK extensions</a>.

The core allows zero-wait-state operation.

<h3>Wishbone datasheet</h3>

<table border>

<tr><th>Description</th><th>Specification</th></tr>

<tr><td>General Description             </td><td>Single-port RAM</td></tr>

<tr><td>Supported cycles                </td><td>Slave read/write<br>Slave block read/write<br>Slave rmw</td></tr>

<tr><td>Data port size                  </td><td>variable</td></tr>

<tr><td>Data port granularity           </td><td>same as port size</td></tr>

<tr><td>Data port maximum operand size  </td><td>same as data port size</td></tr>

<tr><td>Data transfer ordering          </td><td>n/a</td></tr>

<tr><td>Data transfer sequencing        </td><td>n/a</td></tr>

<tr><td>Supported signal list and cross reference to equivalent Wishbone signals</td><td>

        <table>

        <tr><th>Signal name</th><th>Wishbone equiv.</th></tr>

        <tr><td>CLK_I       </td><td>CLK_I</td></tr>

        <tr><td>CYC_I       </td><td>CYC_I</td></tr>

        <tr><td>STB_I       </td><td>STB_I</td></tr>

        <tr><td>WE_I        </td><td>WE_I </td></tr>

        <tr><td>ACK_O       </td><td>ACK_O</td></tr>

        <tr><td>ADR_I(..)   </td><td>ADR_I()</td></tr>

        <tr><td>DAT_I(..)   </td><td>DAT_I()</td></tr>

        <tr><td>DAT_O(..)   </td><td>DAT_O()</td></tr>

        </table>

</table>

<h3>Parameter description</h3>

<table border>

<tr><th>Parameter name</th><th>Description</th></tr>

<tr><td>data_width</td><td>Data bus width</td></tr>

<tr><td>addr_width</td><td>Address bus width</td></tr>

</table>

<h3>Signal description</h3>

<table border>

<tr><th>Signal name</th><th>Description</th></tr>

<tr><td>CLK_I       </td><td>Wishbone clock signal</td></tr>

<tr><td>CYC_I       </td><td>Wishbone active cycle indication signal. High value indicates an active Wishbone cycle on the bus</td></tr>

<tr><td>STB_I       </td><td>Wishbone strobe signal. High value indicates cycle to this particular device</td></tr>

<tr><td>WE_I        </td><td>Wishbone write enable signal. High indicates data flowing from master to slave</td></tr>

<tr><td>ACK_O       </td><td>Wishbone acknowledge signal. High indicates that slave finished operation sucessfully</td></tr>

<tr><td>ACK_OI      </td><td>WhisboneTK acknowledge chain input signal</td></tr>

<tr><td>ADR_I(addr_width-1..0)     </td><td>Wishbone address bus signals</td></tr>

<tr><td>DAT_I(data_width-1..0)     </td><td>Wishbone data bus input (to slave direction) signals</td></tr>

<tr><td>DAT_O(data_width-1..0)     </td><td>Wishbone data bus output (to master direction) signals</td></tr>

<tr><td>DAT_OI(data_width-1..0)    </td><td>WhisboneTK data bus chain input signal</td></tr>

</td></tr></table>

<h2>Author & Maintainer</h2>

<p>

<a href="/people/tantos">Andras Tantos</a>

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