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<link REL="stylesheet" TYPE="text/css" HREF="/people/tantos/styles.css">
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<h1>WisboneTK</h1>
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<h2>Test package</h2>
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<h3>Description</h3>
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The WishboneTK test package contains some procedures that can become useful when it comes to testing. These facilities might
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not sythetize and that's not their purpose. The procedures contained in this package can read, write and check various values
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to/from Wishbone slave devices. The procedures handle all handshaking required between master and slave devices. Currently
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the following procedures are available:
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<ul>
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        <li><a href="#wr_chk_val">wr_chk_val</a></li>
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        <li><a href="#wr_val">wr_val</a></li>
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        <li><a href="#rd_val">rd_val</a></li>
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        <li><a href="#chk_val">chk_val</a></li>
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</ul>
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<a name="wr_chk_val"></a><h3>wr_chk_val</h3>
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The procedure issues a write cycle using the wires passed to the function to the address and with the data specified.
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Than it issues a read cycle to the same address and compares the value with the data specified. It the two values are
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not the same an assert (severity ERROR) is generated.
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<p>
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The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals.
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Later versions probably will add this functionality.
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<h4>Paramters</h4>
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<table border>
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<tr><th>Name</th><th>Direction</th><th>Specification</th></tr>
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<tr><td>CLK_I</td><td>IN </td><td>Wishbone clock signal</td></tr>
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<tr><td>ADR_I</td><td>OUT</td><td>Wishbone address bus</td></tr>
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<tr><td>DAT_O</td><td>IN </td><td>Wishbone data bus slave->master direction</td></tr>
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<tr><td>DAT_I</td><td>OUT</td><td>Wishbone data bus master->slave direction</td></tr>
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<tr><td>WE_I </td><td>OUT</td><td>Wishbone write enable signal</td></tr>
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<tr><td>CYC_I</td><td>OUT</td><td>Wishbone active bus-cycle signal</td></tr>
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<tr><td>STB_I</td><td>OUT</td><td>Wishbone strobe signal</td></tr>
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<tr><td>ACK_O</td><td>IN </td><td>Wishbone acknowledge signal</td></tr>
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<tr><td>ADDR </td><td>IN </td><td>Address to write to / read from</td></tr>
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<tr><td>DATA </td><td>IN </td><td>Data to be written / checked against</td></tr>
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</table>
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<a name="wr_val"></a><h3>wr_val</h3>
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The procedure issues a write cycle using the wires passed to the function to the address and with the data specified.
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<p>
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The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals.
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Later versions probably will add this functionality.
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<h4>Paramters</h4>
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<table border>
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<tr><th>Name</th><th>Direction</th><th>Specification</th></tr>
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<tr><td>CLK_I</td><td>IN </td><td>Wishbone clock signal</td></tr>
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<tr><td>ADR_I</td><td>OUT</td><td>Wishbone address bus</td></tr>
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<tr><td>DAT_O</td><td>IN </td><td>Wishbone data bus slave->master direction</td></tr>
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<tr><td>DAT_I</td><td>OUT</td><td>Wishbone data bus master->slave direction</td></tr>
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<tr><td>WE_I </td><td>OUT</td><td>Wishbone write enable signal</td></tr>
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<tr><td>CYC_I</td><td>OUT</td><td>Wishbone active bus-cycle signal</td></tr>
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<tr><td>STB_I</td><td>OUT</td><td>Wishbone strobe signal</td></tr>
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<tr><td>ACK_O</td><td>IN </td><td>Wishbone acknowledge signal</td></tr>
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<tr><td>ADDR </td><td>IN </td><td>Address to write to</td></tr>
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<tr><td>DATA </td><td>IN </td><td>Data to be written</td></tr>
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</table>
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<a name="rd_val"></a><h3>rd_val</h3>
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The procedure issues a read cycle to the address specified. It copies the value read from the Wishbone bus to the
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data paramter.
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<p>
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The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals.
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Later versions probably will add this functionality.
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<h4>Paramters</h4>
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<table border>
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<tr><th>Name</th><th>Direction</th><th>Specification</th></tr>
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<tr><td>CLK_I</td><td>IN </td><td>Wishbone clock signal</td></tr>
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<tr><td>ADR_I</td><td>OUT</td><td>Wishbone address bus</td></tr>
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<tr><td>DAT_O</td><td>IN </td><td>Wishbone data bus slave->master direction</td></tr>
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<tr><td>DAT_I</td><td>OUT</td><td>Wishbone data bus master->slave direction</td></tr>
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<tr><td>WE_I </td><td>OUT</td><td>Wishbone write enable signal</td></tr>
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<tr><td>CYC_I</td><td>OUT</td><td>Wishbone active bus-cycle signal</td></tr>
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<tr><td>STB_I</td><td>OUT</td><td>Wishbone strobe signal</td></tr>
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<tr><td>ACK_O</td><td>IN </td><td>Wishbone acknowledge signal</td></tr>
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<tr><td>ADDR </td><td>IN </td><td>Address to read from</td></tr>
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<tr><td>DATA </td><td>OUT</td><td>Returns data read from the Wishbone bus</td></tr>
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</table>
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<a name="chk_val"></a><h3>chk_val</h3>
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The procedure issues a read cycle to the address specified and compares the value read from the bus with the data specified.
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It the two values are not the same an assert (severity ERROR) is generated.
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<p>
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The procedure cannot handle ganularity other than the width of the bus. It also cannot hadle ERR and RTY handshake signals.
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Later versions probably will add this functionality.
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<h4>Paramters</h4>
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<table border>
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<tr><th>Name</th><th>Direction</th><th>Specification</th></tr>
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<tr><td>CLK_I</td><td>IN </td><td>Wishbone clock signal</td></tr>
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<tr><td>ADR_I</td><td>OUT</td><td>Wishbone address bus</td></tr>
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<tr><td>DAT_O</td><td>IN </td><td>Wishbone data bus slave->master direction</td></tr>
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<tr><td>DAT_I</td><td>OUT</td><td>Wishbone data bus master->slave direction</td></tr>
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<tr><td>WE_I </td><td>OUT</td><td>Wishbone write enable signal</td></tr>
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<tr><td>CYC_I</td><td>OUT</td><td>Wishbone active bus-cycle signal</td></tr>
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<tr><td>STB_I</td><td>OUT</td><td>Wishbone strobe signal</td></tr>
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<tr><td>ACK_O</td><td>IN </td><td>Wishbone acknowledge signal</td></tr>
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<tr><td>ADDR </td><td>IN </td><td>Address to read from</td></tr>
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<tr><td>DATA </td><td>IN </td><td>Data to be checked against</td></tr>
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</table>
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<!--
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<h2>Other resources</h2>
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You can check the <a href="xxx">Wishbone master and slave devices</a>. These cores written in Verilog are also
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well-suited for test-benches.
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-->
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<h2>Author & Maintainer</h2>
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<p>
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<a href="/people/tantos">Andras Tantos</a>
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