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[/] [xilinx_virtex_fp_library/] [trunk/] [DualPathFPAdderMappedConversions/] [rounding.v] - Blame information for rev 11

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1 11 constantin
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: 
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// 
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// Create Date:    16:09:49 11/04/2013 
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// Design Name: 
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// Module Name:    rounding 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
12
// Description: A  B
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module rounding #(      parameter SIZE_MOST_S_MANTISSA = 24,
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                                        parameter SIZE_LEAST_S_MANTISSA= 25)
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                                (       input [SIZE_MOST_S_MANTISSA - 1 : 0] unrounded_mantissa,
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                                        input [SIZE_LEAST_S_MANTISSA- 1 : 0] dummy_bits,
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                                        output[SIZE_MOST_S_MANTISSA - 1 : 0] rounded_mantissa);
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        wire g, sticky, round_dec;
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        assign g = dummy_bits[SIZE_LEAST_S_MANTISSA - 1];
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        assign sticky = |(dummy_bits[SIZE_LEAST_S_MANTISSA - 2 : 0]);
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        assign round_dec = g & (unrounded_mantissa[0] | sticky);
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        assign rounded_mantissa = unrounded_mantissa + round_dec;
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endmodule

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