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[/] [xilinx_virtex_fp_library/] [trunk/] [GeneralPrecMAFMappedConversions/] [sign_computation.v] - Blame information for rev 19

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1 19 constantin
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: 
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// 
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// Create Date:    03:10:41 02/26/2014 
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// Design Name: 
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// Module Name:    sign_computation 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module sign_computation(        input eff_op,
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                                                        input s_a_number,
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                            input s_b_number,
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                            input a_greater_exponent,
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                                                        input b_greater_exponent,
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                                                        input adder_mantissa_ovf,
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                                                        output sign);
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        wire [4:0] sign_cases;
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        reg intermediar_sign;
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        assign sign_cases = {eff_op, s_a_number, s_b_number, a_greater_exponent, b_greater_exponent};
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        always
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                @(*)
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        begin
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                case (sign_cases)
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                        5'b00000:       intermediar_sign = 1'b0;
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                        5'b00001:       intermediar_sign = 1'b0;
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                        5'b00010:       intermediar_sign = 1'b0;
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                        5'b10000:       intermediar_sign = ~adder_mantissa_ovf;
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                        5'b10001:       intermediar_sign = 1'b0;
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                        5'b10010:       intermediar_sign = 1'b1;
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                        5'b10100:       intermediar_sign = ~adder_mantissa_ovf;
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                        5'b10101:       intermediar_sign = 1'b0;
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                        5'b10110:       intermediar_sign = 1'b1;
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                        5'b00100:       intermediar_sign = 1'b0;
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                        5'b00101:       intermediar_sign = 1'b0;
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                        5'b00110:       intermediar_sign = 1'b0;
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                        5'b11000:       intermediar_sign = adder_mantissa_ovf;
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                        5'b11001:       intermediar_sign = 1'b1;
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                        5'b11010:       intermediar_sign = 1'b0;
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                        5'b01000:       intermediar_sign = 1'b1;
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                        5'b01001:       intermediar_sign = 1'b1;
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                        5'b01010:       intermediar_sign = 1'b1;
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                        5'b01100:       intermediar_sign = 1'b1;
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                        5'b01101:       intermediar_sign = 1'b1;
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                        5'b01110:       intermediar_sign = 1'b1;
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                        5'b11100:       intermediar_sign = adder_mantissa_ovf;
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                        5'b11101:       intermediar_sign = 1'b1;
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                        5'b11110:       intermediar_sign = 1'b0;
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                        default: intermediar_sign = 1'b1;
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                endcase
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        end
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        assign sign = intermediar_sign;
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endmodule

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