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[/] [xilinx_virtex_fp_library/] [trunk/] [HalfPrecision/] [d_ff.vhd] - Blame information for rev 2

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1 2 bigsascha3
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    09:39:58 02/04/2013 
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-- Design Name: 
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-- Module Name:    d_ff - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity d_ff is
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        generic(N : integer := 8);
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        port ( clk, rst : in std_logic;
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                        d: in std_logic_vector( N - 1 downto 0);
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                        q : out std_logic_vector( N - 1 downto 0));
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end d_ff;
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architecture Behavioral of d_ff is
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begin
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        process (clk, rst)
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        begin
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                if(rst = '1') then
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                        q <= (others => '0');
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                elsif (clk'event and clk = '1') then
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                        q<= d;
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                end if;
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        end process;
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end Behavioral;
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