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[/] [xilinx_virtex_fp_library/] [trunk/] [HalfPrecision/] [exp_add_norm.vhd] - Blame information for rev 2

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1 2 bigsascha3
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    09:14:54 02/07/2013 
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-- Design Name: 
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-- Module Name:    exp_add_norm - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity exp_add_norm is
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        generic (SIZE_EXP : natural := 5;
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                                PIPELINE : natural := 0);
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        port (clk, rst : in std_logic;
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                        exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);
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                        ovf_norm : in std_logic_vector (1 downto 0);
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                        ovf_rnd : in std_logic;
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                        exp_out : out std_logic_vector(SIZE_EXP - 1 downto 0));
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end exp_add_norm;
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architecture Behavioral of exp_add_norm is
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        component d_ff
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                generic (N: natural := 8);
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                port (clk, rst : in std_logic;
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                                d : in std_logic_vector (N-1 downto 0);
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                                q : out std_logic_vector (N-1 downto 0));
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        end component;
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        signal exp_add_d, exp_add_q : std_logic_vector(SIZE_EXP - 1  downto 0);
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begin
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        exp_add_d <= exp_in + ovf_norm;
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        exp_out <= exp_add_q + ovf_rnd;
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        NO_LATCH:
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                if PIPELINE = 0 generate
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                        no_ins : exp_add_q <= exp_add_d;
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                end generate;
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        LATCH :
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                if PIPELINE = 1 generate
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                        ins : d_ff generic map (SIZE_EXP)
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                                                port map (clk, rst, exp_add_d, exp_add_q);
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                end generate;
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end Behavioral;
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