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[/] [xilinx_virtex_fp_library/] [trunk/] [HalfPrecision/] [round_norm.vhd] - Blame information for rev 2

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1 2 bigsascha3
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    08:44:49 02/05/2013 
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-- Design Name: 
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-- Module Name:    round_norm - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity round_norm is
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        generic ( OPERAND_SIZE : natural := 24;
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                                MANTISSA_SIZE : natural := 12;
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                                RND_PREC : natural := 0; --0 RNE, 1 Trunc
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                                PIPELINE: natural := 1); -- 0 - no pipeline
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        port ( clk, rst : std_logic;
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                        mantissa_in : in std_logic_vector (OPERAND_SIZE + 1 downto 0);
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                        mantissa_out: out std_logic_vector (MANTISSA_SIZE - 1 downto 0);
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                        neg : in std_logic;
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                        ovf_norm : out std_logic_vector(1 downto 0);
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                        ovf_rnd : out std_logic);
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end round_norm;
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architecture Behavioral of round_norm is
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        component d_ff
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                generic (N: natural := 8);
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                port (clk, rst : in std_logic;
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                                d : in std_logic_vector (N-1 downto 0);
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                                q : out std_logic_vector (N-1 downto 0));
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        end component;
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        signal l,g, s: std_logic;
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        signal rnd_dec_d, rnd_dec_q : std_logic_vector (0 downto 0);
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        signal mantissa_temp_norm : std_logic_vector (OPERAND_SIZE - 1 downto 0);
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        signal mantissa_add_d : std_logic_vector (MANTISSA_SIZE downto 0);
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        signal mantissa_add_q : std_logic_vector (MANTISSA_SIZE downto 0);
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        signal mantissa_rnd : std_logic_vector (MANTISSA_SIZE downto 0);
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begin
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        ovf_norm <= "10" when mantissa_in (OPERAND_SIZE + 1) = '1' else
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                                        "01" when mantissa_in (OPERAND_SIZE) = '1' else
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                                        "00";
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        mantissa_temp_norm <= mantissa_in(OPERAND_SIZE + 1 downto 2) when mantissa_in(OPERAND_SIZE + 1) = '1' else
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                                                                mantissa_in(OPERAND_SIZE downto 1) when mantissa_in(OPERAND_SIZE ) = '1' else
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                                                                mantissa_in (OPERAND_SIZE - 1 downto 0);
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        RNE:
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        if(RND_PREC = 0) generate
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                s <=    '0' when (mantissa_temp_norm (OPERAND_SIZE - 1 - MANTISSA_SIZE - 1 downto 0) =  (OPERAND_SIZE - 1 - MANTISSA_SIZE - 1 downto 0 => '0') and mantissa_in(0) = '0' and mantissa_in (1) = '0') else
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                                '1';
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                l <= mantissa_temp_norm (OPERAND_SIZE - 1 - MANTISSA_SIZE + 1);
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                g <= mantissa_temp_norm (OPERAND_SIZE - 1 - MANTISSA_SIZE);
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                rnd_dec_d (0)<= g and (l or s);
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        end generate;
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        TRUNC:
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        if(RND_PREC = 1) generate
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                s <=    '0';
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                l <= mantissa_temp_norm (OPERAND_SIZE - 1 - MANTISSA_SIZE + 1);
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                g <= '0';
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                rnd_dec_d (0)<= g and (l or s);
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        end generate;
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        mantissa_add_d <= "0" & mantissa_temp_norm (OPERAND_SIZE - 1 downto OPERAND_SIZE - 1 - MANTISSA_SIZE + 1);
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        mantissa_rnd <= mantissa_add_q + rnd_dec_q;
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        ovf_rnd <= mantissa_rnd (MANTISSA_SIZE);
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        mantissa_out <= mantissa_rnd (MANTISSA_SIZE downto 1) when mantissa_rnd (MANTISSA_SIZE) = '1' else
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                                                mantissa_rnd (MANTISSA_SIZE - 1 downto 0);
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        PIPELINE_INS:
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                if PIPELINE /= 0 generate
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                        MANTISSA_DFF : d_ff generic map (N => MANTISSA_SIZE + 1)
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                                                                                port map (clk => clk, rst => rst,
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                                                                                                        d => mantissa_add_d, q => mantissa_add_q);
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                        RND_DEC: d_ff generic map (N => 1)
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                                                        port map (clk => clk, rst => rst,
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                                                                                d => rnd_dec_d, q=> rnd_dec_q);
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                end generate;
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        NO_PIPELINE:
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                if PIPELINE = 0 generate
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                        mantissa_add_q <= mantissa_add_d;
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                        rnd_dec_q <= rnd_dec_d;
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                end generate;
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end Behavioral;
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