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[/] [xilinx_virtex_fp_library/] [trunk/] [HalfPrecision/] [shift.vhd] - Blame information for rev 2

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1 2 bigsascha3
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    19:08:09 02/02/2013 
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-- Design Name: 
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-- Module Name:    right_shift - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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use IEEE.math_real.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity shift is
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        generic (INPUT_SIZE : natural := 13;
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                                SHIFT_SIZE : natural := 4;
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                                OUTPUT_SIZE : natural := 24;
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                                DIRECTION : natural := 1;  -- 1 for left shift; 0 for right shift
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                                PIPELINE : natural := 1; -- 1 if pipelined , 0 no pipeline
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                                POSITION : std_logic_vector(7 downto 0) := "00000100"); -- the position of pipeline registers
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        port (clk, rst : in std_logic;
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                        a : in std_logic_vector (INPUT_SIZE - 1 downto 0);
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                        arith : in std_logic;
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                        shft : in std_logic_vector (SHIFT_SIZE - 1 downto 0);
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                        shifted_a : out std_logic_vector (OUTPUT_SIZE - 1 downto 0));
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end shift;
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architecture Behavioral of shift is
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        type shift_results is array (0 to SHIFT_SIZE) of std_logic_vector(OUTPUT_SIZE - 1 downto 0);
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        component d_ff
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                generic (N: natural := 8);
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                port (clk, rst : in std_logic;
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                                d : in std_logic_vector (N-1 downto 0);
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                                q : out std_logic_vector (N-1 downto 0));
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        end component;
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        signal a_temp_d : shift_results;
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        signal a_temp_q : shift_results;
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begin
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        a_temp_q (0) (OUTPUT_SIZE - 1 downto OUTPUT_SIZE - INPUT_SIZE) <= a;
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        a_temp_q (0) (OUTPUT_SIZE - 1 - INPUT_SIZE downto 0) <= (others => arith);
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        BARREL_SHIFTER_GENERATION:
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                for i in 0 to SHIFT_SIZE - 1 generate
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                        LEFT : if DIRECTION = 1 generate
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                                                MUX_GEN_L:
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                                                        for j in 0 to OUTPUT_SIZE - 1 generate
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                                                                ZERO_INS_L:
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                                                                        if j < 2**i generate
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                                                                                MUX_L1: a_temp_d(i)(j) <= a_temp_q(i)(j) when shft(i) = '0' else
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                                                                                                                                                arith;
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                                                                        end generate ZERO_INS_L;
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                                                                BIT_INS_L:
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                                                                        if j >= 2**i generate
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                                                                                MUX_L2: a_temp_d(i)(j) <= a_temp_q(i)(j) when shft(i) = '0' else
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                                                                                                                                                a_temp_q(i)(j-2**i);
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                                                                        end generate BIT_INS_L;
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                                                        end generate MUX_GEN_L;
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                        end generate LEFT;
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                        RIGHT : if DIRECTION = 0 generate
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                                MUX_GEN_R:
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                                                        for j in 0 to OUTPUT_SIZE - 1 generate
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                                                                ZERO_INS_R:
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                                                                        if OUTPUT_SIZE - 1 < 2**i + j generate
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                                                                                MUX_R1: a_temp_d(i)(j) <= a_temp_q(i)(j) when shft(i) = '0' else
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                                                                                                                                                arith;
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                                                                        end generate ZERO_INS_R;
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                                                                BIT_INS_R:
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                                                                        if  OUTPUT_SIZE - 1 >= 2**i + j generate
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                                                                                MUX_R2: a_temp_d(i)(j) <= a_temp_q(i)(j) when shft(i) = '0' else
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                                                                                                                                                a_temp_q(i)(j+2**i);
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                                                                        end generate BIT_INS_R;
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                                        end generate MUX_GEN_R;
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                        end generate RIGHT;
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                        PIPELINE_INSERTION:
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                                if PIPELINE /= 0 generate
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                                                        LATCH :
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                                                                        if (POSITION (i) = '1') generate
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                                                                                D_INS: d_ff     generic map (N => OUTPUT_SIZE)
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                                                                                                                        port map ( clk => clk, rst => rst,
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                                                                                                                                d => a_temp_d(i), q => a_temp_q(i+1));
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                                                                        end generate LATCH;
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                                                        NO_LATCH:
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                                                                        if (POSITION (i) = '0' ) generate
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                                                                                ASSIGN : a_temp_q(i+1) <= a_temp_d(i);
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                                                                        end generate NO_LATCH;
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                                end generate PIPELINE_INSERTION;
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                        NO_PIPELINE:
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                                if PIPELINE = 0 generate
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                                        NO_INS: a_temp_q(i+1) <= a_temp_d(i);
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                                end generate NO_PIPELINE;
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                end generate BARREL_SHIFTER_GENERATION;
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        shifted_a <= a_temp_q(SHIFT_SIZE);
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end Behavioral;
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