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[/] [xilinx_virtex_fp_library/] [trunk/] [HalfPrecision/] [sign_comp.vhd] - Blame information for rev 2

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1 2 bigsascha3
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    09:28:06 02/07/2013 
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-- Design Name: 
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-- Module Name:    sign_comp - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity sign_comp is
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        port (sign_a, sign_b : in std_logic;
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                        sign_c : in std_logic;
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                        comp_exp : in std_logic;
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                        eff_sub : in std_logic;
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                        sign_add : in std_logic;
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                        sign_res : out std_logic);
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end sign_comp;
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architecture Behavioral of sign_comp is
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        signal sign_int : std_logic;
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begin
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        process (sign_a, sign_b, sign_c, comp_exp,
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                eff_sub, sign_add)
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        begin
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                sign_int <= sign_c;
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                if(eff_sub = '1') then
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                        if(comp_exp = '1') then
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                                sign_int <= sign_a xor sign_b;
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                        elsif (comp_exp = '0' and sign_add = '0') then
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                                sign_int <= sign_c;
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                        else
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                                sign_int <= sign_a xor sign_b;
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                        end if;
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                end if;
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        end process;
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        sign_res <= sign_int;
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end Behavioral;
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