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[/] [xilinx_virtex_fp_library/] [trunk/] [SinglePathFPAdderMappedConversions/] [d_ff.v] - Blame information for rev 15

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Line No. Rev Author Line
1 15 constantin
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: 
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// 
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// Create Date:    09:39:58 02/04/2013 
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// Design Name: 
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// Module Name:    d_ff
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 / File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module d_ff (clk, rst, d, q);
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        parameter SIZE = 24;
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        input clk;
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        input rst;
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        input [SIZE-1 : 0] d;
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        output reg [SIZE-1 : 0] q;
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        always
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                @(posedge clk, posedge rst)
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        begin
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                if (rst)
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                        q <= {SIZE{1'b0}};
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                else
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                        q <= d;
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        end
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endmodule

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