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[/] [xilinx_virtex_fp_library/] [trunk/] [SinglePrecision/] [effective_op.vhd] - Blame information for rev 2

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1 2 bigsascha3
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    10:30:56 02/06/2013 
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-- Design Name: 
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-- Module Name:    effective_op - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity effective_op is
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        port (sign_a, sign_b, sign_c : in std_logic;
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                        sub: in std_logic;
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                        eff_sub : out std_logic);
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end effective_op;
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architecture Behavioral of effective_op is
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        signal sign_a_x_b : std_logic;
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        signal sub_string : std_logic_vector (2 downto 0);
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begin
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        sign_a_x_b <= sign_a xor sign_b;
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        sub_string (0) <= sign_c;
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        sub_string (1) <= sign_a_x_b;
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        sub_string (2) <= sub;
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        with (sub_string) select eff_sub <=
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                '0' when "000",
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                '1' when "001",
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                '1' when "010",
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                '0' when "011",
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                '1' when "100",
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                '0' when "101",
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                '0' when "110",
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                '1' when "111",
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                '0' when others;
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end Behavioral;
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