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[/] [xilinx_virtex_fp_library/] [trunk/] [SinglePrecision/] [exp_add_lzc.vhd] - Blame information for rev 2

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1 2 bigsascha3
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    08:35:50 02/07/2013 
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-- Design Name: 
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-- Module Name:    exp_add_lzc - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity exp_add_lzc is
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        generic( SIZE_EXP : natural := 5;
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                                SIZE_LZC : natural := 4);
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        port (exp_in : in std_logic_vector(SIZE_EXP - 1 downto 0);
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                                lzc : in std_logic_vector(SIZE_LZC - 1 downto 0);
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                                exp_out : out std_logic_vector (SIZE_EXP - 1 downto 0));
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end exp_add_lzc;
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architecture Behavioral of exp_add_lzc is
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        signal bias : std_logic_vector(SIZE_EXP - 1 downto 0);
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        --signal lzc_fp: std_logic_vector(SIZE_LZC - 1 downto 0);
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begin
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        bias_gen:
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                for i in 0 to SIZE_EXP - 3 generate
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                        one_bit : bias (i) <= '1';
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                end generate;
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        bias (SIZE_EXP-1 downto SIZE_EXP - 2) <= "00";
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        --lzc_fp <=     "000000" when (lzc < "010001") else
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        --                      "010001";
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        --exp_out <= exp_in - lzc - bias;
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        exp_out <= exp_in - lzc - bias + 1;
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end Behavioral;
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