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[/] [xilinx_virtex_fp_library/] [trunk/] [SinglePrecision/] [exponent_align.vhd] - Blame information for rev 2

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1 2 bigsascha3
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    09:32:21 02/06/2013 
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-- Design Name: 
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-- Module Name:    exponent_align - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_SIGNED.all;
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use ieee.std_logic_arith.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity exponent_align is
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        generic (SIZE_EXP : natural := 5;
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                                PIPELINE : natural := 2); -- nr of pipeline registers -- max 2
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        port (clk, rst : in std_logic;
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                        exp_a, exp_b : in std_logic_vector (SIZE_EXP - 1 downto 0);
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                        exp_c : in std_logic_vector (SIZE_EXP - 1 downto 0);
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                        align : out std_logic_vector (SIZE_EXP - 1 downto 0);
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                        exp_int : out std_logic_vector (SIZE_EXP downto 0);
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                        comp : out std_logic);
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end exponent_align;
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architecture Behavioral of exponent_align is
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        component d_ff
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                generic (N: natural := 8);
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                port (clk, rst : in std_logic;
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                                d : in std_logic_vector (N-1 downto 0);
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                                q : out std_logic_vector (N-1 downto 0));
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        end component;
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        signal exp_a_x_b_bias : std_logic_vector(SIZE_EXP downto 0);
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        signal exp_a_x_b_d1, exp_a_x_b_q1 : std_logic_vector (SIZE_EXP downto 0);
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        signal exp_a_x_b_q2 : std_logic_vector (SIZE_EXP downto 0);
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        signal exp_c_d1 : std_logic_vector (SIZE_EXP downto 0);
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        signal exp_c_q1, exp_c_q2 : std_logic_vector (SIZE_EXP downto 0);
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        signal exp_dif_d, exp_dif_q : std_logic_vector(SIZE_EXP downto 0);
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        signal bias : std_logic_vector(SIZE_EXP downto 0);
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begin
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        bias_gen:
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                for i in 0 to SIZE_EXP - 2 generate
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                        one_bit : bias (i) <= '1';
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                end generate;
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        bias (SIZE_EXP downto SIZE_EXP - 1) <= "00";
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        exp_a_x_b_bias <= ("0" & exp_a) + ("0" & exp_b);
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        exp_a_x_b_d1 <= exp_a_x_b_bias;
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        exp_c_d1 <= ("0" & exp_c) + bias;
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        exp_dif_d <= exp_c_q1 - exp_a_x_b_q1;
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        exp_int <= exp_c_q2 when exp_dif_q(SIZE_EXP) = '0' else
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                                exp_a_x_b_q2;
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        comp <= exp_dif_q(SIZE_EXP);
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        align <= exp_dif_q (SIZE_EXP - 1 downto 0) when exp_dif_q(SIZE_EXP) = '0' else
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                         -(exp_dif_q (SIZE_EXP - 1 downto 0));
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        --PIPELINING
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        ONE_STAGE:
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                if (PIPELINE = 1) generate
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                        A_X_B_1S : D_FF generic map (N => SIZE_EXP+1)
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                                                                port map (clk => clk, rst => rst,
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                                                                                d => exp_a_x_b_d1, q => exp_a_x_b_q1);
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                        C_1S: D_FF generic map (N => SIZE_EXP + 1)
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                                                                port map (clk => clk, rst => rst,
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                                                                                d => exp_c_d1, q => exp_c_q1);
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                        ASSIGN_A_X_B_1S : exp_a_x_b_q2 <= exp_a_x_b_q1;
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                        ASSIGN_C_1S :   exp_c_q2 <= exp_c_q1;
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                        ASSIGN_dif_1S : exp_dif_q <= exp_dif_d;
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                end generate;
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        TWO_STAGE:
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                if (PIPELINE = 2) generate
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                        A_X_B_2S_1 : D_FF generic map (N => SIZE_EXP+1)
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                                                                port map (clk => clk, rst => rst,
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                                                                                d => exp_a_x_b_d1, q => exp_a_x_b_q1);
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                        C_2S_1: D_FF generic map (N => SIZE_EXP+1)
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                                                                port map (clk => clk, rst => rst,
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                                                                                d => exp_c_d1, q => exp_c_q1);
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                        A_X_B_2S_2 : D_FF generic map (N => SIZE_EXP+1)
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                                                                port map (clk => clk, rst => rst,
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                                                                                d => exp_a_x_b_q1, q => exp_a_x_b_q2);
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                        C_2S_2: D_FF generic map (N => SIZE_EXP+1)
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                                                                port map (clk => clk, rst => rst,
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                                                                                d => exp_c_q1, q => exp_c_q2);
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                        DIF_2S : D_FF generic map (N => SIZE_EXP+1)
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                                                                port map (clk => clk, rst => rst,
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                                                                                d => exp_dif_d, q => exp_dif_q);
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                end generate;
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        NO_STAGE:
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                if (PIPELINE = 0) generate
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                        ASSIGN_A_X_B_NOS_1 : exp_a_x_b_q1 <= exp_a_x_b_d1;
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                        ASSIGN_C_NOS_1 :        exp_c_q1 <= exp_c_d1;
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                        ASSIGN_A_X_B_NOS_2 : exp_a_x_b_q2 <= exp_a_x_b_q1;
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                        ASSIGN_C_NOS_2 :        exp_c_q2 <= exp_c_q1;
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                        ASSIGN_dif_NOS : exp_dif_q <= exp_dif_d;
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                end generate;
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end Behavioral;
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