OpenCores
URL https://opencores.org/ocsvn/xilinx_virtex_fp_library/xilinx_virtex_fp_library/trunk

Subversion Repositories xilinx_virtex_fp_library

[/] [xilinx_virtex_fp_library/] [trunk/] [SinglePrecision/] [lzc_tree.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 bigsascha3
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Create Date:    10:56:33 02/06/2013 
6
-- Design Name: 
7
-- Module Name:    lzc_tree - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
13
-- Dependencies: 
14
--
15
-- Revision: 
16
-- Revision 0.01 - File Created
17
-- Additional Comments: 
18
--
19
----------------------------------------------------------------------------------
20
library IEEE;
21
use IEEE.STD_LOGIC_1164.all;
22
use IEEE.math_real.all;
23
use IEEE.std_logic_unsigned.all;
24
use IEEE.std_logic_arith.all;
25
 
26
-- Uncomment the following library declaration if using
27
-- arithmetic functions with Signed or Unsigned values
28
--use IEEE.NUMERIC_STD.ALL;
29
 
30
-- Uncomment the following library declaration if instantiating
31
-- any Xilinx primitives in this code.
32
--library UNISIM;
33
--use UNISIM.VComponents.all;
34
 
35
entity lzc_tree is
36
        generic (SIZE_INT : natural := 42;
37
                                PIPELINE : natural := 2);
38
        port (clk, rst : in std_logic;
39
                        a  : in std_logic_vector(SIZE_INT - 1 downto 0);
40
                        ovf : in std_logic;
41
                        lz : out std_logic_vector(integer(CEIL(LOG2(real(SIZE_INT)))) - 1 downto 0));
42
end lzc_tree;
43
 
44
architecture Behavioral of lzc_tree is
45
 
46
        component d_ff
47
                generic (N: natural := 8);
48
                port (clk, rst : in std_logic;
49
                                d : in std_logic_vector (N-1 downto 0);
50
                                q : out std_logic_vector (N-1 downto 0));
51
        end component;
52
 
53
        constant nr_levels : integer := integer (CEIL(LOG2(real (SIZE_INT)))) - 1       ;
54
        constant max_pow_2 : integer := integer (2.0 ** (CEIL (LOG2 (real (SIZE_INT)))));
55
        constant size_lz : integer := integer(CEIL(LOG2(real(SIZE_INT))));
56
 
57
        type v_type is array (nr_levels - 1 downto 0) of std_logic_vector(max_pow_2 - 1 downto 0);
58
        type p_type is array(nr_levels - 1 downto 0) of std_logic_vector (max_pow_2 - 1 downto 0);
59
 
60
        signal a_complete : std_logic_vector(max_pow_2 - 1 downto 0);
61
        signal v_d, v_q : v_type;
62
        signal p_d, p_q : p_type;
63
        signal lzc : std_logic_vector(size_lz - 1 downto 0);
64
 
65
begin
66
 
67
        a_complete (max_pow_2 - 1 downto max_pow_2 - 1 - SIZE_INT + 1) <= a;
68
        gen_if:
69
                if(max_pow_2 /= SIZE_INT) generate
70
                        a_complete (max_pow_2 - 1 - SIZE_INT  downto 0) <= (others => '0');
71
                end generate;
72
 
73
 
74
        level_0:
75
                for i in max_pow_2/4 - 1 downto 0 generate
76
                        v_d(0)(i) <= '0' when a_complete(4*i + 3 downto 4*i) = "0000" else
77
                                                '1';
78
                        p_d(0)(2*i+1 downto 2*i) <= "00" when a_complete(4*i+3) = '1' else
79
                                                                                        "01" when a_complete(4*i+2) = '1' else
80
                                                                                        "10" when a_complete(4*i+1) = '1' else
81
                                                                                        "11";
82
                end generate;
83
 
84
 
85
        level_generation:
86
                for i in 1 to nr_levels - 1 generate
87
                        v_levels:
88
                                for j in 0 to max_pow_2/(integer(2**(i+2))) - 1 generate
89
                                        v_d(i)(j) <= v_q(i-1)(2*j+1) or v_q(i-1)(2*j);
90
                                end generate;
91
                        p_levels:
92
                                for j in 0 to max_pow_2/(integer(2**(i+2))) - 1 generate
93
                                        p_d(i)((i+2)*j+i+1) <= not(v_q(i-1)(2*j+1));
94
                                        p_d(i)((i+2)*j+i downto (i+2)*j) <= p_q(i-1)(j*(2*i+2) + 2*i + 1 downto j*(2*i+2) + i+1) when v_q(i-1)(2*j+1) = '1'
95
                                                                                                                        else p_q(i-1)(j*(2*i+2) + i downto j*(2*i+2));
96
                                end generate;
97
        end generate;
98
 
99
        pipeline_stages:
100
                if(PIPELINE /= 0) generate
101
                        INSERTION:
102
                                for i in 0 to nr_levels - 2 generate
103
                                        INS: if ((i+1) mod nr_levels/(PIPELINE+1) = 0) generate
104
                                                                P_Di : D_FF generic map (N => max_pow_2)
105
                                                                                                port map( clk => clk, rst => rst,
106
                                                                                                                        d => p_d(i), q =>p_q(i));
107
                                                                V_Di : D_FF generic map (N => max_pow_2)
108
                                                                                                port map( clk => clk, rst => rst,
109
                                                                                                                        d => v_d(i), q =>v_q(i));
110
                                                        end generate INS;
111
                                        NO_INS: if ((i+1) mod nr_levels/(PIPELINE+1) /= 0) generate
112
                                                                        P_ASSIGN: p_q(i) <= p_d(i);
113
                                                                        V_ASSIGN: v_q(i) <= v_d(i);
114
                                                        end generate NO_INS;
115
                        end generate;
116
                        p_q(nr_levels - 1) <= p_d(nr_levels - 1);
117
                        v_q(nr_levels - 1) <= v_d(nr_levels - 1);
118
                end generate;
119
 
120
 
121
 
122
        no_pipeline:
123
                if(PIPELINE = 0) generate
124
                        NO_INSERTION:
125
                                for i in 0 to nr_levels - 1 generate
126
                                                P_ASSIGN_0: p_q(i) <= p_d(i);
127
                                                V_ASSIGN_0: v_q(i) <= v_d(i);
128
                                end generate;
129
                end generate;
130
 
131
        lzc (size_lz - 1 downto 0) <= p_q(nr_levels - 1)(size_lz - 1 downto 0);
132
 
133
        lz_ovf:
134
                for i in 0 to size_lz - 1  generate
135
                                lz(i) <= lzc (i) and (not ovf);
136
                end generate;
137
 
138
end Behavioral;
139
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.