OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/a-z80/trunk/cpu/control/exec_zero.i File deleted
/a-z80/trunk/cpu/control/exec_matrix.i File deleted
/a-z80/trunk/cpu/control/exec_module.i File deleted
/a-z80/trunk/cpu/control/timing_macros.i
1,6 → 1,6
//=========================================================================================
// This file contains substitute strings for macros used in the Excel timing table and
// is read and processed by genmatrix.py script to generate exec_matrix.i include file.
// is read and processed by genmatrix.py script to generate exec_matrix.vh include file.
//
// Format of the file:
//
/a-z80/trunk/cpu/control/exec_module.vh
0,0 → 1,127
// Automatically generated by genref.py
 
// Module: control/decode_state.v
output logic ctl_state_iy_set,
output logic ctl_state_ixiy_clr,
output logic ctl_state_ixiy_we,
output logic ctl_state_halt_set,
output logic ctl_state_tbl_clr,
output logic ctl_state_tbl_ed_set,
output logic ctl_state_tbl_cb_set,
output logic ctl_state_alu,
output logic ctl_repeat_we,
 
// Module: control/interrupts.v
output logic ctl_iff1_iff2,
output logic ctl_iffx_we,
output logic ctl_iffx_bit,
output logic ctl_im_we,
output logic ctl_no_ints,
 
// Module: control/ir.v
output logic ctl_ir_we,
 
// Module: control/memory_ifc.v
output logic ctl_mRead,
output logic ctl_mWrite,
output logic ctl_iorw,
 
// Module: alu/alu_control.v
output logic ctl_shift_en,
output logic ctl_daa_oe,
output logic ctl_alu_op_low,
output logic ctl_cond_short,
output logic ctl_alu_core_hf,
output logic ctl_eval_cond,
output logic ctl_66_oe,
output logic [1:0] ctl_pf_sel,
 
// Module: alu/alu_select.v
output logic ctl_alu_oe,
output logic ctl_alu_shift_oe,
output logic ctl_alu_op2_oe,
output logic ctl_alu_res_oe,
output logic ctl_alu_op1_oe,
output logic ctl_alu_bs_oe,
output logic ctl_alu_op1_sel_bus,
output logic ctl_alu_op1_sel_low,
output logic ctl_alu_op1_sel_zero,
output logic ctl_alu_op2_sel_zero,
output logic ctl_alu_op2_sel_bus,
output logic ctl_alu_op2_sel_lq,
output logic ctl_alu_sel_op2_neg,
output logic ctl_alu_sel_op2_high,
output logic ctl_alu_core_R,
output logic ctl_alu_core_V,
output logic ctl_alu_core_S,
 
// Module: alu/alu_flags.v
output logic ctl_flags_oe,
output logic ctl_flags_bus,
output logic ctl_flags_alu,
output logic ctl_flags_nf_set,
output logic ctl_flags_cf_set,
output logic ctl_flags_cf_cpl,
output logic ctl_flags_cf_we,
output logic ctl_flags_sz_we,
output logic ctl_flags_xy_we,
output logic ctl_flags_hf_we,
output logic ctl_flags_pf_we,
output logic ctl_flags_nf_we,
output logic ctl_flags_cf2_we,
output logic ctl_flags_hf_cpl,
output logic ctl_flags_use_cf2,
output logic ctl_flags_hf2_we,
output logic ctl_flags_nf_clr,
output logic ctl_alu_zero_16bit,
output logic [1:0] ctl_flags_cf2_sel,
 
// Module: registers/reg_file.v
output logic ctl_sw_4d,
output logic ctl_sw_4u,
output logic ctl_reg_in_hi,
output logic ctl_reg_in_lo,
output logic ctl_reg_out_lo,
output logic ctl_reg_out_hi,
 
// Module: registers/reg_control.v
output logic ctl_reg_exx,
output logic ctl_reg_ex_af,
output logic ctl_reg_ex_de_hl,
output logic ctl_reg_use_sp,
output logic ctl_reg_sel_pc,
output logic ctl_reg_sel_ir,
output logic ctl_reg_sel_wz,
output logic ctl_reg_gp_we,
output logic ctl_reg_not_pc,
output logic ctl_reg_sys_we_lo,
output logic ctl_reg_sys_we_hi,
output logic ctl_reg_sys_we,
output logic [1:0] ctl_reg_gp_hilo,
output logic [1:0] ctl_reg_gp_sel,
output logic [1:0] ctl_reg_sys_hilo,
 
// Module: bus/address_latch.v
output logic ctl_inc_cy,
output logic ctl_inc_dec,
output logic ctl_inc_zero,
output logic ctl_al_we,
output logic ctl_inc_limit6,
output logic ctl_bus_inc_oe,
output logic ctl_apin_mux,
output logic ctl_apin_mux2,
 
// Module: bus/bus_control.v
output logic ctl_bus_ff_oe,
output logic ctl_bus_zero_oe,
output logic ctl_bus_db_oe,
 
// Module: bus/bus_switch.sv
output logic ctl_sw_1u,
output logic ctl_sw_1d,
output logic ctl_sw_2u,
output logic ctl_sw_2d,
output logic ctl_sw_mask543_en,
 
// Module: bus/data_pins.v
output logic ctl_bus_db_we,
/a-z80/trunk/cpu/control/exec_matrix.vh
0,0 → 1,4194
// Automatically generated by genmatrix.py
// 8-bit Load Group
if (pla[17] && !pla[50]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end
end
 
if (pla[61] && !pla[58] && !pla[59]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
end
 
if (use_ixiy && pla[58]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (~use_ixiy && pla[58]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; end
end
 
if (use_ixiy && pla[59]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (~use_ixiy && pla[59]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T1) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMWrite=1; end
if (M2 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1; end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (pla[40]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mWrite=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (pla[50] && !pla[40]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1; end
if (M3 && T1) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T2) begin fMWrite=1; end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (pla[8] && pla[13]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mWrite=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T1) begin fMWrite=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (pla[8] && !pla[13]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1; end
end
 
if (pla[38] && pla[13]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (pla[38] && !pla[13]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1; end
end
 
if (pla[83]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_IFF2;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1;
ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4u=1; /* Read either I or R based on op3 (0 or 1) */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T5) begin nextM=1; setM1=1; end
end
 
if (pla[57]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1;
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo={!op3,op3}; ctl_sw_4d=1; /* Write either I or R based on op3 (0 or 1) */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */ end
if (M1 && T5) begin nextM=1; setM1=1; end
end
 
// 16-bit Load Group
if (pla[7]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1; end
end
 
if (pla[30] && pla[13]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M5 && T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (pla[30] && !pla[13]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M5 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
end
 
if (pla[31] && pla[33]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M4 && T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M5 && T2) begin fMWrite=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (pla[31] && !pla[33]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M5 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
end
 
if (pla[5]) begin
if (M1 && T4) begin validPLA=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M1 && T5) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M1 && T6) begin nextM=1; setM1=1; end
end
 
if (pla[23] && pla[16]) begin
if (M1 && T4) begin validPLA=1; end
if (M1 && T5) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M3 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (pla[23] && !pla[16]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Write 8-bit GP register low byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Write 8-bit GP register high byte */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
end
 
// Exchange, Block Transfer and Search Groups
if (pla[2]) begin
if (M1 && T2) begin
ctl_reg_ex_de_hl=1; /* EX DE,HL */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
end
 
if (pla[39]) begin
if (M1 && T2) begin
ctl_reg_ex_af=1; /* EX AF,AF' */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
end
 
if (pla[1]) begin
if (M1 && T2) begin
ctl_reg_exx=1; /* EXX */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
end
 
if (pla[10]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M5 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T4) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T5) begin nextM=1; setM1=1; end
end
 
if (pla[0]) begin
begin nonRep=1; /* Non-repeating block instruction */ end
end
 
if (pla[12]) begin
if (M1 && T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_use_cf2=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (M3 && T1) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit DE, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_use_cf2=1; end
if (M3 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_DE; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T4) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
if (M3 && T5) begin nextM=1; setM1=nonRep | !repeat_en; end
if (M4 && T1) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T5) begin nextM=1; setM1=1; end
end
 
if (pla[11]) begin
if (M1 && T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_op1_sel_zero=1; /* Zero */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_REP;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_use_cf2=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (M3 && T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_use_cf2=1; end
if (M3 && T3) begin
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T4) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit BC, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_repeat_we=1; /* Update repeating flag latch with BC=1 status */ end
if (M3 && T5) begin nextM=1; setM1=nonRep | !repeat_en | flags_zf; end
if (M4 && T1) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T5) begin nextM=1; setM1=1; end
end
 
// 8-bit Arithmetic and Logic Group
if (pla[65] && !pla[52]) begin
if (M1 && T1) begin /* Which register to be written is decided elsewhere */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1; end
end
 
if (pla[64]) begin
if (M1 && T1) begin /* Which register to be written is decided elsewhere */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1; end
end
 
if (use_ixiy && pla[52]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (!use_ixiy && pla[52]) begin
if (M1 && T1) begin /* Which register to be written is decided elsewhere */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1; end
if (M4 && T1) begin fMRead=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T2) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M4 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_state_alu=1; /* Assert the ALU PLA modifier to determine operation */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1; end
end
 
if (pla[66] && !pla[53]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_use_cf2=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; /* Trying to read flags? Put 0 on the bus instead. */
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_set=1; /* Set CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
end
 
if (pla[75]) begin
if (M1 && T1) begin
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
ctl_alu_sel_op2_neg=1; end
if (M1 && T4) begin
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
ctl_alu_sel_op2_neg=1; end
end
 
if ((M2 || M4) && pla[75]) begin
begin
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
ctl_alu_sel_op2_neg=1; end
end
 
if (use_ixiy && pla[53]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
end
 
if (!use_ixiy && pla[53]) begin
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_set=1; /* Set CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (M2 && T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_use_cf2=1; end
if (M3 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_set=1; /* Set CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (M4 && T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_use_cf2=1; end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
// 16-bit Arithmetic Group
if (pla[69]) begin
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T1) begin
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M2 && T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_xy_we=1;
ctl_flags_cf_we=1; end
if (M2 && T3) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T4) begin nextM=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M3 && T1) begin
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_xy_we=1;
ctl_flags_cf_we=1; end
if (M3 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin nextM=1; setM1=1; end
end
 
if (op3 && pla[68]) begin
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T1) begin
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M2 && T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_cf_we=1; end
if (M2 && T3) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T4) begin nextM=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M3 && T1) begin
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_cf_we=1;
ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
if (M3 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin nextM=1; setM1=1; end
end
 
if (!op3 && pla[68]) begin
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T1) begin
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b01; /* Read 8-bit GP register low byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M2 && T2) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_cf_we=1; end
if (M2 && T3) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T4) begin nextM=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b10; /* Read 8-bit GP register high byte */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M3 && T1) begin
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_cf_we=1;
ctl_alu_zero_16bit=1; /* 16-bit arithmetic operation uses ZF calculated over 2 bytes */ end
if (M3 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin nextM=1; setM1=1; end
end
 
if (pla[9]) begin
if (M1 && T4) begin validPLA=1;
ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit general purpose register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M1 && T5) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit general purpose register, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_use_sp=1; /* For 16-bit loads: use SP instead of AF */ end
if (M1 && T6) begin nextM=1; setM1=1; end
end
 
// General Purpose Arithmetic and CPU Control Groups
if (pla[77]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_cf_we=1;
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_use_cf2=1;
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf2_we=1; /* Write HF2 flag (DAA only) */
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=2;
ctl_daa_oe=1; /* Write DAA correction factor to the bus */
ctl_alu_sel_op2_neg=flags_nf; ctl_flags_cf_cpl=!flags_nf; end
end
 
if (pla[81]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_alu_sel_op2_neg=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op1_sel_zero=1; /* Zero */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_alu_sel_op2_neg=1; end
end
 
if (pla[82]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_hf_cpl=flags_nf; ctl_flags_cf_cpl=flags_nf; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op1_sel_zero=1; /* Zero */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_set=1;
ctl_flags_cf_we=1; end
end
 
if (pla[89]) begin
if (M1 && T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_cf_we=1; ctl_flags_cf_cpl=1; /* CCF */
ctl_flags_hf_cpl=!flags_cf; /* Used for CCF */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (pla[92]) begin
if (M1 && T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_cf_set=1; /* Set CF going into the ALU core */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (pla[95]) begin
if (M1 && T3) begin
ctl_state_halt_set=1; /* Enter HALT state */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
end
 
if (pla[97]) begin
if (M1 && T3) begin
ctl_iffx_bit=op3; ctl_iffx_we=1; /* DI/EI */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
 
if (pla[96]) begin
if (M1 && T3) begin
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_im_we=1; /* IM n ('n' is read by opcode[4:3]) */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1; end
end
 
// Rotate and Shift Group
if (pla[25]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_use_cf2=1; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
end
 
if (~use_ixiy && pla[70] && !pla[55]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_use_cf2=1; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (~use_ixiy && pla[70] && pla[55]) begin
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */
ctl_flags_use_cf2=1; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1; end
if (M2 && T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
if (M3 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=1; ctl_shift_en=1; /* Shifter unit AND shift enable! */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=1; end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1;
ctl_flags_cf_we=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (pla[15] && op3) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end
if (M4 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op2_oe=1; /* OP2 latch */ end
if (M4 && T2) begin fMWrite=1;
ctl_alu_op1_oe=1; /* OP1 latch */
ctl_alu_op2_sel_bus=1; /* Internal bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (pla[15] && !op3) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit WZ, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
if (M3 && T2) begin
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op2_oe=1; /* OP2 latch */ end
if (M3 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_lq=1; /* Cross-bus wire (see schematic) */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_low=1; /* Write low nibble with a high nibble */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */ end
if (M4 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op2_oe=1; /* OP2 latch */ end
if (M4 && T2) begin fMWrite=1;
ctl_alu_op1_oe=1; /* OP1 latch */
ctl_alu_op2_sel_bus=1; /* Internal bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; setM1=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
// Bit Manipulation Group
if (~use_ixiy && pla[72] && !pla[55]) begin
if (M1 && T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M4 && T1) begin fMRead=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; end
if (M4 && T4) begin nextM=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (~use_ixiy && pla[72] && pla[55]) begin
if (M1 && T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_flags_xy_we=1; end
if (M2 && T4) begin nextM=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; end
if (M4 && T4) begin nextM=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_sz_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (~use_ixiy && pla[74] && !pla[55]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (~use_ixiy && pla[74] && pla[55]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M2 && T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M3 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (~use_ixiy && pla[73] && !pla[55]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0}; /* Write 8-bit GP register selected by op[2:0] */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=op21; ctl_reg_gp_hilo={!rsel0,rsel0};/* Read 8-bit GP register selected by op[2:0] */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
if (~use_ixiy && pla[73] && pla[55]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1; end
if (M2 && T3) begin fMRead=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M2 && T4) begin nextM=1; ctl_mWrite=1;
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M3 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T2) begin fMWrite=1; end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=1; end
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
if (M4 && T2) begin fMRead=1; end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 && T1) begin fMWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_alu_sel_op2_neg=1; end
if (M5 && T2) begin fMWrite=1; end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1; end
end
 
// Input and Output Groups
if (pla[37] && !pla[28]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1; end
if (M3 && T1) begin fIORead=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ /* Which register to be written is decided elsewhere */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T2) begin fIORead=1; end
if (M3 && T3) begin fIORead=1; end
if (M3 && T4) begin fIORead=1; nextM=1; setM1=1; end
end
 
if (pla[27] && !pla[34]) begin
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; /* Write 8-bit GP register */
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_iorw=1; end
if (M2 && T1) begin fIORead=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fIORead=1; end
if (M2 && T3) begin fIORead=1; end
if (M2 && T4) begin fIORead=1; nextM=1; setM1=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
end
 
if (pla[37] && pla[28]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1;
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10; ctl_sw_4d=1; /* Read 8-bit general purpose A register, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fIOWrite=1;
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M3 && T2) begin fIOWrite=1; end
if (M3 && T3) begin fIOWrite=1; end
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=1; end
end
 
if (pla[27] && pla[34]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_iorw=1;
if (op4 & op5 & !op3) ctl_bus_zero_oe=1; /* Trying to read flags? Put 0 on the bus instead. */
else begin ctl_reg_gp_sel=op54; ctl_reg_gp_hilo={!rsel3,rsel3}; end /* Read 8-bit GP register */
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T1) begin fIOWrite=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fIOWrite=1; end
if (M2 && T3) begin fIOWrite=1; end
if (M2 && T4) begin fIOWrite=1; nextM=1; setM1=1; end
end
 
if (pla[91] && pla[21]) begin
if (M1 && T1) begin
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; end
if (M1 && T5) begin nextM=1; ctl_iorw=1; end
if (M2 && T1) begin fIORead=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fIORead=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=1; end
if (M2 && T3) begin fIORead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_cf_we=1;
ctl_alu_sel_op2_neg=1; end
if (M2 && T4) begin fIORead=1; nextM=1; ctl_mWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */
ctl_alu_sel_op2_neg=1; end
if (M3 && T1) begin fMWrite=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M4 && T1) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T5) begin nextM=1; setM1=1; end
end
 
if (pla[91] && pla[20]) begin
if (M1 && T1) begin
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b01;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_oe=1; /* Enable FLAGT onto the data bus */ end
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=1; end
if (M1 && T5) begin nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_alu_sel_op2_neg=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4u=1; /* Write 16-bit HL, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=op3; /* Decrement if op3 is set; increment otherwise */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_iorw=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M3 && T1) begin fIOWrite=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit BC, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fIOWrite=1;
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_flags_nf_we=1; /* Sign bit, to be used with FLAGT source set to "alu" */ end
if (M3 && T3) begin fIOWrite=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_we=1; end
if (M3 && T4) begin fIOWrite=1; nextM=1; setM1=nonRep | !repeat_en | flags_zf;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; end
if (M4 && T1) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T2) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T4) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T5) begin nextM=1; setM1=1; end
end
 
// Jump Group
if (pla[29]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[43]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
if (flags_cond_true) begin /* If cc is true, use WZ instead of PC (for jumps) */
ctl_reg_not_pc=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1;
end
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; /* Conditionally selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
end
 
if (pla[47]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; end
if (M3 && T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1; end
if (M3 && T2) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1; end
if (M3 && T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_we=1; end
if (M3 && T4) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=flags_sf; end
if (M3 && T5) begin nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=flags_sf;
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[48]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1;
ctl_cond_short=1; /* M1/T3 only: force a short flags condition (SS) */ end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=!flags_cond_true; end
if (M3 && T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1; end
if (M3 && T2) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1; end
if (M3 && T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_we=1; end
if (M3 && T4) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=flags_sf; end
if (M3 && T5) begin nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=flags_sf;
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[6]) begin
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1; /* Read 16-bit HL, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[26]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1;
ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=1; end
if (M1 && T5) begin nextM=1; ctl_mRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_BC; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_sz_we=1;
ctl_alu_sel_op2_neg=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; setM1=flags_zf; /* Used in DJNZ */ end
if (M3 && T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1; end
if (M3 && T2) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1; end
if (M3 && T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_cf_we=1; end
if (M3 && T4) begin
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_alu_sel_op2_neg=flags_sf; end
if (M3 && T5) begin nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_alu_sel_op2_neg=flags_sf;
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
// Call and Return Group
if (pla[24]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1;
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M5 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[42]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=!flags_cond_true; setM1=!flags_cond_true;
ctl_reg_sys_we_hi=flags_cond_true; ctl_reg_sel_wz=flags_cond_true; ctl_reg_sys_hilo[1]=1; /* Conditionally selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T4) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M4 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M4 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M4 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M5 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M5 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMWrite=1; nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[35]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[45]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1; end
if (M1 && T4) begin validPLA=1; end
if (M1 && T5) begin nextM=1; ctl_mRead=1; setM1=!flags_cond_true; end
if (M2 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[46]) begin
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1;
ctl_iff1_iff2=1; /* RETN copies IFF2 into IFF1 */ end
if (M2 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M3 && T1) begin fMRead=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
if (pla[56]) begin
if (M1 && T3) begin
ctl_reg_sys_we=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */
ctl_alu_op1_sel_zero=1; /* Zero */
ctl_sw_mask543_en=!((in_intr & im2) | in_nmi);
ctl_sw_1d=!in_nmi; ctl_66_oe=in_nmi;
ctl_bus_ff_oe=in_intr & im1; end
if (M1 && T4) begin validPLA=1; end
if (M1 && T5) begin nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M2 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4u=1;
ctl_reg_out_hi=1; /* From the register file into the ALU high byte only */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M2 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMWrite=1; nextM=1; ctl_mWrite=1;
ctl_reg_use_sp=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_sw_4d=1;/* Read 16-bit SP, enable SW4 downstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M3 && T1) begin fMWrite=1;
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_apin_mux=1; /* Apin sourced from incrementer */
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b01; ctl_sw_4u=1;
ctl_reg_out_lo=1; /* From the register file into the ALU low byte only */
ctl_sw_2u=1;
ctl_sw_1u=1;
ctl_bus_db_we=1; /* Write DB pads with internal data bus value */ end
if (M3 && T2) begin fMWrite=1;
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11; ctl_reg_use_sp=1; ctl_sw_4u=1; /* Write 16-bit SP, enable SW4 upstream */
ctl_inc_cy=pc_inc; ctl_inc_dec=1; /* Decrement */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M3 && T3) begin fMWrite=1; nextM=1; ctl_mRead=in_intr & im2; /* RST38 interrupt extension */ setM1=!(in_intr & im2); /* RST38 interrupt extension */
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
// INTR IM2 continues here...
if (M4 && T1) begin fMRead=1;
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */ end
if (M4 && T2) begin fMRead=1;
ctl_sw_4u=1;
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */
ctl_reg_out_lo=1; /* From the register file into the ALU low byte only */
ctl_sw_2d=1;
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */ end
if (M4 && T3) begin fMRead=1; nextM=1; ctl_mRead=1;
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */ end
if (M5 && T1) begin fMRead=1;
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b10; ctl_sw_4d=1; /* Select 8-bit I register */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_op1_oe=1; /* OP1 latch */ end
if (M5 && T2) begin fMRead=1;
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M5 && T3) begin fMRead=1; nextM=1; setM1=1;
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_reg_not_pc=1; /* For M1/T1 load from a register other than PC */ end
end
 
// CB-Table opcodes
if (pla[49]) begin
if (M1 && T3) begin
ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b11;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_bus=1; /* Load FLAGT from the data bus */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1;
ctl_flags_xy_we=1;
ctl_flags_hf_we=1;
ctl_flags_pf_we=1;
ctl_flags_nf_we=1; /* Previous NF, to be used when loading FLAGT */
ctl_flags_cf_we=1;
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
if (M1 && T4) begin validPLA=1; nextM=1; ctl_mRead=1; end
if (M2 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ end
if (M2 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ end
if (M2 && T3) begin fMRead=1; nextM=1; ctl_mRead=1; end
if (M3 && T1) begin fMRead=1;
ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit PC */
ctl_al_we=1; /* Write a value from the register bus to the address latch */ ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T2) begin fMRead=1;
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; /* Output enable incrementer to the register bus */ ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T3) begin fMRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T4) begin ixy_d=1; /* Compute WZ=IX+d */ end
if (M3 && T5) begin nextM=1; ctl_mRead=1; ixy_d=1; /* Compute WZ=IX+d */ end
if (M4 && T1) begin
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_alu_bs_oe=1; /* Bit-selector unit */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_ir_we=1; end
// Loading a new instruction immediately changes PLA wires and continues into the new effective instructions' M4/T1 cycle
end
 
// Special Purposes PLA Entries
if (pla[3]) begin
if (M1 && T2) begin
ctl_state_ixiy_we=1; ctl_state_iy_set=op5; setIXIY=1; /* IX/IY prefix */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
 
if (pla[44]) begin
if (M1 && T2) begin
ctl_state_tbl_cb_set=1; setCBED=1; /* CB-table prefix */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
 
if (pla[51]) begin
if (M1 && T2) begin
ctl_state_tbl_ed_set=1; setCBED=1; /* ED-table prefix */ end
if (M1 && T4) begin validPLA=1; nextM=1; setM1=1;
ctl_no_ints=1; /* Disable interrupt generation for this opcode (DI/EI/CB/ED/DD/FD) */ end
end
 
if (pla[76]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
if (M1 && T1) begin
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
end
 
if (pla[78]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
end
 
if (pla[79]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_alu_sel_op2_neg=1;
if (ctl_alu_op_low) begin
ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_nf_we=1; ctl_flags_nf_set=1; end
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
end
 
if (pla[80]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
end
 
if (pla[84]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_V; end
end
 
if (pla[85]) begin
begin
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=1; ctl_flags_cf_set=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
end
 
if (pla[86]) begin
begin
ctl_alu_core_R=1; ctl_alu_core_V=1; ctl_alu_core_S=1; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
end
 
if (pla[88]) begin
begin
ctl_alu_core_R=1; ctl_alu_core_V=0; ctl_alu_core_S=0; ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
ctl_flags_nf_we=1; ctl_flags_nf_clr=1; end
if (M1 && T1) begin
ctl_reg_gp_we=1; ctl_reg_gp_sel=`GP_REG_AF; ctl_reg_gp_hilo=2'b10;
ctl_reg_in_hi=1; ctl_reg_in_lo=1; /* From the ALU side into the register file */
ctl_flags_xy_we=1;
ctl_flags_pf_we=1; ctl_pf_sel=`PFSEL_P; end
if (M1 && T2) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1; /* Clear CF going into the ALU core */ end
end
 
// State machine to compute (IX+d)
if (ixy_d) begin
if (T1) begin
ctl_sw_2d=1;
ctl_sw_1d=1;
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_bus=1; /* Internal bus */
ctl_flags_sz_we=1; end
if (T2) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b01;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_sw_2d=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (ctl_alu_op_low) begin
ctl_flags_cf_set=1; ctl_flags_cf_cpl=1;
end else begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1; end
if (T3) begin
ctl_reg_sys_we_lo=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[0]=1; /* Selecting only Z */
ctl_reg_in_lo=1; /* From the ALU side into the register file low byte only */
ctl_sw_2u=1;
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_cf2_we=1; ctl_flags_cf2_sel=0; end
if (T4) begin
ctl_reg_gp_sel=`GP_REG_HL; ctl_reg_gp_hilo=2'b10;
ctl_reg_out_hi=1; ctl_reg_out_lo=1; /* From the register file into the ALU */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_shift_oe=!ctl_alu_bs_oe; /* Shifter unit without shift-enable */
ctl_alu_op2_sel_zero=1; /* Zero */
ctl_alu_op1_sel_bus=1; /* Internal bus */
ctl_alu_op_low=1; /* Activate ALU operation on low nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_hf_we=1;
ctl_flags_use_cf2=1;
ctl_alu_sel_op2_neg=flags_sf; end
if (T5) begin
ctl_reg_sel_wz=1; ctl_reg_sys_hilo=2'b11; ctl_sw_4d=1; /* Select 16-bit WZ */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_reg_sys_we_hi=1; ctl_reg_sel_wz=1; ctl_reg_sys_hilo[1]=1; /* Selecting only W */
ctl_reg_in_hi=1; /* From the ALU side into the register file high byte only */
ctl_flags_alu=1; /* Load FLAGT from the ALU */
ctl_alu_oe=1; /* Enable ALU onto the data bus */
ctl_alu_res_oe=1; /* Result latch */
ctl_alu_sel_op2_high=1; /* Activate ALU operation on high nibble */
ctl_alu_core_R=0; ctl_alu_core_V=0; ctl_alu_core_S=0;
if (!ctl_alu_op_low) begin
ctl_alu_core_hf=1;
end
ctl_flags_xy_we=1;
ctl_alu_sel_op2_neg=flags_sf;
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; /* Clear IX/IY flag */ end
end
 
// Default instruction fetch (M1) state machine
if (M1) begin
if (M1 && T1) begin
ctl_reg_sys_we=1; ctl_reg_sel_pc=1; ctl_reg_sys_hilo=2'b11; pc_inc=!(in_halt | in_intr | in_nmi); /* Write 16-bit PC and control incrementer */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */ end
if (M1 && T2) begin
ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Select 16-bit IR */
ctl_al_we=1; /* Write a value from the register bus to the address latch */
ctl_bus_db_oe=1; /* Read DB pads to internal data bus */
ctl_state_ixiy_we=1; ctl_state_ixiy_clr=!setIXIY; /* Clear IX/IY flag */
ctl_state_tbl_clr=!setCBED; /* Clear CB/ED prefix */
ctl_ir_we=1;
ctl_bus_zero_oe=in_halt; ctl_bus_ff_oe=(in_intr & (im1 | im2)) | in_nmi; end
if (M1 && T3) begin
ctl_reg_sys_we=1; ctl_reg_sel_ir=1; ctl_reg_sys_hilo=2'b11; /* Write 16-bit IR */
ctl_inc_cy=pc_inc; /* Increment */
ctl_bus_inc_oe=1; ctl_apin_mux2=1; /* Apin sourced from AL */
ctl_inc_limit6=1; /* Limit the incrementer to 6 bits */ end
if (M1 && T4) begin
ctl_eval_cond=1; /* Evaluate flags condition based on the opcode[5:3] */ end
end
 
/a-z80/trunk/cpu/control/simulation/modelsim/test_control.mpf
442,7 → 442,7
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 7
Project_Files_Count = 8
Project_File_0 = $ROOT/cpu/control/interrupts.v
Project_File_P_0 = compile_order 1 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_1 = $ROOT/cpu/control/pin_control.v
449,14 → 449,16
Project_File_P_1 = compile_order 6 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_2 = $ROOT/cpu/control/resets.v
Project_File_P_2 = compile_order 4 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_3 = $ROOT/cpu/control/test_interrupts.sv
Project_File_P_3 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_4 = $ROOT/cpu/control/test_pin_control.sv
Project_File_P_4 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_5 = $ROOT/cpu/control/test_reset.sv
Project_File_P_5 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_6 = $ROOT/cpu/control/test_sequencer.sv
Project_File_P_6 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_3 = $ROOT/cpu/control/sequencer.v
Project_File_P_3 = compile_order 7 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type verilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat 0 vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_4 = $ROOT/cpu/control/test_interrupts.sv
Project_File_P_4 = compile_order 2 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder interrupts group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_5 = $ROOT/cpu/control/test_pin_control.sv
Project_File_P_5 = compile_order 0 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder {pin control} group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_6 = $ROOT/cpu/control/test_reset.sv
Project_File_P_6 = compile_order 3 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder reset group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_File_7 = $ROOT/cpu/control/test_sequencer.sv
Project_File_P_7 = compile_order 5 compile_to work cover_branch 0 cover_cond 0 cover_covercells 0 cover_excludedefault 0 cover_expr 0 cover_exttoggle 0 cover_fsm 0 cover_nofec 0 cover_noshort 0 cover_optlevel 3 cover_stmt 0 cover_toggle 0 dont_compile 0 file_type systemverilog folder sequencer group_id 0 last_compile 1 ood 0 toggle - vlog_0InOptions {} vlog_1995compat SV vlog_disableopt 0 vlog_enable0In 0 vlog_hazard 0 vlog_nodebug 0 vlog_noload 0 vlog_options {} vlog_protect 0 vlog_showsource 0 vlog_upper 0 voptflow 1
Project_Sim_Count = 4
Project_Sim_0 = Test pin control
Project_Sim_P_0 = timing default -sdfnoerror 0 -t default -nofileshare 0 +no_pulse_msg 0 -Lf {} Generics {} +notimingchecks 0 ok 1 folder {pin control} +pulse_e {} additional_dus work.test_pin_control -assertfile {} -std_output {} -L {} -nopsl 0 -nosva 0 +pulse_r {} -absentisempty 0 -assertcover 0 -multisource_delay {} OtherArgs {} -vital2.2b 0 is_vopt_flow 0 -memprof 0 -noglitch 0 -0in_options {} selected_du {} -sdf {} -hazards 0 -0in 0 vopt_env 1 -coverage 0 +plusarg {} -assertdebug 0 -wlf {} -sdfnowarn 0 -std_input {}
/a-z80/trunk/cpu/control/genmatrix.py
2,8 → 2,8
#
# This script reads A-Z80 instruction timing data from a spreadsheet text file
# and generates a Verilog include file defining the control block execution matrix.
# Macros in the timing spreadsheet are substituted using a list of keys stored
# in the macros file. See the macro file for the format information.
# Token keywords in the timing spreadsheet are substituted using a list of keys
# stored in the macros file. See the macro file for the format information.
#
# Input timing file is exported from the Excel file as a TAB-delimited text file.
#
167,7 → 167,7
imatrix.append("{0}{1} end".format(state, action))
 
# Create a file containing the logic matrix code
with open('exec_matrix.i', 'w') as file:
with open('exec_matrix.vh', 'w') as file:
file.write("// Automatically generated by genmatrix.py\n")
# If there were errors, print them first (and output to the console)
if len(errors)>0:
178,5 → 178,5
for item in imatrix:
file.write("{}\n".format(item))
 
# Touch a file that includes 'exec_matrix.i' to ensure it will recompile correctly
# Touch a file that includes 'exec_matrix.vh' to ensure it will recompile correctly
os.utime("execute.sv", None)
/a-z80/trunk/cpu/control/execute.sv
22,7 → 22,7
//----------------------------------------------------------
// Control signals generated by the instruction execution
//----------------------------------------------------------
`include "exec_module.i"
`include "exec_module.vh"
 
output logic nextM, // Last M cycle of any instruction
output logic setM1, // Last T clock of any instruction
134,7 → 134,7
// Default assignment of all control outputs to 0 to prevent generating
// latches.
//-------------------------------------------------------------------------
`include "exec_zero.i"
`include "exec_zero.vh"
 
// Reset internal control wires
validPLA = 0; // Every valid PLA entry will set it
153,7 → 153,7
//-------------------------------------------------------------------------
// State-based signal assignment
//-------------------------------------------------------------------------
`include "exec_matrix.i"
`include "exec_matrix.vh"
 
// List more specific combinational signal assignments after the include
//-------------------------------------------------------------------------
/a-z80/trunk/cpu/control/genref.py
25,7 → 25,7
# Create 2 files that should be included in the execution engine block:
# 1. A module arguments section
# 2. A file containing the code to initialize control wires to zero
with open('exec_module.i', 'w') as file1, open('exec_zero.i', 'w') as file0:
with open('exec_module.vh', 'w') as file1, open('exec_zero.vh', 'w') as file0:
file1.write("// Automatically generated by genref.py\n")
file0.write("// Automatically generated by genref.py\n")
 
45,7 → 45,7
wires.append(info[2] + " " + info[3].translate(None, ';,'))
 
if len(wires)>0:
with open('exec_module.i', 'a') as file1, open('exec_zero.i', 'a') as file0:
with open('exec_module.vh', 'a') as file1, open('exec_zero.vh', 'a') as file0:
print "MODULE: " + infile
file0.write("\n// Module: " + infile + "\n")
file1.write("\n// Module: " + infile + "\n")
59,5 → 59,5
else:
file0.write(wire + " = 0;\n")
 
# Touch a file that includes 'exec_module.i' and 'exec_zero.i' to ensure it will recompile correctly
# Touch a file that includes 'exec_module.vh' and 'exec_zero.vh' to ensure it will recompile correctly
os.utime("execute.sv", None)
/a-z80/trunk/cpu/control/exec_zero.vh
0,0 → 1,127
// Automatically generated by genref.py
 
// Module: control/decode_state.v
ctl_state_iy_set = 0;
ctl_state_ixiy_clr = 0;
ctl_state_ixiy_we = 0;
ctl_state_halt_set = 0;
ctl_state_tbl_clr = 0;
ctl_state_tbl_ed_set = 0;
ctl_state_tbl_cb_set = 0;
ctl_state_alu = 0;
ctl_repeat_we = 0;
 
// Module: control/interrupts.v
ctl_iff1_iff2 = 0;
ctl_iffx_we = 0;
ctl_iffx_bit = 0;
ctl_im_we = 0;
ctl_no_ints = 0;
 
// Module: control/ir.v
ctl_ir_we = 0;
 
// Module: control/memory_ifc.v
ctl_mRead = 0;
ctl_mWrite = 0;
ctl_iorw = 0;
 
// Module: alu/alu_control.v
ctl_shift_en = 0;
ctl_daa_oe = 0;
ctl_alu_op_low = 0;
ctl_cond_short = 0;
ctl_alu_core_hf = 0;
ctl_eval_cond = 0;
ctl_66_oe = 0;
ctl_pf_sel = 0;
 
// Module: alu/alu_select.v
ctl_alu_oe = 0;
ctl_alu_shift_oe = 0;
ctl_alu_op2_oe = 0;
ctl_alu_res_oe = 0;
ctl_alu_op1_oe = 0;
ctl_alu_bs_oe = 0;
ctl_alu_op1_sel_bus = 0;
ctl_alu_op1_sel_low = 0;
ctl_alu_op1_sel_zero = 0;
ctl_alu_op2_sel_zero = 0;
ctl_alu_op2_sel_bus = 0;
ctl_alu_op2_sel_lq = 0;
ctl_alu_sel_op2_neg = 0;
ctl_alu_sel_op2_high = 0;
ctl_alu_core_R = 0;
ctl_alu_core_V = 0;
ctl_alu_core_S = 0;
 
// Module: alu/alu_flags.v
ctl_flags_oe = 0;
ctl_flags_bus = 0;
ctl_flags_alu = 0;
ctl_flags_nf_set = 0;
ctl_flags_cf_set = 0;
ctl_flags_cf_cpl = 0;
ctl_flags_cf_we = 0;
ctl_flags_sz_we = 0;
ctl_flags_xy_we = 0;
ctl_flags_hf_we = 0;
ctl_flags_pf_we = 0;
ctl_flags_nf_we = 0;
ctl_flags_cf2_we = 0;
ctl_flags_hf_cpl = 0;
ctl_flags_use_cf2 = 0;
ctl_flags_hf2_we = 0;
ctl_flags_nf_clr = 0;
ctl_alu_zero_16bit = 0;
ctl_flags_cf2_sel = 0;
 
// Module: registers/reg_file.v
ctl_sw_4d = 0;
ctl_sw_4u = 0;
ctl_reg_in_hi = 0;
ctl_reg_in_lo = 0;
ctl_reg_out_lo = 0;
ctl_reg_out_hi = 0;
 
// Module: registers/reg_control.v
ctl_reg_exx = 0;
ctl_reg_ex_af = 0;
ctl_reg_ex_de_hl = 0;
ctl_reg_use_sp = 0;
ctl_reg_sel_pc = 0;
ctl_reg_sel_ir = 0;
ctl_reg_sel_wz = 0;
ctl_reg_gp_we = 0;
ctl_reg_not_pc = 0;
ctl_reg_sys_we_lo = 0;
ctl_reg_sys_we_hi = 0;
ctl_reg_sys_we = 0;
ctl_reg_gp_hilo = 0;
ctl_reg_gp_sel = 0;
ctl_reg_sys_hilo = 0;
 
// Module: bus/address_latch.v
ctl_inc_cy = 0;
ctl_inc_dec = 0;
ctl_inc_zero = 0;
ctl_al_we = 0;
ctl_inc_limit6 = 0;
ctl_bus_inc_oe = 0;
ctl_apin_mux = 0;
ctl_apin_mux2 = 0;
 
// Module: bus/bus_control.v
ctl_bus_ff_oe = 0;
ctl_bus_zero_oe = 0;
ctl_bus_db_oe = 0;
 
// Module: bus/bus_switch.sv
ctl_sw_1u = 0;
ctl_sw_1d = 0;
ctl_sw_2u = 0;
ctl_sw_2d = 0;
ctl_sw_mask543_en = 0;
 
// Module: bus/data_pins.v
ctl_bus_db_we = 0;
/a-z80/trunk/cpu/top-level-files.txt
5,7 → 5,7
------ Control block -------
control/clk_delay.v
control/decode_state.v
control/exec_module.i
control/exec_module.vh
control/execute.sv
control/interrupts.v
control/ir.v
/a-z80/trunk/cpu/bus/bus_switch.sv
6,7 → 6,7
// This module provides control data bus switch signals. The sole purpose of
// having these wires defined in this module is to get all control signals
// (which are processed by genglobals.py) to appear in the list of global
// control signals ("globals.i") for consistency.
// control signals ("globals.vh") for consistency.
//============================================================================
 
module bus_switch
/a-z80/trunk/cpu/toplevel/globals.i File deleted
/a-z80/trunk/cpu/toplevel/test_fuse.i File deleted
/a-z80/trunk/cpu/toplevel/core.i File deleted
/a-z80/trunk/cpu/toplevel/genfuse.py
92,7 → 92,7
 
#---------------------------- START -----------------------------------
# Create a file that should be included in the test_fuse source
ftest = open('test_fuse.i', 'w')
ftest = open('test_fuse.vh', 'w')
ftest.write("// Automatically generated by genfuse.py\n\n")
 
# Initial pre-test state is reset and control signals asserted
282,5 → 282,5
ftest.write("`define TOTAL_CLKS " + str(total_clks) + "\n")
ftest.write("$fdisplay(f,\"=== Tests completed ===\");\n")
 
# Touch a file that includes 'test_fuse.i' to ensure it will recompile correctly
# Touch a file that includes 'test_fuse.vh' to ensure it will recompile correctly
os.utime("test_fuse.sv", None)
/a-z80/trunk/cpu/toplevel/z80_top_ifc_n.sv
8,7 → 8,7
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Include core A-Z80 level connecting all internal modules
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "core.i"
`include "core.vh"
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Address, Data and Control bus drivers connecting to external pins
/a-z80/trunk/cpu/toplevel/test_fuse.sv
20,7 → 20,7
 
// Run all the tests and write the result to a file
f = $fopen("fuse.result.txt");
`include "test_fuse.i"
`include "test_fuse.vh"
$fclose(f);
 
end : init
/a-z80/trunk/cpu/toplevel/globals.vh
0,0 → 1,291
// Automatically generated by genglobals.py
 
// Module: control/clk_delay.v
wire hold_clk_iorq;
wire hold_clk_wait;
wire iorq_Tw;
wire busack;
wire pin_control_oe;
wire hold_clk_busrq;
 
// Module: control/decode_state.v
wire in_halt;
wire table_cb;
wire table_ed;
wire table_xx;
wire use_ix;
wire use_ixiy;
wire in_alu;
wire repeat_en;
 
// Module: control/exec_module.vh
wire ctl_state_iy_set;
wire ctl_state_ixiy_clr;
wire ctl_state_ixiy_we;
wire ctl_state_halt_set;
wire ctl_state_tbl_clr;
wire ctl_state_tbl_ed_set;
wire ctl_state_tbl_cb_set;
wire ctl_state_alu;
wire ctl_repeat_we;
wire ctl_iff1_iff2;
wire ctl_iffx_we;
wire ctl_iffx_bit;
wire ctl_im_we;
wire ctl_no_ints;
wire ctl_ir_we;
wire ctl_mRead;
wire ctl_mWrite;
wire ctl_iorw;
wire ctl_shift_en;
wire ctl_daa_oe;
wire ctl_alu_op_low;
wire ctl_cond_short;
wire ctl_alu_core_hf;
wire ctl_eval_cond;
wire ctl_66_oe;
wire [1:0] ctl_pf_sel;
wire ctl_alu_oe;
wire ctl_alu_shift_oe;
wire ctl_alu_op2_oe;
wire ctl_alu_res_oe;
wire ctl_alu_op1_oe;
wire ctl_alu_bs_oe;
wire ctl_alu_op1_sel_bus;
wire ctl_alu_op1_sel_low;
wire ctl_alu_op1_sel_zero;
wire ctl_alu_op2_sel_zero;
wire ctl_alu_op2_sel_bus;
wire ctl_alu_op2_sel_lq;
wire ctl_alu_sel_op2_neg;
wire ctl_alu_sel_op2_high;
wire ctl_alu_core_R;
wire ctl_alu_core_V;
wire ctl_alu_core_S;
wire ctl_flags_oe;
wire ctl_flags_bus;
wire ctl_flags_alu;
wire ctl_flags_nf_set;
wire ctl_flags_cf_set;
wire ctl_flags_cf_cpl;
wire ctl_flags_cf_we;
wire ctl_flags_sz_we;
wire ctl_flags_xy_we;
wire ctl_flags_hf_we;
wire ctl_flags_pf_we;
wire ctl_flags_nf_we;
wire ctl_flags_cf2_we;
wire ctl_flags_hf_cpl;
wire ctl_flags_use_cf2;
wire ctl_flags_hf2_we;
wire ctl_flags_nf_clr;
wire ctl_alu_zero_16bit;
wire [1:0] ctl_flags_cf2_sel;
wire ctl_sw_4d;
wire ctl_sw_4u;
wire ctl_reg_in_hi;
wire ctl_reg_in_lo;
wire ctl_reg_out_lo;
wire ctl_reg_out_hi;
wire ctl_reg_exx;
wire ctl_reg_ex_af;
wire ctl_reg_ex_de_hl;
wire ctl_reg_use_sp;
wire ctl_reg_sel_pc;
wire ctl_reg_sel_ir;
wire ctl_reg_sel_wz;
wire ctl_reg_gp_we;
wire ctl_reg_not_pc;
wire ctl_reg_sys_we_lo;
wire ctl_reg_sys_we_hi;
wire ctl_reg_sys_we;
wire [1:0] ctl_reg_gp_hilo;
wire [1:0] ctl_reg_gp_sel;
wire [1:0] ctl_reg_sys_hilo;
wire ctl_inc_cy;
wire ctl_inc_dec;
wire ctl_inc_zero;
wire ctl_al_we;
wire ctl_inc_limit6;
wire ctl_bus_inc_oe;
wire ctl_apin_mux;
wire ctl_apin_mux2;
wire ctl_bus_ff_oe;
wire ctl_bus_zero_oe;
wire ctl_bus_db_oe;
wire ctl_sw_1u;
wire ctl_sw_1d;
wire ctl_sw_2u;
wire ctl_sw_2d;
wire ctl_sw_mask543_en;
wire ctl_bus_db_we;
 
// Module: control/execute.sv
wire nextM;
wire setM1;
wire fFetch;
wire fMRead;
wire fMWrite;
wire fIORead;
wire fIOWrite;
 
// Module: control/interrupts.v
wire iff1;
wire iff2;
wire im1;
wire im2;
wire in_nmi;
wire in_intr;
 
// Module: control/ir.v
wire [7:0] opcode;
 
// Module: control/pin_control.v
wire bus_ab_pin_we;
wire bus_db_pin_oe;
wire bus_db_pin_re;
 
// Module: control/pla_decode.sv
wire [104:0] pla;
 
// Module: control/resets.v
wire clrpc;
wire nreset;
 
// Module: control/memory_ifc.v
wire nM1_out;
wire nRFSH_out;
wire nMREQ_out;
wire nRD_out;
wire nWR_out;
wire nIORQ_out;
wire latch_wait;
 
// Module: control/sequencer.v
wire M1;
wire M2;
wire M3;
wire M4;
wire M5;
wire M6;
wire T1;
wire T2;
wire T3;
wire T4;
wire T5;
wire T6;
wire timings_en;
 
// Module: alu/alu_control.v
wire alu_shift_in;
wire alu_shift_right;
wire alu_shift_left;
wire shift_cf_out;
wire alu_parity_in;
wire flags_cond_true;
wire daa_cf_out;
wire pf_sel;
wire alu_op_low;
wire alu_core_cf_in;
wire [7:0] db;
 
// Module: alu/alu_select.v
wire alu_oe;
wire alu_shift_oe;
wire alu_op2_oe;
wire alu_res_oe;
wire alu_op1_oe;
wire alu_bs_oe;
wire alu_op1_sel_bus;
wire alu_op1_sel_low;
wire alu_op1_sel_zero;
wire alu_op2_sel_zero;
wire alu_op2_sel_bus;
wire alu_op2_sel_lq;
wire alu_sel_op2_neg;
wire alu_sel_op2_high;
wire alu_core_R;
wire alu_core_V;
wire alu_core_S;
 
// Module: alu/alu_flags.v
wire flags_sf;
wire flags_zf;
wire flags_hf;
wire flags_pf;
wire flags_cf;
wire flags_nf;
wire flags_cf_latch;
wire flags_hf2;
 
// Module: alu/alu.v
wire alu_zero;
wire alu_parity_out;
wire alu_high_eq_9;
wire alu_high_gt_9;
wire alu_low_gt_9;
wire alu_shift_db0;
wire alu_shift_db7;
wire alu_core_cf_out;
wire alu_sf_out;
wire alu_yf_out;
wire alu_xf_out;
wire alu_vf_out;
wire [3:0] test_db_high;
wire [3:0] test_db_low;
 
// Module: registers/reg_control.v
wire reg_sel_bc;
wire reg_sel_bc2;
wire reg_sel_ix;
wire reg_sel_iy;
wire reg_sel_de;
wire reg_sel_hl;
wire reg_sel_de2;
wire reg_sel_hl2;
wire reg_sel_af;
wire reg_sel_af2;
wire reg_sel_wz;
wire reg_sel_pc;
wire reg_sel_ir;
wire reg_sel_sp;
wire reg_sel_gp_hi;
wire reg_sel_gp_lo;
wire reg_sel_sys_lo;
wire reg_sel_sys_hi;
wire reg_gp_we;
wire reg_sys_we_lo;
wire reg_sys_we_hi;
 
// Module: bus/address_latch.v
wire address_is_1;
wire [15:0] address;
 
// Module: bus/address_pins.v
wire [15:0] abus;
 
// Module: bus/bus_control.v
wire bus_db_oe;
 
// Module: bus/bus_switch.sv
wire bus_sw_1u;
wire bus_sw_1d;
wire bus_sw_2u;
wire bus_sw_2d;
wire bus_sw_mask543_en;
 
// Module: bus/control_pins_n.v
wire nmi;
wire busrq;
wire clk;
wire intr;
wire mwait;
wire reset_in;
wire pin_nM1;
wire pin_nMREQ;
wire pin_nIORQ;
wire pin_nRD;
wire pin_nWR;
wire pin_nRFSH;
wire pin_nHALT;
wire pin_nBUSACK;
/a-z80/trunk/cpu/toplevel/z80_top_direct_n.sv
27,7 → 27,7
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Include core A-Z80 level connecting all internal modules
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`include "core.i"
`include "core.vh"
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Address, Data and Control bus drivers connecting to external pins
/a-z80/trunk/cpu/toplevel/genglobals.py
22,7 → 22,7
files = f.read().splitlines()
 
# Create a file that should be included in the top-level source
with open('globals.i', 'w') as file1:
with open('globals.vh', 'w') as file1:
file1.write("// Automatically generated by genglobals.py\n")
 
# Keep track of duplicated symbols across all files
46,7 → 46,7
wires.append(info[2].translate(None, ';,'))
 
if len(wires)>0:
with open('globals.i', 'a') as file1:
with open('globals.vh', 'a') as file1:
file1.write("\n// Module: " + infile + "\n")
for wire in wires:
# Everything in globals is a wire
57,7 → 57,7
file1.write("wire " + wire + ";\n")
globals.append(wire)
 
# Touch files that include 'globals.i' to ensure it will recompile correctly
os.utime("core.i", None)
# Touch files that include 'globals.vh' to ensure it will recompile correctly
os.utime("core.vh", None)
os.utime("z80_top_direct_n.sv", None)
os.utime("z80_top_ifc_n.sv", None)
/a-z80/trunk/cpu/toplevel/core.vh
0,0 → 1,81
//============================================================================
// A-Z80 core, instantiates and connects all internal blocks.
//
// This file is included by the "z80_top_ifc_n" and "z80_top_direct" providing
// interface binding and direct (no interface) binding.
//============================================================================
 
// Include a list of top-level signal wires
`include "globals.vh"
 
// Specific to Modelsim, some modules in the schematics need to be pre-initialized
// to avoid starting simulations with unknown values in selected flip flops.
// When synthesized, the CPU RESET input signal will do the work.
reg fpga_reset = 0;
initial begin
fpga_reset = 1;
#1 fpga_reset = 0;
end
 
// Define internal data bus partitions separated by data bus switches
wire [7:0] db0; // Segment connecting data pins and IR
wire [7:0] db1; // Segment with ALU
wire [7:0] db2; // Segment with msb part of the register address-side interface
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Control block
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Collect the PLA instruction decode prefix bitfield
logic [6:0] prefix;
assign prefix = { ~use_ixiy, use_ixiy, ~in_halt, in_alu, table_xx, table_cb, table_ed };
 
ir instruction_reg_( .*, .db(db0[7:0]) );
pla_decode pla_decode_( .* );
resets reset_block_( .* );
sequencer sequencer_( .* );
execute execute_( .* );
interrupts interrupts_( .*, .db(db0[4:3]) );
decode_state decode_state_( .* );
clk_delay clk_delay_( .* );
pin_control pin_control_( .* );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// ALU and ALU control, including the flags
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
alu_control alu_control_( .*, .db(db1[7:0]), .op543({pla[104],pla[103],pla[102]}) );
alu_select alu_select_( .* );
alu_flags alu_flags_( .*, .db(db1[7:0]) );
alu alu_( .*, .db(db2[7:0]), .bsel(db0[5:3]) );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Register file and register control
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [7:0] db_hi_as;
wire [7:0] db_lo_as;
 
reg_file reg_file_( .*, .db_hi_ds(db2[7:0]), .db_lo_ds(db1[7:0]), .db_hi_as(db_hi_as[7:0]), .db_lo_as(db_lo_as[7:0]) );
reg_control reg_control_( .* );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Address latch (with the incrementer)
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
address_latch address_latch_( .*, .abus({db_hi_as[7:0], db_lo_as[7:0]}) );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Timing control of the external pins
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire nM1_int;
assign nM1_int = !((setM1 & nextM) | (fFetch & T1));
memory_ifc memory_ifc_( .* );
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Data path within the CPU in various forms, ending with data pins
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
bus_switch bus_switch_( .* );
data_switch sw2_( .sw_up_en(bus_sw_2u), .sw_down_en(bus_sw_2d), .db_up(db1[7:0]), .db_down(db2[7:0]) );
 
// Controls writers to the first section of the data bus
bus_control bus_control_( .*, .db(db0[7:0]) );
 
// Data switch SW1 with the data mask
data_switch_mask sw1_( .sw_mask543_en(bus_sw_mask543_en), .sw_up_en(bus_sw_1u), .sw_down_en(bus_sw_1d), .db_up(db0[7:0]), .db_down(db1[7:0]) );
/a-z80/trunk/cpu/toplevel/test_fuse.vh
0,0 → 1,5065
// Automatically generated by genfuse.py
 
force dut.reg_file_.reg_gp_we=0;
force dut.reg_control_.ctl_reg_sys_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
#2
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode 00 NOP");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'h00;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h00) $fdisplay(f,"* Reg af a=%h !=00",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h00) $fdisplay(f,"* Reg bc c=%h !=00",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h00) $fdisplay(f,"* Reg bc b=%h !=00",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h00) $fdisplay(f,"* Reg de e=%h !=00",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h00) $fdisplay(f,"* Reg de d=%h !=00",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h00) $fdisplay(f,"* Reg hl l=%h !=00",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h00) $fdisplay(f,"* Reg hl h=%h !=00",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode ed67 RRD");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h24;
force dut.reg_file_.b2v_latch_af_hi.db=8'h36;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h6a;
force dut.reg_file_.b2v_latch_bc_hi.db=8'hb1;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'hdb;
force dut.reg_file_.b2v_latch_de_hi.db=8'ha4;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'hde;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hb9;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'hed;
ram.Mem[1] = 8'h67;
// Preset memory
ram.Mem[47582] = 8'h93;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#34 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h24) $fdisplay(f,"* Reg af f=%h !=24",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h33) $fdisplay(f,"* Reg af a=%h !=33",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h6a) $fdisplay(f,"* Reg bc c=%h !=6a",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hb1) $fdisplay(f,"* Reg bc b=%h !=b1",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hdb) $fdisplay(f,"* Reg de e=%h !=db",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'ha4) $fdisplay(f,"* Reg de d=%h !=a4",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'hde) $fdisplay(f,"* Reg hl l=%h !=de",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb9) $fdisplay(f,"* Reg hl h=%h !=b9",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[47582]!==8'h69) $fdisplay(f,"* Mem[b9de]=%h !=69",ram.Mem[47582]);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode ed6f RLD");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h8b;
force dut.reg_file_.b2v_latch_af_hi.db=8'h65;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h7a;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h7a;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'hf0;
force dut.reg_file_.b2v_latch_de_hi.db=8'hec;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'h3c;
force dut.reg_file_.b2v_latch_hl_hi.db=8'h40;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'hed;
ram.Mem[1] = 8'h6f;
// Preset memory
ram.Mem[16444] = 8'hc4;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#34 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h2d) $fdisplay(f,"* Reg af f=%h !=2d",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h6c) $fdisplay(f,"* Reg af a=%h !=6c",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h7a) $fdisplay(f,"* Reg bc c=%h !=7a",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h7a) $fdisplay(f,"* Reg bc b=%h !=7a",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf0) $fdisplay(f,"* Reg de e=%h !=f0",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hec) $fdisplay(f,"* Reg de d=%h !=ec",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h3c) $fdisplay(f,"* Reg hl l=%h !=3c",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h40) $fdisplay(f,"* Reg hl h=%h !=40",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
if (ram.Mem[16444]!==8'h45) $fdisplay(f,"* Mem[403c]=%h !=45",ram.Mem[16444]);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode 81 ADD A,C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'h81;
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h31) $fdisplay(f,"* Reg af f=%h !=31",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h30) $fdisplay(f,"* Reg af a=%h !=30",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode cb41 BIT 0,C");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'h9e;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h43;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h1b;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h4e;
force dut.reg_file_.b2v_latch_de_hi.db=8'h95;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'he9;
force dut.reg_file_.b2v_latch_hl_hi.db=8'h7b;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'hcb;
ram.Mem[1] = 8'h41;
// Preset memory
ram.Mem[31721] = 8'hf7;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h10) $fdisplay(f,"* Reg af f=%h !=10",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h9e) $fdisplay(f,"* Reg af a=%h !=9e",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h43) $fdisplay(f,"* Reg bc c=%h !=43",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h1b) $fdisplay(f,"* Reg bc b=%h !=1b",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h4e) $fdisplay(f,"* Reg de e=%h !=4e",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h95) $fdisplay(f,"* Reg de d=%h !=95",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'he9) $fdisplay(f,"* Reg hl l=%h !=e9",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h7b) $fdisplay(f,"* Reg hl h=%h !=7b",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode cb93 RES 2,E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hc2;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h05;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h4e;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'hf8;
force dut.reg_file_.b2v_latch_de_hi.db=8'hb3;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'h34;
force dut.reg_file_.b2v_latch_hl_hi.db=8'h22;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'hcb;
ram.Mem[1] = 8'h93;
// Preset memory
ram.Mem[8756] = 8'ha0;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hc2) $fdisplay(f,"* Reg af a=%h !=c2",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h05) $fdisplay(f,"* Reg bc c=%h !=05",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h4e) $fdisplay(f,"* Reg bc b=%h !=4e",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'hf8) $fdisplay(f,"* Reg de e=%h !=f8",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hb3) $fdisplay(f,"* Reg de d=%h !=b3",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h34) $fdisplay(f,"* Reg hl l=%h !=34",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'h22) $fdisplay(f,"* Reg hl h=%h !=22",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode cbe5 SET 4,L");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hca;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_bc_hi.db=8'hdf;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h88;
force dut.reg_file_.b2v_latch_de_hi.db=8'hd5;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'h8f;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hb4;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'hcb;
ram.Mem[1] = 8'he5;
// Preset memory
ram.Mem[46223] = 8'hcf;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#14 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h00) $fdisplay(f,"* Reg af f=%h !=00",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hca) $fdisplay(f,"* Reg af a=%h !=ca",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h0d) $fdisplay(f,"* Reg bc c=%h !=0d",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'hdf) $fdisplay(f,"* Reg bc b=%h !=df",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h88) $fdisplay(f,"* Reg de e=%h !=88",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'hd5) $fdisplay(f,"* Reg de d=%h !=d5",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'h9f) $fdisplay(f,"* Reg hl l=%h !=9f",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hb4) $fdisplay(f,"* Reg hl h=%h !=b4",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0002) $fdisplay(f,"* PC=%h !=0002",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h02) $fdisplay(f,"* Reg ir r=%h !=02",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode 8c ADC A,H");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'h8c;
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h91) $fdisplay(f,"* Reg af f=%h !=91",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd1) $fdisplay(f,"* Reg af a=%h !=d1",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode 92 SUB D");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'h92;
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h82) $fdisplay(f,"* Reg af f=%h !=82",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hd5) $fdisplay(f,"* Reg af a=%h !=d5",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode 9d SBC A,L");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'h9d;
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h1a) $fdisplay(f,"* Reg af f=%h !=1a",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h4f) $fdisplay(f,"* Reg af a=%h !=4f",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode a3 AND E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'ha3;
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h14) $fdisplay(f,"* Reg af f=%h !=14",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'h05) $fdisplay(f,"* Reg af a=%h !=05",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode ae XOR (HL)");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'hae;
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#12 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,"* Reg af f=%h !=a8",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hbc) $fdisplay(f,"* Reg af a=%h !=bc",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode b4 OR H");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'hb4;
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'ha8) $fdisplay(f,"* Reg af f=%h !=a8",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hfd) $fdisplay(f,"* Reg af a=%h !=fd",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode bf CP A");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'hf5;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h3b;
force dut.reg_file_.b2v_latch_bc_hi.db=8'h0f;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'h0d;
force dut.reg_file_.b2v_latch_de_hi.db=8'h20;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'ha6;
force dut.reg_file_.b2v_latch_hl_hi.db=8'hdc;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'hbf;
// Preset memory
ram.Mem[56486] = 8'h49;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2
#1 force dut.reg_file_.reg_gp_we=0;
force dut.z80_top_ifc_n.fpga_reset=1;
if (dut.reg_file_.b2v_latch_af_lo.latch!==8'h62) $fdisplay(f,"* Reg af f=%h !=62",dut.reg_file_.b2v_latch_af_lo.latch);
if (dut.reg_file_.b2v_latch_af_hi.latch!==8'hf5) $fdisplay(f,"* Reg af a=%h !=f5",dut.reg_file_.b2v_latch_af_hi.latch);
if (dut.reg_file_.b2v_latch_bc_lo.latch!==8'h3b) $fdisplay(f,"* Reg bc c=%h !=3b",dut.reg_file_.b2v_latch_bc_lo.latch);
if (dut.reg_file_.b2v_latch_bc_hi.latch!==8'h0f) $fdisplay(f,"* Reg bc b=%h !=0f",dut.reg_file_.b2v_latch_bc_hi.latch);
if (dut.reg_file_.b2v_latch_de_lo.latch!==8'h0d) $fdisplay(f,"* Reg de e=%h !=0d",dut.reg_file_.b2v_latch_de_lo.latch);
if (dut.reg_file_.b2v_latch_de_hi.latch!==8'h20) $fdisplay(f,"* Reg de d=%h !=20",dut.reg_file_.b2v_latch_de_hi.latch);
if (dut.reg_file_.b2v_latch_hl_lo.latch!==8'ha6) $fdisplay(f,"* Reg hl l=%h !=a6",dut.reg_file_.b2v_latch_hl_lo.latch);
if (dut.reg_file_.b2v_latch_hl_hi.latch!==8'hdc) $fdisplay(f,"* Reg hl h=%h !=dc",dut.reg_file_.b2v_latch_hl_hi.latch);
if (dut.reg_file_.b2v_latch_af2_lo.latch!==8'h00) $fdisplay(f,"* Reg af2 f=%h !=00",dut.reg_file_.b2v_latch_af2_lo.latch);
if (dut.reg_file_.b2v_latch_af2_hi.latch!==8'h00) $fdisplay(f,"* Reg af2 a=%h !=00",dut.reg_file_.b2v_latch_af2_hi.latch);
if (dut.reg_file_.b2v_latch_bc2_lo.latch!==8'h00) $fdisplay(f,"* Reg bc2 c=%h !=00",dut.reg_file_.b2v_latch_bc2_lo.latch);
if (dut.reg_file_.b2v_latch_bc2_hi.latch!==8'h00) $fdisplay(f,"* Reg bc2 b=%h !=00",dut.reg_file_.b2v_latch_bc2_hi.latch);
if (dut.reg_file_.b2v_latch_de2_lo.latch!==8'h00) $fdisplay(f,"* Reg de2 e=%h !=00",dut.reg_file_.b2v_latch_de2_lo.latch);
if (dut.reg_file_.b2v_latch_de2_hi.latch!==8'h00) $fdisplay(f,"* Reg de2 d=%h !=00",dut.reg_file_.b2v_latch_de2_hi.latch);
if (dut.reg_file_.b2v_latch_hl2_lo.latch!==8'h00) $fdisplay(f,"* Reg hl2 l=%h !=00",dut.reg_file_.b2v_latch_hl2_lo.latch);
if (dut.reg_file_.b2v_latch_hl2_hi.latch!==8'h00) $fdisplay(f,"* Reg hl2 h=%h !=00",dut.reg_file_.b2v_latch_hl2_hi.latch);
if (dut.reg_file_.b2v_latch_ix_lo.latch!==8'h00) $fdisplay(f,"* Reg ix x=%h !=00",dut.reg_file_.b2v_latch_ix_lo.latch);
if (dut.reg_file_.b2v_latch_ix_hi.latch!==8'h00) $fdisplay(f,"* Reg ix i=%h !=00",dut.reg_file_.b2v_latch_ix_hi.latch);
if (dut.reg_file_.b2v_latch_iy_lo.latch!==8'h00) $fdisplay(f,"* Reg iy y=%h !=00",dut.reg_file_.b2v_latch_iy_lo.latch);
if (dut.reg_file_.b2v_latch_iy_hi.latch!==8'h00) $fdisplay(f,"* Reg iy i=%h !=00",dut.reg_file_.b2v_latch_iy_hi.latch);
if (dut.reg_file_.b2v_latch_sp_lo.latch!==8'h00) $fdisplay(f,"* Reg sp p=%h !=00",dut.reg_file_.b2v_latch_sp_lo.latch);
if (dut.reg_file_.b2v_latch_sp_hi.latch!==8'h00) $fdisplay(f,"* Reg sp s=%h !=00",dut.reg_file_.b2v_latch_sp_hi.latch);
if (pc!==16'h0001) $fdisplay(f,"* PC=%h !=0001",pc);
if (dut.reg_file_.b2v_latch_ir_lo.latch!==8'h01) $fdisplay(f,"* Reg ir r=%h !=01",dut.reg_file_.b2v_latch_ir_lo.latch);
if (dut.reg_file_.b2v_latch_ir_hi.latch!==8'h00) $fdisplay(f,"* Reg ir i=%h !=00",dut.reg_file_.b2v_latch_ir_hi.latch);
//--------------------------------------------------------------------------------
force dut.instruction_reg_.ctl_ir_we=1;
force dut.instruction_reg_.db=0;
#2 release dut.instruction_reg_.ctl_ir_we;
release dut.instruction_reg_.db;
$fdisplay(f,"Testing opcode 43 LD B,E");
// Preset af
force dut.reg_file_.b2v_latch_af_lo.we=1;
force dut.reg_file_.b2v_latch_af_hi.we=1;
force dut.reg_file_.b2v_latch_af_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af_hi.db=8'h02;
#2 release dut.reg_file_.b2v_latch_af_lo.we;
release dut.reg_file_.b2v_latch_af_hi.we;
release dut.reg_file_.b2v_latch_af_lo.db;
release dut.reg_file_.b2v_latch_af_hi.db;
// Preset bc
force dut.reg_file_.b2v_latch_bc_lo.we=1;
force dut.reg_file_.b2v_latch_bc_hi.we=1;
force dut.reg_file_.b2v_latch_bc_lo.db=8'h98;
force dut.reg_file_.b2v_latch_bc_hi.db=8'hcf;
#2 release dut.reg_file_.b2v_latch_bc_lo.we;
release dut.reg_file_.b2v_latch_bc_hi.we;
release dut.reg_file_.b2v_latch_bc_lo.db;
release dut.reg_file_.b2v_latch_bc_hi.db;
// Preset de
force dut.reg_file_.b2v_latch_de_lo.we=1;
force dut.reg_file_.b2v_latch_de_hi.we=1;
force dut.reg_file_.b2v_latch_de_lo.db=8'hd8;
force dut.reg_file_.b2v_latch_de_hi.db=8'h90;
#2 release dut.reg_file_.b2v_latch_de_lo.we;
release dut.reg_file_.b2v_latch_de_hi.we;
release dut.reg_file_.b2v_latch_de_lo.db;
release dut.reg_file_.b2v_latch_de_hi.db;
// Preset hl
force dut.reg_file_.b2v_latch_hl_lo.we=1;
force dut.reg_file_.b2v_latch_hl_hi.we=1;
force dut.reg_file_.b2v_latch_hl_lo.db=8'h69;
force dut.reg_file_.b2v_latch_hl_hi.db=8'ha1;
#2 release dut.reg_file_.b2v_latch_hl_lo.we;
release dut.reg_file_.b2v_latch_hl_hi.we;
release dut.reg_file_.b2v_latch_hl_lo.db;
release dut.reg_file_.b2v_latch_hl_hi.db;
// Preset af2
force dut.reg_file_.b2v_latch_af2_lo.we=1;
force dut.reg_file_.b2v_latch_af2_hi.we=1;
force dut.reg_file_.b2v_latch_af2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_af2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_af2_lo.we;
release dut.reg_file_.b2v_latch_af2_hi.we;
release dut.reg_file_.b2v_latch_af2_lo.db;
release dut.reg_file_.b2v_latch_af2_hi.db;
// Preset bc2
force dut.reg_file_.b2v_latch_bc2_lo.we=1;
force dut.reg_file_.b2v_latch_bc2_hi.we=1;
force dut.reg_file_.b2v_latch_bc2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_bc2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_bc2_lo.we;
release dut.reg_file_.b2v_latch_bc2_hi.we;
release dut.reg_file_.b2v_latch_bc2_lo.db;
release dut.reg_file_.b2v_latch_bc2_hi.db;
// Preset de2
force dut.reg_file_.b2v_latch_de2_lo.we=1;
force dut.reg_file_.b2v_latch_de2_hi.we=1;
force dut.reg_file_.b2v_latch_de2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_de2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_de2_lo.we;
release dut.reg_file_.b2v_latch_de2_hi.we;
release dut.reg_file_.b2v_latch_de2_lo.db;
release dut.reg_file_.b2v_latch_de2_hi.db;
// Preset hl2
force dut.reg_file_.b2v_latch_hl2_lo.we=1;
force dut.reg_file_.b2v_latch_hl2_hi.we=1;
force dut.reg_file_.b2v_latch_hl2_lo.db=8'h00;
force dut.reg_file_.b2v_latch_hl2_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_hl2_lo.we;
release dut.reg_file_.b2v_latch_hl2_hi.we;
release dut.reg_file_.b2v_latch_hl2_lo.db;
release dut.reg_file_.b2v_latch_hl2_hi.db;
// Preset ix
force dut.reg_file_.b2v_latch_ix_lo.we=1;
force dut.reg_file_.b2v_latch_ix_hi.we=1;
force dut.reg_file_.b2v_latch_ix_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ix_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ix_lo.we;
release dut.reg_file_.b2v_latch_ix_hi.we;
release dut.reg_file_.b2v_latch_ix_lo.db;
release dut.reg_file_.b2v_latch_ix_hi.db;
// Preset iy
force dut.reg_file_.b2v_latch_iy_lo.we=1;
force dut.reg_file_.b2v_latch_iy_hi.we=1;
force dut.reg_file_.b2v_latch_iy_lo.db=8'h00;
force dut.reg_file_.b2v_latch_iy_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_iy_lo.we;
release dut.reg_file_.b2v_latch_iy_hi.we;
release dut.reg_file_.b2v_latch_iy_lo.db;
release dut.reg_file_.b2v_latch_iy_hi.db;
// Preset sp
force dut.reg_file_.b2v_latch_sp_lo.we=1;
force dut.reg_file_.b2v_latch_sp_hi.we=1;
force dut.reg_file_.b2v_latch_sp_lo.db=8'h00;
force dut.reg_file_.b2v_latch_sp_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_sp_lo.we;
release dut.reg_file_.b2v_latch_sp_hi.we;
release dut.reg_file_.b2v_latch_sp_lo.db;
release dut.reg_file_.b2v_latch_sp_hi.db;
// Preset wz
force dut.reg_file_.b2v_latch_wz_lo.we=1;
force dut.reg_file_.b2v_latch_wz_hi.we=1;
force dut.reg_file_.b2v_latch_wz_lo.db=8'h00;
force dut.reg_file_.b2v_latch_wz_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_wz_lo.we;
release dut.reg_file_.b2v_latch_wz_hi.we;
release dut.reg_file_.b2v_latch_wz_lo.db;
release dut.reg_file_.b2v_latch_wz_hi.db;
// Preset pc
force dut.reg_file_.b2v_latch_pc_lo.we=1;
force dut.reg_file_.b2v_latch_pc_hi.we=1;
force dut.reg_file_.b2v_latch_pc_lo.db=8'h00;
force dut.reg_file_.b2v_latch_pc_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_pc_lo.we;
release dut.reg_file_.b2v_latch_pc_hi.we;
release dut.reg_file_.b2v_latch_pc_lo.db;
release dut.reg_file_.b2v_latch_pc_hi.db;
// Preset ir
force dut.reg_file_.b2v_latch_ir_lo.we=1;
force dut.reg_file_.b2v_latch_ir_hi.we=1;
force dut.reg_file_.b2v_latch_ir_lo.db=8'h00;
force dut.reg_file_.b2v_latch_ir_hi.db=8'h00;
#2 release dut.reg_file_.b2v_latch_ir_lo.we;
release dut.reg_file_.b2v_latch_ir_hi.we;
release dut.reg_file_.b2v_latch_ir_lo.db;
release dut.reg_file_.b2v_latch_ir_hi.db;
// Preset memory
ram.Mem[0] = 8'h43;
// Preset memory
ram.Mem[41321] = 8'h50;
force dut.z80_top_ifc_n.fpga_reset=0;
force dut.address_latch_.abus=16'h0000;
release dut.reg_control_.ctl_reg_sys_we;
release dut.reg_file_.reg_gp_we;
#3
release dut.address_latch_.abus;
#1
#6 // Execute
force dut.reg_control_.ctl_reg_sys_we=0;
#2 pc=z.A;
#2