URL
https://opencores.org/ocsvn/a-z80/a-z80/trunk
Subversion Repositories a-z80
Compare Revisions
- This comparison shows the changes necessary to convert path
/a-z80/trunk/cpu/registers/simulation/modelsim
- from Rev 3 to Rev 8
- ↔ Reverse comparison
Rev 3 → Rev 8
/test_registers.mpf
2,9 → 2,9
; |
; All Rights Reserved. |
; |
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF |
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF |
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. |
; |
; |
|
[Library] |
std = $MODEL_TECH/../std |
129,7 → 129,7
|
work = work |
[vcom] |
; VHDL93 variable selects language version as the default. |
; VHDL93 variable selects language version as the default. |
; Default is VHDL-2002. |
; Value of 0 or 1987 for VHDL-1987. |
; Value of 1 or 1993 for VHDL-1993. |
251,7 → 251,7
UserTimeUnit = default |
|
; Default run length |
RunLength = 0 ns |
RunLength = 100 ns |
|
; Maximum iterations that can be run without advancing simulation time |
IterationLimit = 5000 |
272,7 → 272,7
BreakOnAssertion = 4 |
|
; Assertion Message Format |
; %S - Severity Level |
; %S - Severity Level |
; %R - Report Message |
; %T - Time of assertion |
; %D - Delta |
424,10 → 424,10
; description of a message. |
|
; Control transcripting of elaboration/runtime messages. |
; The default is to have messages appear in the transcript and |
; The default is to have messages appear in the transcript and |
; recorded in the wlf file (messages that are recorded in the |
; wlf file can be viewed in the MsgViewer). The other settings |
; are to send messages only to the transcript or only to the |
; are to send messages only to the transcript or only to the |
; wlf file. The valid values are |
; both {default} |
; tran {transcript only} |
469,42 → 469,42
ForceSoftPaths = 1 |
ProjectStatusDelay = 5000 |
VERILOG_DoubleClick = Edit |
VERILOG_CustomDoubleClick = |
VERILOG_CustomDoubleClick = |
SYSTEMVERILOG_DoubleClick = Edit |
SYSTEMVERILOG_CustomDoubleClick = |
SYSTEMVERILOG_CustomDoubleClick = |
VHDL_DoubleClick = Edit |
VHDL_CustomDoubleClick = |
VHDL_CustomDoubleClick = |
PSL_DoubleClick = Edit |
PSL_CustomDoubleClick = |
PSL_CustomDoubleClick = |
TEXT_DoubleClick = Edit |
TEXT_CustomDoubleClick = |
TEXT_CustomDoubleClick = |
SYSTEMC_DoubleClick = Edit |
SYSTEMC_CustomDoubleClick = |
SYSTEMC_CustomDoubleClick = |
TCL_DoubleClick = Edit |
TCL_CustomDoubleClick = |
TCL_CustomDoubleClick = |
MACRO_DoubleClick = Edit |
MACRO_CustomDoubleClick = |
MACRO_CustomDoubleClick = |
VCD_DoubleClick = Edit |
VCD_CustomDoubleClick = |
VCD_CustomDoubleClick = |
SDF_DoubleClick = Edit |
SDF_CustomDoubleClick = |
SDF_CustomDoubleClick = |
XML_DoubleClick = Edit |
XML_CustomDoubleClick = |
XML_CustomDoubleClick = |
LOGFILE_DoubleClick = Edit |
LOGFILE_CustomDoubleClick = |
LOGFILE_CustomDoubleClick = |
UCDB_DoubleClick = Edit |
UCDB_CustomDoubleClick = |
UCDB_CustomDoubleClick = |
UPF_DoubleClick = Edit |
UPF_CustomDoubleClick = |
UPF_CustomDoubleClick = |
PCF_DoubleClick = Edit |
PCF_CustomDoubleClick = |
PCF_CustomDoubleClick = |
PROJECT_DoubleClick = Edit |
PROJECT_CustomDoubleClick = |
PROJECT_CustomDoubleClick = |
VRM_DoubleClick = Edit |
VRM_CustomDoubleClick = |
VRM_CustomDoubleClick = |
DEBUGDATABASE_DoubleClick = Edit |
DEBUGDATABASE_CustomDoubleClick = |
DEBUGDATABASE_CustomDoubleClick = |
DEBUGARCHIVE_DoubleClick = Edit |
DEBUGARCHIVE_CustomDoubleClick = |
DEBUGARCHIVE_CustomDoubleClick = |
Project_Major_Version = 10 |
Project_Minor_Version = 1 |
/wave_registers.do
12,6 → 12,8
add wave -noupdate -divider Control |
add wave -noupdate -itemcolor Violet /test_registers/ctl_sw_4u_sig |
add wave -noupdate -itemcolor Violet /test_registers/ctl_sw_4d_sig |
add wave -noupdate -itemcolor Violet /test_registers/reg_file_inst/reg_sw_4d_lo |
add wave -noupdate -itemcolor Violet /test_registers/reg_file_inst/reg_sw_4d_hi |
add wave -noupdate /test_registers/ctl_reg_in_hi_sig |
add wave -noupdate /test_registers/ctl_reg_in_lo_sig |
add wave -noupdate /test_registers/ctl_reg_out_hi_sig |
41,10 → 43,10
add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_sys_hi_sig |
add wave -noupdate -color Coral -itemcolor Gold /test_registers/reg_sel_sys_lo_sig |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {1300 ns} 0} |
WaveRestoreCursors {{Cursor 1} {1200 ns} 0} |
quietly wave cursor active 1 |
configure wave -namecolwidth 236 |
configure wave -valuecolwidth 67 |
configure wave -namecolwidth 260 |
configure wave -valuecolwidth 39 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 0 |
configure wave -snapdistance 10 |