OpenCores
URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /a-z80/trunk/cpu/registers
    from Rev 8 to Rev 13
    ↔ Reverse comparison
  •

Rev 8 → Rev 13

/reg_control.bdf
340,6 → 340,22
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(line (pt 42 24)(pt 64 24))
)
(drawing
2232,7 → 2048,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
2257,7 → 2073,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
2289,7 → 2105,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
)
(drawing
2322,7 → 2138,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 48 24)(pt 64 24))
)
(drawing
2348,7 → 2164,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
2380,7 → 2196,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 42 24)(pt 64 24))
)
(drawing
2405,7 → 2221,7
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
2444,7 → 2260,7
(pt 64 24)
(output)
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 65 27)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 48 15 62 27)(font "Courier New" (bold))(invisible))
(line (pt 43 24)(pt 64 24))
)
(drawing
2454,6 → 2270,259
(arc (pt 31 36)(pt 31 12)(rect 19 12 44 37))
)
)
(symbol
(rect 680 800 744 880)
(text "TFFE" (rect 1 0 24 10)(font "Arial" (font_size 6)))
(text "inst20" (rect 3 68 32 80)(font "Arial" ))
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 24)
(input)
(text "T" (rect 14 20 19 32)(font "Courier New" (bold)))
(text "T" (rect 14 20 19 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 56)
(input)
(text "ENA" (rect 14 49 31 61)(font "Courier New" (bold)))
(text "ENA" (rect 14 49 31 61)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
)
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 3)(pt 32 0))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 47 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
(line (pt 12 68)(pt 52 68))
(line (pt 12 12)(pt 52 12))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 68 36 76))
(circle (rect 28 4 36 12))
)
)
(symbol
(rect 680 376 744 456)
(text "TFFE" (rect 1 0 24 10)(font "Arial" (font_size 6)))
(text "inst30" (rect 3 68 32 80)(font "Arial" ))
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 24)
(input)
(text "T" (rect 14 20 19 32)(font "Courier New" (bold)))
(text "T" (rect 14 20 19 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 56)
(input)
(text "ENA" (rect 14 49 31 61)(font "Courier New" (bold)))
(text "ENA" (rect 14 49 31 61)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
)
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 3)(pt 32 0))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 47 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
(line (pt 12 68)(pt 52 68))
(line (pt 12 12)(pt 52 12))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 68 36 76))
(circle (rect 28 4 36 12))
)
)
(symbol
(rect 680 488 744 568)
(text "TFFE" (rect 1 0 24 10)(font "Arial" (font_size 6)))
(text "inst34" (rect 3 68 32 80)(font "Arial" ))
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 24)
(input)
(text "T" (rect 14 20 19 32)(font "Courier New" (bold)))
(text "T" (rect 14 20 19 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 56)
(input)
(text "ENA" (rect 14 49 31 61)(font "Courier New" (bold)))
(text "ENA" (rect 14 49 31 61)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
)
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 3)(pt 32 0))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 47 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
(line (pt 12 68)(pt 52 68))
(line (pt 12 12)(pt 52 12))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 68 36 76))
(circle (rect 28 4 36 12))
)
)
(symbol
(rect 336 440 400 520)
(text "TFFE" (rect 1 0 24 10)(font "Arial" (font_size 6)))
(text "inst35" (rect 3 68 32 80)(font "Arial" ))
(port
(pt 32 80)
(input)
(text "CLRN" (rect 21 59 44 71)(font "Courier New" (bold)))
(text "CLRN" (rect 21 58 44 70)(font "Courier New" (bold)))
(line (pt 32 80)(pt 32 76))
)
(port
(pt 0 24)
(input)
(text "T" (rect 14 20 19 32)(font "Courier New" (bold)))
(text "T" (rect 14 20 19 32)(font "Courier New" (bold)))
(line (pt 0 24)(pt 12 24))
)
(port
(pt 0 40)
(input)
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(text "CLK" (rect 2 28 19 40)(font "Courier New" (bold))(invisible))
(line (pt 0 40)(pt 12 40))
)
(port
(pt 0 56)
(input)
(text "ENA" (rect 14 49 31 61)(font "Courier New" (bold)))
(text "ENA" (rect 14 49 31 61)(font "Courier New" (bold)))
(line (pt 0 56)(pt 12 56))
)
(port
(pt 32 0)
(input)
(text "PRN" (rect 24 13 41 25)(font "Courier New" (bold)))
(text "PRN" (rect 24 11 41 23)(font "Courier New" (bold)))
(line (pt 32 3)(pt 32 0))
)
(port
(pt 64 24)
(output)
(text "Q" (rect 45 20 50 32)(font "Courier New" (bold)))
(text "Q" (rect 43 20 47 32)(font "Courier New" (bold)))
(line (pt 52 24)(pt 64 24))
)
(drawing
(line (pt 12 68)(pt 52 68))
(line (pt 12 12)(pt 52 12))
(line (pt 52 68)(pt 52 12))
(line (pt 12 68)(pt 12 12))
(line (pt 12 34)(pt 19 41))
(line (pt 18 41)(pt 12 47))
(circle (rect 28 68 36 76))
(circle (rect 28 4 36 12))
)
)
(symbol
(rect 328 840 376 872)
(text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6)))
(text "inst7" (rect 3 21 26 33)(font "Arial" ))
(port
(pt 0 16)
(input)
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible))
(line (pt 0 16)(pt 13 16))
)
(port
(pt 48 16)
(output)
(text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible))
(text "OUT" (rect 32 7 46 19)(font "Courier New" (bold))(invisible))
(line (pt 39 16)(pt 48 16))
)
(drawing
(line (pt 13 25)(pt 13 7))
(line (pt 13 7)(pt 31 16))
(line (pt 13 25)(pt 31 16))
(circle (rect 31 12 39 20))
)
)
(connector
(pt 616 680)
(pt 600 680)
3501,6 → 3570,45
(pt 400 1344)
(pt 552 1344)
)
(connector
(pt 336 496)
(pt 312 496)
)
(connector
(pt 208 856)
(pt 328 856)
)
(connector
(pt 312 496)
(pt 312 800)
)
(connector
(pt 312 800)
(pt 528 800)
)
(connector
(pt 528 800)
(pt 528 856)
)
(connector
(pt 528 856)
(pt 680 856)
)
(connector
(text "n_hold_clk_wait" (rect 400 840 476 852)(font "Arial" ))
(pt 376 856)
(pt 528 856)
)
(connector
(text "n_hold_clk_wait" (rect 607 544 683 556)(font "Arial" ))
(pt 680 544)
(pt 656 544)
)
(connector
(text "n_hold_clk_wait" (rect 608 432 684 444)(font "Arial" ))
(pt 680 432)
(pt 656 432)
)
(junction (pt 600 624))
(junction (pt 264 312))
(junction (pt 264 632))
3555,6 → 3663,7
(junction (pt 400 1312))
(junction (pt 640 1240))
(junction (pt 640 1408))
(junction (pt 528 856))
(text "BC" (rect 440 120 456 134)(font "Arial" (font_size 8)))
(text "2'b00" (rect 328 120 358 134)(font "Arial" (font_size 8)))
(text "2'b01" (rect 328 280 358 294)(font "Arial" (font_size 8)))
3581,7 → 3690,7
(section (rect 130 0 320 20)(text "MODULE" (rect 2 1 48 13)(font "Arial" ))(text "reg_control" (rect 43 2 146 21)(font "Arial" (font_size 12)(bold)))(border))
(section (rect 0 21 320 40)(text "DESIGNER" (rect 2 0 59 12)(font "Arial" ))(text "Goran Devic" (rect 56 2 151 19)(font "Arial" (font_size 11)))(border))
(section (rect 0 41 240 60)(text "DATE" (rect 2 0 30 12)(font "Arial" ))(text "May 17, 2014, 2016" (rect 56 3 191 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.3" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(section (rect 241 41 320 60)(text "REV" (rect 2 1 25 13)(font "Arial" ))(text "1.4" (rect 43 3 64 19)(font "Arial" (font_size 10)))(border))
(drawing
)
)
/reg_control.bsf
96,74 → 96,81
(port
(pt 0 192)
(input)
(text "ctl_reg_use_sp" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "ctl_reg_use_sp" (rect 21 187 109 201)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "hold_clk_wait" (rect 21 187 98 201)(font "Arial" (font_size 8)))
(line (pt 0 192)(pt 16 192))
)
(port
(pt 0 208)
(input)
(text "ctl_reg_sys_we_hi" (rect 0 0 109 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we_hi" (rect 21 203 130 217)(font "Arial" (font_size 8)))
(text "ctl_reg_use_sp" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "ctl_reg_use_sp" (rect 21 203 109 217)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208))
)
(port
(pt 0 224)
(input)
(text "ctl_reg_sys_we" (rect 0 0 93 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we" (rect 21 219 114 233)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we_hi" (rect 0 0 109 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we_hi" (rect 21 219 130 233)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224))
)
(port
(pt 0 240)
(input)
(text "ctl_reg_sys_we_lo" (rect 0 0 109 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we_lo" (rect 21 235 130 249)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we" (rect 0 0 93 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we" (rect 21 235 114 249)(font "Arial" (font_size 8)))
(line (pt 0 240)(pt 16 240))
)
(port
(pt 0 256)
(input)
(text "ctl_reg_sys_hilo[1..0]" (rect 0 0 121 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_hilo[1..0]" (rect 21 251 142 265)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 16 256)(line_width 3))
(text "ctl_reg_sys_we_lo" (rect 0 0 109 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_we_lo" (rect 21 251 130 265)(font "Arial" (font_size 8)))
(line (pt 0 256)(pt 16 256))
)
(port
(pt 0 272)
(input)
(text "ctl_sw_4d" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "ctl_sw_4d" (rect 21 267 81 281)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 16 272))
(text "ctl_reg_sys_hilo[1..0]" (rect 0 0 121 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sys_hilo[1..0]" (rect 21 267 142 281)(font "Arial" (font_size 8)))
(line (pt 0 272)(pt 16 272)(line_width 3))
)
(port
(pt 0 288)
(input)
(text "ctl_reg_sel_ir" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_ir" (rect 21 283 97 297)(font "Arial" (font_size 8)))
(text "ctl_sw_4d" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "ctl_sw_4d" (rect 21 283 81 297)(font "Arial" (font_size 8)))
(line (pt 0 288)(pt 16 288))
)
(port
(pt 0 304)
(input)
(text "ctl_reg_sel_pc" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_pc" (rect 21 299 104 313)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_ir" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_ir" (rect 21 299 97 313)(font "Arial" (font_size 8)))
(line (pt 0 304)(pt 16 304))
)
(port
(pt 0 320)
(input)
(text "ctl_reg_not_pc" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "ctl_reg_not_pc" (rect 21 315 105 329)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_pc" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_pc" (rect 21 315 104 329)(font "Arial" (font_size 8)))
(line (pt 0 320)(pt 16 320))
)
(port
(pt 0 336)
(input)
(text "ctl_reg_sel_wz" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_wz" (rect 21 331 109 345)(font "Arial" (font_size 8)))
(text "ctl_reg_not_pc" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "ctl_reg_not_pc" (rect 21 331 105 345)(font "Arial" (font_size 8)))
(line (pt 0 336)(pt 16 336))
)
(port
(pt 0 352)
(input)
(text "ctl_reg_sel_wz" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "ctl_reg_sel_wz" (rect 21 347 109 361)(font "Arial" (font_size 8)))
(line (pt 0 352)(pt 16 352))
)
(port
(pt 264 32)
(output)
(text "reg_gp_we" (rect 0 0 66 14)(font "Arial" (font_size 8)))
/reg_control.v
14,7 → 14,7
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Tue Mar 08 20:46:27 2016"
// CREATED "Thu Dec 08 22:19:25 2016"
 
module reg_control(
ctl_reg_exx,
34,6 → 34,7
ctl_reg_sys_we,
clk,
ctl_sw_4d,
hold_clk_wait,
ctl_reg_gp_hilo,
ctl_reg_gp_sel,
ctl_reg_sys_hilo,
80,6 → 81,7
input wire ctl_reg_sys_we;
input wire clk;
input wire ctl_sw_4d;
input wire hold_clk_wait;
input wire [1:0] ctl_reg_gp_hilo;
input wire [1:0] ctl_reg_gp_sel;
input wire [1:0] ctl_reg_sys_hilo;
111,6 → 113,7
reg bank_exx;
reg bank_hl_de1;
reg bank_hl_de2;
wire n_hold_clk_wait;
wire reg_sys_we_lo_ALTERA_SYNTHESIZED;
wire SYNTHESIZED_WIRE_52;
wire SYNTHESIZED_WIRE_53;
172,7 → 175,7
 
assign reg_sel_ix = SYNTHESIZED_WIRE_56 & use_ix;
 
assign SYNTHESIZED_WIRE_37 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
assign SYNTHESIZED_WIRE_50 = ctl_reg_ex_de_hl & SYNTHESIZED_WIRE_53;
 
assign reg_sel_iy = SYNTHESIZED_WIRE_56 & SYNTHESIZED_WIRE_10;
 
180,15 → 183,15
 
assign SYNTHESIZED_WIRE_2 = ~bank_af;
 
assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_47 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_58;
 
assign SYNTHESIZED_WIRE_47 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_46 = bank_hl_de2 & SYNTHESIZED_WIRE_59;
 
assign SYNTHESIZED_WIRE_41 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_58;
 
assign SYNTHESIZED_WIRE_50 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_49 = bank_hl_de2 & SYNTHESIZED_WIRE_58;
 
assign SYNTHESIZED_WIRE_49 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_48 = SYNTHESIZED_WIRE_57 & SYNTHESIZED_WIRE_59;
 
assign reg_sel_de = SYNTHESIZED_WIRE_53 & SYNTHESIZED_WIRE_21;
 
198,13 → 201,13
 
assign reg_sel_hl2 = bank_exx & SYNTHESIZED_WIRE_25;
 
assign SYNTHESIZED_WIRE_40 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_38 = bank_hl_de1 & SYNTHESIZED_WIRE_59;
 
assign SYNTHESIZED_WIRE_53 = ~bank_exx;
 
assign SYNTHESIZED_WIRE_46 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
assign SYNTHESIZED_WIRE_45 = bank_hl_de1 & SYNTHESIZED_WIRE_58;
 
assign SYNTHESIZED_WIRE_45 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
assign SYNTHESIZED_WIRE_44 = SYNTHESIZED_WIRE_60 & SYNTHESIZED_WIRE_59;
 
assign SYNTHESIZED_WIRE_52 = SYNTHESIZED_WIRE_30 & SYNTHESIZED_WIRE_31;
 
224,34 → 227,45
 
assign SYNTHESIZED_WIRE_56 = SYNTHESIZED_WIRE_61 & use_ixiy;
 
assign SYNTHESIZED_WIRE_44 = ~ctl_reg_gp_sel[0];
assign SYNTHESIZED_WIRE_42 = ~ctl_reg_gp_sel[0];
 
assign SYNTHESIZED_WIRE_39 = ctl_reg_ex_de_hl & bank_exx;
assign SYNTHESIZED_WIRE_43 = ctl_reg_ex_de_hl & bank_exx;
 
assign SYNTHESIZED_WIRE_34 = ~use_ixiy;
 
assign SYNTHESIZED_WIRE_59 = ctl_reg_gp_sel[0] & SYNTHESIZED_WIRE_36;
 
assign SYNTHESIZED_WIRE_10 = ~use_ix;
 
assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;
 
assign SYNTHESIZED_WIRE_43 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_hl_de1 <= 0;
bank_af <= 0;
end
else
bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_37;
if (n_hold_clk_wait)
begin
bank_af <= bank_af ^ ctl_reg_ex_af;
end
end
 
assign SYNTHESIZED_WIRE_42 = ~SYNTHESIZED_WIRE_38;
assign SYNTHESIZED_WIRE_10 = ~use_ix;
 
assign SYNTHESIZED_WIRE_57 = ~bank_hl_de2;
 
assign SYNTHESIZED_WIRE_41 = ~reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
assign SYNTHESIZED_WIRE_40 = ~SYNTHESIZED_WIRE_37;
 
assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_38 | SYNTHESIZED_WIRE_39;
 
assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_40;
 
assign SYNTHESIZED_WIRE_37 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_41 & ctl_reg_sel_ir;
 
assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_42 & ctl_reg_gp_sel[1];
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
259,53 → 273,56
bank_hl_de2 <= 0;
end
else
bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_39;
if (n_hold_clk_wait)
begin
bank_hl_de2 <= bank_hl_de2 ^ SYNTHESIZED_WIRE_43;
end
end
 
assign SYNTHESIZED_WIRE_23 = SYNTHESIZED_WIRE_40 | SYNTHESIZED_WIRE_41;
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_44 | SYNTHESIZED_WIRE_45;
 
assign reg_sw_4d_hi = ctl_sw_4d & SYNTHESIZED_WIRE_42;
assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_46 | SYNTHESIZED_WIRE_47;
 
assign SYNTHESIZED_WIRE_38 = ctl_reg_sys_hilo[1] & SYNTHESIZED_WIRE_43 & ctl_reg_sel_ir;
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_48 | SYNTHESIZED_WIRE_49;
 
assign SYNTHESIZED_WIRE_61 = SYNTHESIZED_WIRE_44 & ctl_reg_gp_sel[1];
 
assign SYNTHESIZED_WIRE_21 = SYNTHESIZED_WIRE_45 | SYNTHESIZED_WIRE_46;
 
assign SYNTHESIZED_WIRE_25 = SYNTHESIZED_WIRE_47 | SYNTHESIZED_WIRE_48;
 
assign SYNTHESIZED_WIRE_24 = SYNTHESIZED_WIRE_49 | SYNTHESIZED_WIRE_50;
 
assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
 
assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];
 
assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_exx <= 0;
bank_hl_de1 <= 0;
end
else
bank_exx <= bank_exx ^ ctl_reg_exx;
if (n_hold_clk_wait)
begin
bank_hl_de1 <= bank_hl_de1 ^ SYNTHESIZED_WIRE_50;
end
end
 
assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
 
 
always@(posedge clk or negedge nreset)
begin
if (!nreset)
begin
bank_af <= 0;
bank_exx <= 0;
end
else
bank_af <= bank_af ^ ctl_reg_ex_af;
if (n_hold_clk_wait)
begin
bank_exx <= bank_exx ^ ctl_reg_exx;
end
end
 
assign SYNTHESIZED_WIRE_55 = ctl_reg_gp_sel[0] & ctl_reg_gp_sel[1];
 
assign SYNTHESIZED_WIRE_30 = ~ctl_reg_gp_sel[0];
 
assign SYNTHESIZED_WIRE_31 = ~ctl_reg_gp_sel[1];
 
assign n_hold_clk_wait = ~hold_clk_wait;
 
assign reg_sel_bc2 = SYNTHESIZED_WIRE_52 & bank_exx;
 
assign reg_sys_we_lo = reg_sys_we_lo_ALTERA_SYNTHESIZED;
 
endmodule
/test_registers.sv
49,6 → 49,7
logic ctl_reg_sys_we_sig=0; // Write to system register
logic use_ixiy_sig=0; // Use IX or IY
logic use_ix_sig=0; // Use IX and not IY
logic hold_clk_wait_sig=0; // Hold all transitions
 
logic ctl_reg_exx_sig=0; // Exchange register banks
logic ctl_reg_ex_af_sig=0; // Exchange AF banks
182,6 → 183,7
.ctl_reg_sys_we(ctl_reg_sys_we_sig) , // input ctl_reg_sys_we_sig
.clk(clk) , // input clk
.ctl_sw_4d (ctl_sw_4d_sig) , // input ctl_sw_4d
.hold_clk_wait(hold_clk_wait_sig) , // input hold_clk_wait_sig
.reg_sel_bc(reg_sel_bc_sig) , // output reg_sel_bc_sig
.reg_sel_bc2(reg_sel_bc2_sig) , // output reg_sel_bc2_sig
.reg_sel_ix(reg_sel_ix_sig) , // output reg_sel_ix_sig

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