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Rev 8 → Rev 13

/wait_state.bdf
0,0 → 1,492
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "Memory Speed Control, Zilog Manual" (rect 72 40 324 56)(font "Arial" (font_size 10))(border))
(text "Adding One Wait State to an M1 Cycle" (rect 536 168 802 184)(font "Arial" (font_size 10)))
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(line (pt 64 272)(pt 784 272)(color 0 255 0))
/wait_state.bsf
0,0 → 1,64
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 16 16 184 112)
(text "wait_state" (rect 5 0 65 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "nM1" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "nM1" (rect 21 27 44 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32))
)
(port
(pt 0 48)
(input)
(text "CLK" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "CLK" (rect 21 43 44 57)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48))
)
(port
(pt 0 64)
(input)
(text "nMREQ" (rect 0 0 41 14)(font "Arial" (font_size 8)))
(text "nMREQ" (rect 21 59 62 73)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64))
)
(port
(pt 168 32)
(output)
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(line (pt 168 32)(pt 152 32))
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(port
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(line (pt 168 48)(pt 152 48))
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(drawing
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/wait_state.v
0,0 → 1,86
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
 
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED "Thu Dec 08 00:16:50 2016"
 
module wait_state(
CLK,
nM1,
nMREQ,
nWAIT_M1,
nWAIT_Mem
);
 
 
input wire CLK;
input wire nM1;
input wire nMREQ;
output wire nWAIT_M1;
output wire nWAIT_Mem;
 
reg SYNTHESIZED_WIRE_1;
reg DFF_inst3;
reg DFF_inst2;
reg DFF_inst5;
wire SYNTHESIZED_WIRE_0;
 
assign nWAIT_M1 = DFF_inst2;
 
 
 
assign SYNTHESIZED_WIRE_0 = ~SYNTHESIZED_WIRE_1;
 
 
always@(posedge CLK or negedge DFF_inst3)
begin
if (!DFF_inst3)
begin
DFF_inst2 <= 1;
end
else
begin
DFF_inst2 <= nM1;
end
end
 
 
always@(posedge CLK)
begin
begin
DFF_inst3 <= DFF_inst2;
end
end
 
 
always@(posedge CLK)
begin
begin
SYNTHESIZED_WIRE_1 <= nMREQ;
end
end
 
 
always@(posedge CLK)
begin
begin
DFF_inst5 <= SYNTHESIZED_WIRE_1;
end
end
 
assign nWAIT_Mem = ~(DFF_inst5 & SYNTHESIZED_WIRE_0);
 
 
endmodule

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