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/aes-128_pipelined_encryption/trunk/rtl/ShiftRows.v File deleted \ No newline at end of file
/aes-128_pipelined_encryption/trunk/rtl/RoundKeyGen.v File deleted \ No newline at end of file
/aes-128_pipelined_encryption/trunk/rtl/MixColumns.v File deleted \ No newline at end of file
/aes-128_pipelined_encryption/trunk/rtl/KeyExpantion.v File deleted \ No newline at end of file
/aes-128_pipelined_encryption/trunk/doc/AES_Pipelined_Cipher.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
aes-128_pipelined_encryption/trunk/doc/AES_Pipelined_Cipher.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: aes-128_pipelined_encryption/trunk/doc/release_notes.txt =================================================================== --- aes-128_pipelined_encryption/trunk/doc/release_notes.txt (revision 2) +++ aes-128_pipelined_encryption/trunk/doc/release_notes.txt (nonexistent) @@ -1,30 +0,0 @@ -DESIGN : 128 bit AES Pipelined Cipher - -RELEASE DATE: 07-07-2013 - -REVISION 0.0 - -FEATURES : - --One clock domain --Asynchronous reset --128 bit data --128 bit Cipher Key --Optimized for speed --Pipelined architecture - -BlOCKS STATUS: - -Top_PipelinedCipher completed - Functionally Verified -KeyExpantion completed - Functionally Verified -RoundKeyGen completed - Functionally Verified -Round completed - Functionally Verified -SubBytes completed - Functionally Verified -SBox completed - Functionally Verified -ShiftRows completed - Functionally Verified -MixColumns completed - Functionally Verified -AddRoundKey completed - Functionally Verified - -WHOLE DESIGN : completed - Functionally Verified using AESVS document test vectors (284 vector) - Synthesis , Place and Route on Xilinx virtex 6 6vcx240tff784-2 - Post Place and Route Simulation Verified \ No newline at end of file Index: aes-128_pipelined_encryption/trunk/sim/topcipher_test_outputs.txt =================================================================== --- aes-128_pipelined_encryption/trunk/sim/topcipher_test_outputs.txt (revision 2) +++ aes-128_pipelined_encryption/trunk/sim/topcipher_test_outputs.txt (nonexistent) @@ -1,284 +0,0 @@ -0336763e966d92595a567cc9ce537f5e -a9a1631bf4996954ebc093957b234589 -ff4f8391a6a40ca5b25d23bedd44a597 -dc43be40be0e53712f7e2bf5ca707209 -92beedab1895a94faa69b632e5cc47ce -459264f4798f6a78bacb89c15ed3d601 -08a4e2efec8a8e3312ca7460b9040bbf -6d251e6944b051e04eaa6fb4dbf78465 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-Description : -Owner : Amr Salah -*/ - -`timescale 1 ns/1 ps - -module Top_PipelinedCipher_tb(); - -parameter DATA_W = 128; //data width -parameter KEY_L = 128; //key length -parameter NO_ROUNDS = 10; //number of rounds -parameter Clk2Q = 2; //Clk-Q delay -parameter No_Patterns = 284; //number of patterns - -reg clk; -reg reset; -reg data_valid_in; -reg cipherkey_valid_in; -reg [KEY_L-1:0] cipher_key; -reg [DATA_W-1:0] plain_text; -wire valid_out; -wire[DATA_W-1:0]cipher_text; -reg dut_error; -reg [DATA_W-1:0] data_expected; -reg [DATA_W-1:0] data_input_vectors [0:No_Patterns-1] ; -reg [DATA_W-1:0] cipherkey_input_vectors [0:No_Patterns-1] ; -reg [DATA_W-1:0] output_vectors [0:No_Patterns-1] ; - -integer i; - -Top_PipelinedCipher U //connecting DUT -( -.clk(clk), -.reset(reset), -.data_valid_in(data_valid_in), -.cipherkey_valid_in(cipherkey_valid_in), -.cipher_key(cipher_key), -.plain_text(plain_text), -.valid_out(valid_out), -.cipher_text(cipher_text) -); - -event terminate_sim; -event reset_enable; - -initial begin //reading input data and cipherkey vectors and expected output vectors - -$readmemh("topcipher_data_test_inputs.txt",data_input_vectors); -$readmemh("topcipher_key_test_inputs.txt",cipherkey_input_vectors); -$readmemh("topcipher_test_outputs.txt",output_vectors); - -end - -initial begin - $display ("###################################################"); - clk = 0; - reset = 1; - data_valid_in = 0; - cipherkey_valid_in = 0; - dut_error = 0; //design error counter -end - -always - #5 clk = !clk; //clock generator - -`ifndef GATES //if not gate simulation -initial begin - $dumpfile("Top_PipelinedCipher.vcd"); - $dumpvars; -end -`endif - -initial -forever @ (terminate_sim) begin //simulation termination logic - $display ("Terminating simulation"); - if (dut_error == 0) begin - $display ("Simulation Result : PASSED"); - end - else begin - $display ("Simulation Result : FAILED"); - end - $display ("###################################################"); - #1 $stop; - -end - -event reset_done; - -initial //reset logic -forever begin - @ (reset_enable); - @ (negedge clk) - $display ("Applying reset"); - reset = 0; - data_expected = 'b0; - @ (negedge clk) - reset = 1; - $display ("Came out of Reset"); - -> reset_done; -end - -initial begin - #10 -> reset_enable; - @ (reset_done); - - for (i=0;i< No_Patterns;i=i+1) begin //apply inputs - @ (posedge clk) - #Clk2Q - data_valid_in = 1; //assert valid signals - cipherkey_valid_in = 1; - plain_text = data_input_vectors[i]; - cipher_key = cipherkey_input_vectors[i]; - end - - @(posedge clk) - data_valid_in = 0; //deassert valid signals - cipherkey_valid_in = 0; - -end - -integer j; - -initial @(reset_done) begin - -repeat((4 * NO_ROUNDS)+1) begin //waiting for first output (latency) -@(posedge clk); -end - -for(j=0;j< No_Patterns;j=j+1) begin //assign expected outputs -@(posedge clk) -data_expected = output_vectors[j]; -end - -end - - -//compare logic - -always @ (posedge clk) begin -if (valid_out || (!reset)) begin - if(data_expected != cipher_text) begin - $display ("DUT ERROR AT TIME%d",$time); - $display ("Expected Data value %h, Got Data Value %h", data_expected, cipher_text); - dut_error = 1; - -> terminate_sim; //stop simulation when error occures - end -end -if(j == No_Patterns) begin //terminate simulation after the end of output vectors - -> terminate_sim; -end - end -endmodule \ No newline at end of file Index: aes-128_pipelined_encryption/trunk/sim/topcipher_key_test_inputs.txt =================================================================== --- aes-128_pipelined_encryption/trunk/sim/topcipher_key_test_inputs.txt (revision 2) +++ aes-128_pipelined_encryption/trunk/sim/topcipher_key_test_inputs.txt (nonexistent) @@ -1,284 +0,0 @@ -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 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-00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 \ No newline at end of file Index: aes-128_pipelined_encryption/trunk/sim/Top_PipelinedCipher.do =================================================================== --- aes-128_pipelined_encryption/trunk/sim/Top_PipelinedCipher.do (revision 2) +++ aes-128_pipelined_encryption/trunk/sim/Top_PipelinedCipher.do (nonexistent) @@ -1,13 +0,0 @@ -vlib work -vlog ../rtl/SBox.v -vlog ../rtl/SubBytes.v -vlog ../rtl/ShiftRows.v -vlog ../rtl/MixColumns.v -vlog ../rtl/AddRoundKey.v -vlog ../rtl/Round.v -vlog ../rtl/RoundKeyGen.v -vlog ../rtl/KeyExpantion.v -vlog ../rtl/Top_PipelinedCipher.v -vlog ../sim/Top_PipelinedCipher_tb.v -vsim -novopt Top_PipelinedCipher_tb -run -a Index: aes-128_pipelined_encryption/trunk/sim/timesim.do =================================================================== --- aes-128_pipelined_encryption/trunk/sim/timesim.do (revision 2) +++ aes-128_pipelined_encryption/trunk/sim/timesim.do (nonexistent) @@ -1,4 +0,0 @@ -vlog Top_PipelinedCipher_tb.v -vlog ../syn/netgen/par/Top_PipelinedCipher_timesim.v -vsim +define+GATES -novopt -sdfmax /U/=../syn/netgen/par/Top_PipelinedCipher_timesim.sdf -novopt work.Top_PipelinedCipher_tb glbl -run -a \ No newline at end of file Index: aes-128_pipelined_encryption/trunk/syn/readme.txt =================================================================== --- aes-128_pipelined_encryption/trunk/syn/readme.txt (revision 2) +++ aes-128_pipelined_encryption/trunk/syn/readme.txt (nonexistent) @@ -1,8 +0,0 @@ -1-edit run.tcl and replace . with your project directory (that contains tcl files) - -2-edit setup.tcl at line 218 begin to add your files as shown -3-edit setup.tcl at line 230 set your top module - -4-open xilinx bash shell and point to the directory that contains tcl files then write xtclsh -5-write the command: source run.tcl -6-after running all processes the sdf file and the verilog netlist can be found in netgen folder Index: aes-128_pipelined_encryption/trunk/syn/setup.tcl =================================================================== --- aes-128_pipelined_encryption/trunk/syn/setup.tcl (revision 2) +++ aes-128_pipelined_encryption/trunk/syn/setup.tcl (nonexistent) @@ -1,493 +0,0 @@ -# -# Project automation script for AES -# -# Created for ISE version 12.1 -# -# This file contains several Tcl procedures (procs) that you can use to automate -# your project by running from xtclsh or the Project Navigator Tcl console. -# If you load this file (using the Tcl command: source AES.tcl), then you can -# run any of the procs included here. -# -# This script is generated assuming your project has HDL sources. -# Several of the defined procs won't apply to an EDIF or NGC based project. -# If that is the case, simply remove them from this script. -# -# You may also edit any of these procs to customize them. See comments in each -# proc for more instructions. -# -# This file contains the following procedures: -# -# Top Level procs (meant to be called directly by the user): -# run_process: you can use this top-level procedure to run any processes -# that you choose to by adding and removing comments, or by -# adding new entries. -# rebuild_project: you can alternatively use this top-level procedure -# to recreate your entire project, and the run selected processes. -# -# Lower Level (helper) procs (called under in various cases by the top level procs): -# show_help: print some basic information describing how this script works -# add_source_files: adds the listed source files to your project. -# set_project_props: sets the project properties that were in effect when this -# script was generated. -# create_libraries: creates and adds file to VHDL libraries that were defined when -# this script was generated. -# set_process_props: set the process properties as they were set for your project -# when this script was generated. -# - -set myProject "AES" -set myScript "setup.tcl" - -# -# Main (top-level) routines -# - -# -# run_process -# This procedure is used to run processes on an existing project. You may comment or -# uncomment lines to control which processes are run. This routine is set up to run -# the Implement Design and Generate Programming File processes by default. This proc -# also sets process properties as specified in the "set_process_props" proc. Only -# those properties which have values different from their current settings in the project -# file will be modified in the project. -# -proc run_process {} { - - global myScript - global myProject - - ## put out a 'heartbeat' - so we know something's happening. - puts "\n$myScript: running ($myProject)...\n" - - if { ! [ open_project ] } { - return false - } - - set_process_props - # - # Remove the comment characters (#'s) to enable the following commands - process run "Synthesize" - process run "Translate" - process run "Map" - process run "Place & Route" - process run "Generate Post-Place & Route Simulation Model" - # - puts "Running 'Implement Design'" - if { ! [ process run "Implement Design" ] } { - puts "$myScript: Implementation run failed, check run output for details." - project close - return - } - puts "Running 'Generate Programming File'" - if { ! [ process run "Generate Programming File" ] } { - puts "$myScript: Generate Programming File run failed, check run output for details." - project close - return - } - - puts "Run completed." - project close - -} - -# -# rebuild_project -# -# This procedure renames the project file (if it exists) and recreates the project. -# It then sets project properties and adds project sources as specified by the -# set_project_props and add_source_files support procs. It recreates VHDL libraries -# and partitions as they existed at the time this script was generated. -# -# It then calls run_process to set process properties and run selected processes. -# -proc rebuild_project {} { - - global myScript - global myProject - - project close - ## put out a 'heartbeat' - so we know something's happening. - puts "\n$myScript: Rebuilding ($myProject)...\n" - - set proj_exts [ list ise xise gise ] - foreach ext $proj_exts { - set proj_name "${myProject}.$ext" - if { [ file exists $proj_name ] } { - file delete $proj_name - } - } - - project new $myProject - set_project_props - add_source_files - create_libraries - puts "$myScript: project rebuild completed." - - run_process - -} - -# -# Support Routines -# - -# -# show_help: print information to help users understand the options available when -# running this script. -# -proc show_help {} { - - global myScript - - puts "" - puts "usage: xtclsh $myScript " - puts " or you can run xtclsh and then enter 'source $myScript'." - puts "" - puts "options:" - puts " run_process - set properties and run processes." - puts " rebuild_project - rebuild the project from scratch and run processes." - puts " set_project_props - set project properties (device, speed, etc.)" - puts " add_source_files - add source files" - puts " create_libraries - create vhdl libraries" - puts " set_process_props - set process property values" - puts " show_help - print this message" - puts "" -} - -proc open_project {} { - - global myScript - global myProject - - if { ! [ file exists ${myProject}.xise ] } { - ## project file isn't there, rebuild it. - puts "Project $myProject not found. Use project_rebuild to recreate it." - return false - } - - project open $myProject - - return true - -} -# -# set_project_props -# -# This procedure sets the project properties as they were set in the project -# at the time this script was generated. -# -proc set_project_props {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Setting project properties..." - - project set family "Virtex6" - project set device "xc6vcx240t" - project set package "ff784" - project set speed "-2" - project set top_level_module_type "HDL" - project set synthesis_tool "XST (VHDL/Verilog)" - project set simulator "Modelsim-SE Verilog" - project set "Preferred Language" "Verilog" - project set "Enable Message Filtering" "false" - -} - - -# -# add_source_files -# -# This procedure add the source files that were known to the project at the -# time this script was generated. -# -proc add_source_files {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Adding sources to project..." - - xfile add "../rtl/AddRoundKey.v" - xfile add "../rtl/KeyExpantion.v" - xfile add "../rtl/MixColumns.v" - xfile add "../rtl/Round.v" - xfile add "../rtl/RoundKeyGen.v" - xfile add "../rtl/SBox.v" - xfile add "../rtl/ShiftRows.v" - xfile add "../rtl/SubBytes.v" - xfile add "../rtl/Top_PipelinedCipher.v" - xfile add "./Top_PipelinedCipher.ucf" - - # Set the Top Module as well... - project set top "Top_PipelinedCipher" - - puts "$myScript: project sources reloaded." - -} ; # end add_source_files - -# -# create_libraries -# -# This procedure defines VHDL libraries and associates files with those libraries. -# It is expected to be used when recreating the project. Any libraries defined -# when this script was generated are recreated by this procedure. -# -proc create_libraries {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Creating libraries..." - - - # must close the project or library definitions aren't saved. - project save - -} ; # end create_libraries - -# -# set_process_props -# -# This procedure sets properties as requested during script generation (either -# all of the properties, or only those modified from their defaults). -# -proc set_process_props {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: setting process properties..." - - project set "Compiled Library Directory" "\$XILINX//" - project set "Global Optimization" "Off" -process "Map" - project set "Use DSP Block" "Auto" -process "Synthesize - XST" - project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File" - project set "Configuration Rate" "2" -process "Generate Programming File" - project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map" - project set "Place And Route Mode" "Route Only" -process "Place & Route" - project set "Number of Clock Buffers" "32" -process "Synthesize - XST" - project set "Max Fanout" "100000" -process "Synthesize - XST" - project set "Use Clock Enable" "Auto" -process "Synthesize - XST" - project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST" - project set "Use Synchronous Set" "Auto" -process "Synthesize - XST" - project set "Enable Hardware Co-Simulation" "false" - project set "Filter Files From Compile Order" "true" - #project set "Use Custom Project File" "false" -process "Post-Map Check Syntax" - #project set "Use Custom Project File" "false" -process "Post-Place & Route Check Syntax" - #project set "Use Custom Project File" "false" -process "Post-Translate Check Syntax" - project set "Last Applied Goal" "Balanced" - project set "Last Applied Strategy" "Xilinx Default (unlocked)" - project set "Last Unlock Status" "false" - project set "Manual Compile Order" "false" - project set "Placer Effort Level" "High" -process "Map" - project set "Extra Cost Tables" "0" -process "Map" - project set "LUT Combining" "Off" -process "Map" - project set "Combinatorial Logic Optimization" "false" -process "Map" - project set "Starting Placer Cost Table (1-100)" "1" -process "Map" - project set "Power Reduction" "Off" -process "Map" - project set "Register Duplication" "Off" -process "Map" - project set "Project Generator" "ProjNav" - project set "Property Specification in Project File" "Store all values" - project set "Reduce Control Sets" "Auto" -process "Synthesize - XST" - project set "Selected Module Instance Name" "/Top_PipelinedCipher_tb" - project set "Shift Register Minimum Size" "2" -process "Synthesize - XST" - project set "Case Implementation Style" "None" -process "Synthesize - XST" - project set "Mux Extraction" "Yes" - project set "RAM Extraction" "true" -process "Synthesize - XST" - project set "ROM Extraction" "true" -process "Synthesize - XST" - project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST" - project set "Optimization Goal" "Speed" -process "Synthesize - XST" - project set "Optimization Effort" "Normal" -process "Synthesize - XST" - project set "Resource Sharing" "true" -process "Synthesize - XST" - project set "Shift Register Extraction" "true" -process "Synthesize - XST" - project set "User Browsed Strategy Files" "" - project set "VHDL Source Analysis Standard" "VHDL-93" - project set "Working Directory" "." - project set "JTAG to System Monitor Connection" "Enable" -process "Generate Programming File" - project set "Other Bitgen Command Line Options" "" -process "Generate Programming File" - project set "Generate Detailed Package Parasitics" "false" -process "Generate IBIS Model" - project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model" - project set "Show All Models" "false" -process "Generate IBIS Model" - project set "Target UCF File Name" "" -process "Back-annotate Pin Locations" - project set "Ignore User Timing Constraints" "false" -process "Map" - project set "Use RLOC Constraints" "Yes" -process "Map" - project set "Other Map Command Line Options" "" -process "Map" - project set "Use LOC Constraints" "true" -process "Translate" - project set "Other Ngdbuild Command Line Options" "" -process "Translate" - project set "Ignore User Timing Constraints" "false" -process "Place & Route" - project set "Other Place & Route Command Line Options" "" -process "Place & Route" - project set "BPI Reads Per Page" "1" -process "Generate Programming File" - project set "Configuration Pin Busy" "Pull Up" -process "Generate Programming File" - project set "Configuration Clk (Configuration Pins)" "Pull Up" -process "Generate Programming File" - project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File" - project set "Configuration Pin CS" "Pull Up" -process "Generate Programming File" - project set "DCI Update Mode" "As Required" -process "Generate Programming File" - project set "Configuration Pin DIn" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File" - project set "Create ASCII Configuration File" "false" -process "Generate Programming File" - project set "Create Binary Configuration File" "false" -process "Generate Programming File" - project set "Create Bit File" "true" -process "Generate Programming File" - project set "Enable BitStream Compression" "false" -process "Generate Programming File" - project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File" - project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File" - project set "Create ReadBack Data Files" "false" -process "Generate Programming File" - project set "Configuration Pin HSWAPEN" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin Init" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin M0" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin M1" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin M2" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File" - project set "Power Down Device if Over Safe Temperature" "false" -process "Generate Programming File" - project set "Configuration Pin RdWr" "Pull Up" -process "Generate Programming File" - project set "Starting Address for Fallback Configuration" "0x00000000" -process "Generate Programming File" - project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File" - project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File" - project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File" - project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File" - project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File" - project set "Watchdog Timer Mode" "Off" -process "Generate Programming File" - project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File" - project set "Done (Output Events)" "Default (4)" -process "Generate Programming File" - project set "Drive Done Pin High" "false" -process "Generate Programming File" - project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File" - project set "Wait for DCI Match (Output Events)" "Auto" -process "Generate Programming File" - project set "Wait for PLL Lock (Output Events)" "No Wait" -process "Generate Programming File" - project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File" - project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File" - project set "Enable Internal Done Pipe" "false" -process "Generate Programming File" - project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map" - project set "Maximum Compression" "false" -process "Map" - project set "Generate Detailed MAP Report" "false" -process "Map" - project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map" - project set "Perform Timing-Driven Packing and Placement" "false" - project set "Trim Unconnected Signals" "true" -process "Map" - project set "Create I/O Pads from Ports" "false" -process "Translate" - project set "Macro Search Path" "" -process "Translate" - project set "Netlist Translation Type" "Timestamp" -process "Translate" - project set "User Rules File for Netlister Launcher" "" -process "Translate" - project set "Allow Unexpanded Blocks" "false" -process "Translate" - project set "Allow Unmatched LOC Constraints" "false" -process "Translate" - project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate" - project set "Add I/O Buffers" "true" -process "Synthesize - XST" - project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST" - project set "Keep Hierarchy" "No" -process "Synthesize - XST" - project set "Register Balancing" "No" -process "Synthesize - XST" - project set "Register Duplication" "true" -process "Synthesize - XST" - project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST" - project set "Automatic BRAM Packing" "false" -process "Synthesize - XST" - project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST" - project set "Bus Delimiter" "<>" -process "Synthesize - XST" - project set "Case" "Maintain" -process "Synthesize - XST" - project set "Cores Search Directories" "" -process "Synthesize - XST" - project set "Cross Clock Analysis" "false" -process "Synthesize - XST" - project set "DSP Utilization Ratio" "100" -process "Synthesize - XST" - project set "Equivalent Register Removal" "true" -process "Synthesize - XST" - project set "FSM Style" "LUT" -process "Synthesize - XST" - project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST" - project set "Generics, Parameters" "" -process "Synthesize - XST" - project set "Hierarchy Separator" "/" -process "Synthesize - XST" - project set "HDL INI File" "" -process "Synthesize - XST" - project set "LUT Combining" "Auto" -process "Synthesize - XST" - project set "Library Search Order" "" -process "Synthesize - XST" - project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST" - project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST" - project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST" - project set "Power Reduction" "false" -process "Synthesize - XST" - project set "Read Cores" "true" -process "Synthesize - XST" - project set "LUT-FF Pairs Utilization Ratio" "100" -process "Synthesize - XST" - project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST" - project set "Verilog Include Directories" "" -process "Synthesize - XST" - project set "Verilog 2001" "true" - project set "Verilog Macros" "" -process "Synthesize - XST" - project set "Write Timing Constraints" "false" -process "Synthesize - XST" - project set "Other XST Command Line Options" "" -process "Synthesize - XST" - project set "Timing Mode" "Performance Evaluation" -process "Map" - project set "Generate Asynchronous Delay Report" "false" -process "Place & Route" - project set "Generate Clock Region Report" "false" -process "Place & Route" - project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route" - project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route" - project set "Power Reduction" "false" -process "Place & Route" - project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route" - project set "Auto Implementation Compile Order" "true" - project set "Auto Implementation Top" "false" - project set "Equivalent Register Removal" "true" -process "Map" - project set "Placer Extra Effort" "None" -process "Map" - project set "Power Activity File" "" -process "Map" - project set "Retiming" "false" -process "Map" - project set "Synthesis Constraints File" "" -process "Synthesize - XST" - project set "RAM Style" "Auto" -process "Synthesize - XST" - project set "Verbose Property Persistence" "true" - project set "Encrypt Bitstream" "false" -process "Generate Programming File" - project set "Output File Name" "Top_PipelinedCipher" -process "Generate IBIS Model" - project set "Enable Multi-Threading" "Off" -process "Place & Route" - project set "Timing Mode" "Performance Evaluation" -process "Place & Route" - project set "Cycles for First BPI Page Read" "1" -process "Generate Programming File" - project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File" - project set "Create Logic Allocation File" "false" -process "Generate Programming File" - project set "Create Mask File" "false" -process "Generate Programming File" - project set "Watchdog Timer Value" "0x000000" -process "Generate Programming File" - project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File" - project set "Enable Multi-Threading" "Off" -process "Map" - project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST" - project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST" - project set "ROM Style" "Auto" -process "Synthesize - XST" - project set "Safe Implementation" "No" -process "Synthesize - XST" - project set "AES Initial Vector" "" -process "Generate Programming File" - project set "Power Activity File" "" -process "Place & Route" - project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route" - project set "HMAC Key (Hex String)" "" -process "Generate Programming File" - project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File" - project set "AES Key (Hex String)" "" -process "Generate Programming File" - project set "Input Encryption Key File" "" -process "Generate Programming File" - project set "Fallback Reconfiguration" "Enable" -process "Generate Programming File" - project set "Automatically Insert glbl Module in the Netlist" "true" -process "Generate Post-Place & Route Simulation Model" - project set "Include SIMPRIM Models in Verilog File" "true" -process "Generate Post-Place & Route Simulation Model" - project set "Include sdf_annotate task in Verilog File" "false" -process "Generate Post-Place & Route Simulation Model" - - puts "$myScript: project property values set." - -} ; # end set_process_props - -proc main {} { - - if { [llength $::argv] == 0 } { - show_help - return true - } - - foreach option $::argv { - switch $option { - "show_help" { show_help } - "run_process" { run_process } - "rebuild_project" { rebuild_project } - "set_project_props" { set_project_props } - "add_source_files" { add_source_files } - "create_libraries" { create_libraries } - "set_process_props" { set_process_props } - default { puts "unrecognized option: $option"; show_help } - } - } -} - -if { $tcl_interactive } { - show_help -} else { - if {[catch {main} result]} { - puts "$myScript failed: $result." - } -} - Index: aes-128_pipelined_encryption/trunk/syn/Top_PipelinedCipher.ucf =================================================================== --- aes-128_pipelined_encryption/trunk/syn/Top_PipelinedCipher.ucf (revision 2) +++ aes-128_pipelined_encryption/trunk/syn/Top_PipelinedCipher.ucf (nonexistent) @@ -1,4 +0,0 @@ - -#Created by Constraints Editor (xc6vcx240t-ff784-2) - 2013/06/28 -NET "clk" TNM_NET = clk; -TIMESPEC TS_clk = PERIOD "clk" 5 ns HIGH 50%; Index: aes-128_pipelined_encryption/trunk/syn/run.tcl =================================================================== --- aes-128_pipelined_encryption/trunk/syn/run.tcl (revision 2) +++ aes-128_pipelined_encryption/trunk/syn/run.tcl (nonexistent) @@ -1,5 +0,0 @@ -#put here your project directory -set project_directory . -cd $project_directory -source setup.tcl -rebuild_project \ No newline at end of file Index: aes-128_pipelined_encryption/tags/R0/doc/AES_Pipelined_Cipher.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: aes-128_pipelined_encryption/tags/R0/doc/AES_Pipelined_Cipher.pdf =================================================================== --- aes-128_pipelined_encryption/tags/R0/doc/AES_Pipelined_Cipher.pdf (revision 2) +++ aes-128_pipelined_encryption/tags/R0/doc/AES_Pipelined_Cipher.pdf (nonexistent)
aes-128_pipelined_encryption/tags/R0/doc/AES_Pipelined_Cipher.pdf Property changes : Deleted: svn:mime-type ## -1 +0,0 ## -application/octet-stream \ No newline at end of property Index: aes-128_pipelined_encryption/tags/R0/doc/release_notes.txt =================================================================== --- aes-128_pipelined_encryption/tags/R0/doc/release_notes.txt (revision 2) +++ aes-128_pipelined_encryption/tags/R0/doc/release_notes.txt (nonexistent) @@ -1,30 +0,0 @@ -DESIGN : 128 bit AES Pipelined Cipher - -RELEASE DATE: 07-07-2013 - -REVISION 0.0 - -FEATURES : - --One clock domain --Asynchronous reset --128 bit data --128 bit Cipher Key --Optimized for speed --Pipelined architecture - -BlOCKS STATUS: - -Top_PipelinedCipher completed - Functionally Verified -KeyExpantion completed - Functionally Verified -RoundKeyGen completed - Functionally Verified -Round completed - Functionally Verified -SubBytes completed - Functionally Verified -SBox completed - Functionally Verified -ShiftRows completed - Functionally Verified -MixColumns completed - Functionally Verified -AddRoundKey completed - Functionally Verified - -WHOLE DESIGN : completed - Functionally Verified using AESVS document test vectors (284 vector) - Synthesis , Place and Route on Xilinx virtex 6 6vcx240tff784-2 - Post Place and Route Simulation Verified \ No newline at end of file Index: aes-128_pipelined_encryption/tags/R0/sim/topcipher_test_outputs.txt =================================================================== --- aes-128_pipelined_encryption/tags/R0/sim/topcipher_test_outputs.txt (revision 2) +++ aes-128_pipelined_encryption/tags/R0/sim/topcipher_test_outputs.txt (nonexistent) @@ -1,284 +0,0 @@ -0336763e966d92595a567cc9ce537f5e -a9a1631bf4996954ebc093957b234589 -ff4f8391a6a40ca5b25d23bedd44a597 -dc43be40be0e53712f7e2bf5ca707209 -92beedab1895a94faa69b632e5cc47ce -459264f4798f6a78bacb89c15ed3d601 -08a4e2efec8a8e3312ca7460b9040bbf -6d251e6944b051e04eaa6fb4dbf78465 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-Description : -Owner : Amr Salah -*/ - -`timescale 1 ns/1 ps - -module Top_PipelinedCipher_tb(); - -parameter DATA_W = 128; //data width -parameter KEY_L = 128; //key length -parameter NO_ROUNDS = 10; //number of rounds -parameter Clk2Q = 2; //Clk-Q delay -parameter No_Patterns = 284; //number of patterns - -reg clk; -reg reset; -reg data_valid_in; -reg cipherkey_valid_in; -reg [KEY_L-1:0] cipher_key; -reg [DATA_W-1:0] plain_text; -wire valid_out; -wire[DATA_W-1:0]cipher_text; -reg dut_error; -reg [DATA_W-1:0] data_expected; -reg [DATA_W-1:0] data_input_vectors [0:No_Patterns-1] ; -reg [DATA_W-1:0] cipherkey_input_vectors [0:No_Patterns-1] ; -reg [DATA_W-1:0] output_vectors [0:No_Patterns-1] ; - -integer i; - -Top_PipelinedCipher U //connecting DUT -( -.clk(clk), -.reset(reset), -.data_valid_in(data_valid_in), -.cipherkey_valid_in(cipherkey_valid_in), -.cipher_key(cipher_key), -.plain_text(plain_text), -.valid_out(valid_out), -.cipher_text(cipher_text) -); - -event terminate_sim; -event reset_enable; - -initial begin //reading input data and cipherkey vectors and expected output vectors - -$readmemh("topcipher_data_test_inputs.txt",data_input_vectors); -$readmemh("topcipher_key_test_inputs.txt",cipherkey_input_vectors); -$readmemh("topcipher_test_outputs.txt",output_vectors); - -end - -initial begin - $display ("###################################################"); - clk = 0; - reset = 1; - data_valid_in = 0; - cipherkey_valid_in = 0; - dut_error = 0; //design error counter -end - -always - #5 clk = !clk; //clock generator - -`ifndef GATES //if not gate simulation -initial begin - $dumpfile("Top_PipelinedCipher.vcd"); - $dumpvars; -end -`endif - -initial -forever @ (terminate_sim) begin //simulation termination logic - $display ("Terminating simulation"); - if (dut_error == 0) begin - $display ("Simulation Result : PASSED"); - end - else begin - $display ("Simulation Result : FAILED"); - end - $display ("###################################################"); - #1 $stop; - -end - -event reset_done; - -initial //reset logic -forever begin - @ (reset_enable); - @ (negedge clk) - $display ("Applying reset"); - reset = 0; - data_expected = 'b0; - @ (negedge clk) - reset = 1; - $display ("Came out of Reset"); - -> reset_done; -end - -initial begin - #10 -> reset_enable; - @ (reset_done); - - for (i=0;i< No_Patterns;i=i+1) begin //apply inputs - @ (posedge clk) - #Clk2Q - data_valid_in = 1; //assert valid signals - cipherkey_valid_in = 1; - plain_text = data_input_vectors[i]; - cipher_key = cipherkey_input_vectors[i]; - end - - @(posedge clk) - data_valid_in = 0; //deassert valid signals - cipherkey_valid_in = 0; - -end - -integer j; - -initial @(reset_done) begin - -repeat((4 * NO_ROUNDS)+1) begin //waiting for first output (latency) -@(posedge clk); -end - -for(j=0;j< No_Patterns;j=j+1) begin //assign expected outputs -@(posedge clk) -data_expected = output_vectors[j]; -end - -end - - -//compare logic - -always @ (posedge clk) begin -if (valid_out || (!reset)) begin - if(data_expected != cipher_text) begin - $display ("DUT ERROR AT TIME%d",$time); - $display ("Expected Data value %h, Got Data Value %h", data_expected, cipher_text); - dut_error = 1; - -> terminate_sim; //stop simulation when error occures - end -end -if(j == No_Patterns) begin //terminate simulation after the end of output vectors - -> terminate_sim; -end - end -endmodule \ No newline at end of file Index: aes-128_pipelined_encryption/tags/R0/sim/topcipher_key_test_inputs.txt =================================================================== --- aes-128_pipelined_encryption/tags/R0/sim/topcipher_key_test_inputs.txt (revision 2) +++ aes-128_pipelined_encryption/tags/R0/sim/topcipher_key_test_inputs.txt (nonexistent) @@ -1,284 +0,0 @@ -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 -00000000000000000000000000000000 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aes-128_pipelined_encryption/tags/R0/sim/Top_PipelinedCipher.do (nonexistent) @@ -1,13 +0,0 @@ -vlib work -vlog ../rtl/SBox.v -vlog ../rtl/SubBytes.v -vlog ../rtl/ShiftRows.v -vlog ../rtl/MixColumns.v -vlog ../rtl/AddRoundKey.v -vlog ../rtl/Round.v -vlog ../rtl/RoundKeyGen.v -vlog ../rtl/KeyExpantion.v -vlog ../rtl/Top_PipelinedCipher.v -vlog ../sim/Top_PipelinedCipher_tb.v -vsim -novopt Top_PipelinedCipher_tb -run -a Index: aes-128_pipelined_encryption/tags/R0/sim/timesim.do =================================================================== --- aes-128_pipelined_encryption/tags/R0/sim/timesim.do (revision 2) +++ aes-128_pipelined_encryption/tags/R0/sim/timesim.do (nonexistent) @@ -1,4 +0,0 @@ -vlog Top_PipelinedCipher_tb.v -vlog ../syn/netgen/par/Top_PipelinedCipher_timesim.v -vsim +define+GATES -novopt -sdfmax /U/=../syn/netgen/par/Top_PipelinedCipher_timesim.sdf -novopt work.Top_PipelinedCipher_tb glbl -run -a \ No newline at end of file Index: aes-128_pipelined_encryption/tags/R0/syn/readme.txt =================================================================== --- aes-128_pipelined_encryption/tags/R0/syn/readme.txt (revision 2) +++ aes-128_pipelined_encryption/tags/R0/syn/readme.txt (nonexistent) @@ -1,8 +0,0 @@ -1-edit run.tcl and replace . with your project directory (that contains tcl files) - -2-edit setup.tcl at line 218 begin to add your files as shown -3-edit setup.tcl at line 230 set your top module - -4-open xilinx bash shell and point to the directory that contains tcl files then write xtclsh -5-write the command: source run.tcl -6-after running all processes the sdf file and the verilog netlist can be found in netgen folder Index: aes-128_pipelined_encryption/tags/R0/syn/setup.tcl =================================================================== --- aes-128_pipelined_encryption/tags/R0/syn/setup.tcl (revision 2) +++ aes-128_pipelined_encryption/tags/R0/syn/setup.tcl (nonexistent) @@ -1,493 +0,0 @@ -# -# Project automation script for AES -# -# Created for ISE version 12.1 -# -# This file contains several Tcl procedures (procs) that you can use to automate -# your project by running from xtclsh or the Project Navigator Tcl console. -# If you load this file (using the Tcl command: source AES.tcl), then you can -# run any of the procs included here. -# -# This script is generated assuming your project has HDL sources. -# Several of the defined procs won't apply to an EDIF or NGC based project. -# If that is the case, simply remove them from this script. -# -# You may also edit any of these procs to customize them. See comments in each -# proc for more instructions. -# -# This file contains the following procedures: -# -# Top Level procs (meant to be called directly by the user): -# run_process: you can use this top-level procedure to run any processes -# that you choose to by adding and removing comments, or by -# adding new entries. -# rebuild_project: you can alternatively use this top-level procedure -# to recreate your entire project, and the run selected processes. -# -# Lower Level (helper) procs (called under in various cases by the top level procs): -# show_help: print some basic information describing how this script works -# add_source_files: adds the listed source files to your project. -# set_project_props: sets the project properties that were in effect when this -# script was generated. -# create_libraries: creates and adds file to VHDL libraries that were defined when -# this script was generated. -# set_process_props: set the process properties as they were set for your project -# when this script was generated. -# - -set myProject "AES" -set myScript "setup.tcl" - -# -# Main (top-level) routines -# - -# -# run_process -# This procedure is used to run processes on an existing project. You may comment or -# uncomment lines to control which processes are run. This routine is set up to run -# the Implement Design and Generate Programming File processes by default. This proc -# also sets process properties as specified in the "set_process_props" proc. Only -# those properties which have values different from their current settings in the project -# file will be modified in the project. -# -proc run_process {} { - - global myScript - global myProject - - ## put out a 'heartbeat' - so we know something's happening. - puts "\n$myScript: running ($myProject)...\n" - - if { ! [ open_project ] } { - return false - } - - set_process_props - # - # Remove the comment characters (#'s) to enable the following commands - process run "Synthesize" - process run "Translate" - process run "Map" - process run "Place & Route" - process run "Generate Post-Place & Route Simulation Model" - # - puts "Running 'Implement Design'" - if { ! [ process run "Implement Design" ] } { - puts "$myScript: Implementation run failed, check run output for details." - project close - return - } - puts "Running 'Generate Programming File'" - if { ! [ process run "Generate Programming File" ] } { - puts "$myScript: Generate Programming File run failed, check run output for details." - project close - return - } - - puts "Run completed." - project close - -} - -# -# rebuild_project -# -# This procedure renames the project file (if it exists) and recreates the project. -# It then sets project properties and adds project sources as specified by the -# set_project_props and add_source_files support procs. It recreates VHDL libraries -# and partitions as they existed at the time this script was generated. -# -# It then calls run_process to set process properties and run selected processes. -# -proc rebuild_project {} { - - global myScript - global myProject - - project close - ## put out a 'heartbeat' - so we know something's happening. - puts "\n$myScript: Rebuilding ($myProject)...\n" - - set proj_exts [ list ise xise gise ] - foreach ext $proj_exts { - set proj_name "${myProject}.$ext" - if { [ file exists $proj_name ] } { - file delete $proj_name - } - } - - project new $myProject - set_project_props - add_source_files - create_libraries - puts "$myScript: project rebuild completed." - - run_process - -} - -# -# Support Routines -# - -# -# show_help: print information to help users understand the options available when -# running this script. -# -proc show_help {} { - - global myScript - - puts "" - puts "usage: xtclsh $myScript " - puts " or you can run xtclsh and then enter 'source $myScript'." - puts "" - puts "options:" - puts " run_process - set properties and run processes." - puts " rebuild_project - rebuild the project from scratch and run processes." - puts " set_project_props - set project properties (device, speed, etc.)" - puts " add_source_files - add source files" - puts " create_libraries - create vhdl libraries" - puts " set_process_props - set process property values" - puts " show_help - print this message" - puts "" -} - -proc open_project {} { - - global myScript - global myProject - - if { ! [ file exists ${myProject}.xise ] } { - ## project file isn't there, rebuild it. - puts "Project $myProject not found. Use project_rebuild to recreate it." - return false - } - - project open $myProject - - return true - -} -# -# set_project_props -# -# This procedure sets the project properties as they were set in the project -# at the time this script was generated. -# -proc set_project_props {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Setting project properties..." - - project set family "Virtex6" - project set device "xc6vcx240t" - project set package "ff784" - project set speed "-2" - project set top_level_module_type "HDL" - project set synthesis_tool "XST (VHDL/Verilog)" - project set simulator "Modelsim-SE Verilog" - project set "Preferred Language" "Verilog" - project set "Enable Message Filtering" "false" - -} - - -# -# add_source_files -# -# This procedure add the source files that were known to the project at the -# time this script was generated. -# -proc add_source_files {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Adding sources to project..." - - xfile add "../rtl/AddRoundKey.v" - xfile add "../rtl/KeyExpantion.v" - xfile add "../rtl/MixColumns.v" - xfile add "../rtl/Round.v" - xfile add "../rtl/RoundKeyGen.v" - xfile add "../rtl/SBox.v" - xfile add "../rtl/ShiftRows.v" - xfile add "../rtl/SubBytes.v" - xfile add "../rtl/Top_PipelinedCipher.v" - xfile add "./Top_PipelinedCipher.ucf" - - # Set the Top Module as well... - project set top "Top_PipelinedCipher" - - puts "$myScript: project sources reloaded." - -} ; # end add_source_files - -# -# create_libraries -# -# This procedure defines VHDL libraries and associates files with those libraries. -# It is expected to be used when recreating the project. Any libraries defined -# when this script was generated are recreated by this procedure. -# -proc create_libraries {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: Creating libraries..." - - - # must close the project or library definitions aren't saved. - project save - -} ; # end create_libraries - -# -# set_process_props -# -# This procedure sets properties as requested during script generation (either -# all of the properties, or only those modified from their defaults). -# -proc set_process_props {} { - - global myScript - - if { ! [ open_project ] } { - return false - } - - puts "$myScript: setting process properties..." - - project set "Compiled Library Directory" "\$XILINX//" - project set "Global Optimization" "Off" -process "Map" - project set "Use DSP Block" "Auto" -process "Synthesize - XST" - project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File" - project set "Configuration Rate" "2" -process "Generate Programming File" - project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map" - project set "Place And Route Mode" "Route Only" -process "Place & Route" - project set "Number of Clock Buffers" "32" -process "Synthesize - XST" - project set "Max Fanout" "100000" -process "Synthesize - XST" - project set "Use Clock Enable" "Auto" -process "Synthesize - XST" - project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST" - project set "Use Synchronous Set" "Auto" -process "Synthesize - XST" - project set "Enable Hardware Co-Simulation" "false" - project set "Filter Files From Compile Order" "true" - #project set "Use Custom Project File" "false" -process "Post-Map Check Syntax" - #project set "Use Custom Project File" "false" -process "Post-Place & Route Check Syntax" - #project set "Use Custom Project File" "false" -process "Post-Translate Check Syntax" - project set "Last Applied Goal" "Balanced" - project set "Last Applied Strategy" "Xilinx Default (unlocked)" - project set "Last Unlock Status" "false" - project set "Manual Compile Order" "false" - project set "Placer Effort Level" "High" -process "Map" - project set "Extra Cost Tables" "0" -process "Map" - project set "LUT Combining" "Off" -process "Map" - project set "Combinatorial Logic Optimization" "false" -process "Map" - project set "Starting Placer Cost Table (1-100)" "1" -process "Map" - project set "Power Reduction" "Off" -process "Map" - project set "Register Duplication" "Off" -process "Map" - project set "Project Generator" "ProjNav" - project set "Property Specification in Project File" "Store all values" - project set "Reduce Control Sets" "Auto" -process "Synthesize - XST" - project set "Selected Module Instance Name" "/Top_PipelinedCipher_tb" - project set "Shift Register Minimum Size" "2" -process "Synthesize - XST" - project set "Case Implementation Style" "None" -process "Synthesize - XST" - project set "Mux Extraction" "Yes" - project set "RAM Extraction" "true" -process "Synthesize - XST" - project set "ROM Extraction" "true" -process "Synthesize - XST" - project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST" - project set "Optimization Goal" "Speed" -process "Synthesize - XST" - project set "Optimization Effort" "Normal" -process "Synthesize - XST" - project set "Resource Sharing" "true" -process "Synthesize - XST" - project set "Shift Register Extraction" "true" -process "Synthesize - XST" - project set "User Browsed Strategy Files" "" - project set "VHDL Source Analysis Standard" "VHDL-93" - project set "Working Directory" "." - project set "JTAG to System Monitor Connection" "Enable" -process "Generate Programming File" - project set "Other Bitgen Command Line Options" "" -process "Generate Programming File" - project set "Generate Detailed Package Parasitics" "false" -process "Generate IBIS Model" - project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model" - project set "Show All Models" "false" -process "Generate IBIS Model" - project set "Target UCF File Name" "" -process "Back-annotate Pin Locations" - project set "Ignore User Timing Constraints" "false" -process "Map" - project set "Use RLOC Constraints" "Yes" -process "Map" - project set "Other Map Command Line Options" "" -process "Map" - project set "Use LOC Constraints" "true" -process "Translate" - project set "Other Ngdbuild Command Line Options" "" -process "Translate" - project set "Ignore User Timing Constraints" "false" -process "Place & Route" - project set "Other Place & Route Command Line Options" "" -process "Place & Route" - project set "BPI Reads Per Page" "1" -process "Generate Programming File" - project set "Configuration Pin Busy" "Pull Up" -process "Generate Programming File" - project set "Configuration Clk (Configuration Pins)" "Pull Up" -process "Generate Programming File" - project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File" - project set "Configuration Pin CS" "Pull Up" -process "Generate Programming File" - project set "DCI Update Mode" "As Required" -process "Generate Programming File" - project set "Configuration Pin DIn" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File" - project set "Create ASCII Configuration File" "false" -process "Generate Programming File" - project set "Create Binary Configuration File" "false" -process "Generate Programming File" - project set "Create Bit File" "true" -process "Generate Programming File" - project set "Enable BitStream Compression" "false" -process "Generate Programming File" - project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File" - project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File" - project set "Create ReadBack Data Files" "false" -process "Generate Programming File" - project set "Configuration Pin HSWAPEN" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin Init" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin M0" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin M1" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin M2" "Pull Up" -process "Generate Programming File" - project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File" - project set "Power Down Device if Over Safe Temperature" "false" -process "Generate Programming File" - project set "Configuration Pin RdWr" "Pull Up" -process "Generate Programming File" - project set "Starting Address for Fallback Configuration" "0x00000000" -process "Generate Programming File" - project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File" - project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File" - project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File" - project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File" - project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File" - project set "Watchdog Timer Mode" "Off" -process "Generate Programming File" - project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File" - project set "Done (Output Events)" "Default (4)" -process "Generate Programming File" - project set "Drive Done Pin High" "false" -process "Generate Programming File" - project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File" - project set "Wait for DCI Match (Output Events)" "Auto" -process "Generate Programming File" - project set "Wait for PLL Lock (Output Events)" "No Wait" -process "Generate Programming File" - project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File" - project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File" - project set "Enable Internal Done Pipe" "false" -process "Generate Programming File" - project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map" - project set "Maximum Compression" "false" -process "Map" - project set "Generate Detailed MAP Report" "false" -process "Map" - project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map" - project set "Perform Timing-Driven Packing and Placement" "false" - project set "Trim Unconnected Signals" "true" -process "Map" - project set "Create I/O Pads from Ports" "false" -process "Translate" - project set "Macro Search Path" "" -process "Translate" - project set "Netlist Translation Type" "Timestamp" -process "Translate" - project set "User Rules File for Netlister Launcher" "" -process "Translate" - project set "Allow Unexpanded Blocks" "false" -process "Translate" - project set "Allow Unmatched LOC Constraints" "false" -process "Translate" - project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate" - project set "Add I/O Buffers" "true" -process "Synthesize - XST" - project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST" - project set "Keep Hierarchy" "No" -process "Synthesize - XST" - project set "Register Balancing" "No" -process "Synthesize - XST" - project set "Register Duplication" "true" -process "Synthesize - XST" - project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST" - project set "Automatic BRAM Packing" "false" -process "Synthesize - XST" - project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST" - project set "Bus Delimiter" "<>" -process "Synthesize - XST" - project set "Case" "Maintain" -process "Synthesize - XST" - project set "Cores Search Directories" "" -process "Synthesize - XST" - project set "Cross Clock Analysis" "false" -process "Synthesize - XST" - project set "DSP Utilization Ratio" "100" -process "Synthesize - XST" - project set "Equivalent Register Removal" "true" -process "Synthesize - XST" - project set "FSM Style" "LUT" -process "Synthesize - XST" - project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST" - project set "Generics, Parameters" "" -process "Synthesize - XST" - project set "Hierarchy Separator" "/" -process "Synthesize - XST" - project set "HDL INI File" "" -process "Synthesize - XST" - project set "LUT Combining" "Auto" -process "Synthesize - XST" - project set "Library Search Order" "" -process "Synthesize - XST" - project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST" - project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST" - project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST" - project set "Power Reduction" "false" -process "Synthesize - XST" - project set "Read Cores" "true" -process "Synthesize - XST" - project set "LUT-FF Pairs Utilization Ratio" "100" -process "Synthesize - XST" - project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST" - project set "Verilog Include Directories" "" -process "Synthesize - XST" - project set "Verilog 2001" "true" - project set "Verilog Macros" "" -process "Synthesize - XST" - project set "Write Timing Constraints" "false" -process "Synthesize - XST" - project set "Other XST Command Line Options" "" -process "Synthesize - XST" - project set "Timing Mode" "Performance Evaluation" -process "Map" - project set "Generate Asynchronous Delay Report" "false" -process "Place & Route" - project set "Generate Clock Region Report" "false" -process "Place & Route" - project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route" - project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route" - project set "Power Reduction" "false" -process "Place & Route" - project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route" - project set "Auto Implementation Compile Order" "true" - project set "Auto Implementation Top" "false" - project set "Equivalent Register Removal" "true" -process "Map" - project set "Placer Extra Effort" "None" -process "Map" - project set "Power Activity File" "" -process "Map" - project set "Retiming" "false" -process "Map" - project set "Synthesis Constraints File" "" -process "Synthesize - XST" - project set "RAM Style" "Auto" -process "Synthesize - XST" - project set "Verbose Property Persistence" "true" - project set "Encrypt Bitstream" "false" -process "Generate Programming File" - project set "Output File Name" "Top_PipelinedCipher" -process "Generate IBIS Model" - project set "Enable Multi-Threading" "Off" -process "Place & Route" - project set "Timing Mode" "Performance Evaluation" -process "Place & Route" - project set "Cycles for First BPI Page Read" "1" -process "Generate Programming File" - project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File" - project set "Create Logic Allocation File" "false" -process "Generate Programming File" - project set "Create Mask File" "false" -process "Generate Programming File" - project set "Watchdog Timer Value" "0x000000" -process "Generate Programming File" - project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File" - project set "Enable Multi-Threading" "Off" -process "Map" - project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST" - project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST" - project set "ROM Style" "Auto" -process "Synthesize - XST" - project set "Safe Implementation" "No" -process "Synthesize - XST" - project set "AES Initial Vector" "" -process "Generate Programming File" - project set "Power Activity File" "" -process "Place & Route" - project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route" - project set "HMAC Key (Hex String)" "" -process "Generate Programming File" - project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File" - project set "AES Key (Hex String)" "" -process "Generate Programming File" - project set "Input Encryption Key File" "" -process "Generate Programming File" - project set "Fallback Reconfiguration" "Enable" -process "Generate Programming File" - project set "Automatically Insert glbl Module in the Netlist" "true" -process "Generate Post-Place & Route Simulation Model" - project set "Include SIMPRIM Models in Verilog File" "true" -process "Generate Post-Place & Route Simulation Model" - project set "Include sdf_annotate task in Verilog File" "false" -process "Generate Post-Place & Route Simulation Model" - - puts "$myScript: project property values set." - -} ; # end set_process_props - -proc main {} { - - if { [llength $::argv] == 0 } { - show_help - return true - } - - foreach option $::argv { - switch $option { - "show_help" { show_help } - "run_process" { run_process } - "rebuild_project" { rebuild_project } - "set_project_props" { set_project_props } - "add_source_files" { add_source_files } - "create_libraries" { create_libraries } - "set_process_props" { set_process_props } - default { puts "unrecognized option: $option"; show_help } - } - } -} - -if { $tcl_interactive } { - show_help -} else { - if {[catch {main} result]} { - puts "$myScript failed: $result." - } -} - Index: aes-128_pipelined_encryption/tags/R0/syn/Top_PipelinedCipher.ucf =================================================================== --- aes-128_pipelined_encryption/tags/R0/syn/Top_PipelinedCipher.ucf (revision 2) +++ aes-128_pipelined_encryption/tags/R0/syn/Top_PipelinedCipher.ucf (nonexistent) @@ -1,4 +0,0 @@ - -#Created by Constraints Editor (xc6vcx240t-ff784-2) - 2013/06/28 -NET "clk" TNM_NET = clk; -TIMESPEC TS_clk = PERIOD "clk" 5 ns HIGH 50%; Index: aes-128_pipelined_encryption/tags/R0/syn/run.tcl =================================================================== --- aes-128_pipelined_encryption/tags/R0/syn/run.tcl (revision 2) +++ aes-128_pipelined_encryption/tags/R0/syn/run.tcl (nonexistent) @@ -1,5 +0,0 @@ -#put here your project directory -set project_directory . -cd $project_directory -source setup.tcl -rebuild_project \ No newline at end of file Index: aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher_map.mrp =================================================================== --- aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher_map.mrp (revision 2) +++ aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher_map.mrp (nonexistent) @@ -1,581 +0,0 @@ -Release 12.1 Map M.53d (nt64) -Xilinx Mapping Report File for Design 'Top_PipelinedCipher' - -Design Information ------------------- -Command Line : map -intstyle ise -p xc6vcx240t-ff784-2 -w -ol high -t 1 -xt 0 --register_duplication off -global_opt off -ir off -pr off -lc off -power off -o -Top_PipelinedCipher_map.ncd Top_PipelinedCipher.ngd Top_PipelinedCipher.pcf -Target Device : xc6vcx240t -Target Package : ff784 -Target Speed : -2 -Mapper Version : virtex6 -- $Revision: 1.52 $ -Mapped Date : Wed Jul 17 15:14:08 2013 - -Design Summary --------------- -Number of errors: 0 -Number of warnings: 0 -Slice Logic Utilization: - Number of Slice Registers: 10,769 out of 301,440 3% - Number used as Flip Flops: 10,769 - Number used as Latches: 0 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 0 - Number of Slice LUTs: 12,475 out of 150,720 8% - Number used as logic: 9,842 out of 150,720 6% - Number using O6 output only: 9,081 - Number using O5 output only: 0 - Number using O5 and O6: 761 - Number used as ROM: 0 - Number used as Memory: 0 out of 58,400 0% - Number used exclusively as route-thrus: 2,633 - Number with same-slice register load: 2,633 - Number with same-slice carry load: 0 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 3,214 out of 37,680 8% - Number of LUT Flip Flop pairs used: 12,527 - Number with an unused Flip Flop: 5,031 out of 12,527 40% - Number with an unused LUT: 52 out of 12,527 1% - Number of fully used LUT-FF pairs: 7,444 out of 12,527 59% - Number of unique control sets: 82 - Number of slice register sites lost - to control set restrictions: 7 out of 301,440 1% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 389 out of 400 97% - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 0 out of 416 0% - Number of RAMB18E1/FIFO18E1s: 0 out of 832 0% - Number of BUFG/BUFGCTRLs: 2 out of 32 6% - Number used as BUFGs: 2 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 0 out of 720 0% - Number of OLOGICE1/OSERDESE1s: 0 out of 720 0% - Number of BSCANs: 0 out of 4 0% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFOs: 0 out of 36 0% - Number of BUFIODQSs: 0 out of 72 0% - Number of BUFRs: 0 out of 36 0% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 0 out of 768 0% - Number of EFUSE_USRs: 0 out of 1 0% - Number of GTXE1s: 0 out of 12 0% - Number of IBUFDS_GTXE1s: 0 out of 8 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 0 out of 18 0% - Number of IODELAYE1s: 0 out of 720 0% - Number of MMCM_ADVs: 0 out of 12 0% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 1 0% - -Average Fanout of Non-Clock Nets: 7.45 - -Peak Memory Usage: 1019 MB -Total REAL time to MAP completion: 3 mins 28 secs -Total CPU time to MAP completion: 3 mins 19 secs - -Table of Contents ------------------ -Section 1 - Errors -Section 2 - Warnings -Section 3 - Informational -Section 4 - Removed Logic Summary -Section 5 - Removed Logic -Section 6 - IOB Properties -Section 7 - RPMs -Section 8 - Guide Report -Section 9 - Area Group and Partition Summary -Section 10 - Timing Report -Section 11 - Configuration String Information -Section 12 - Control Set Information -Section 13 - Utilization by Hierarchy - -Section 1 - Errors ------------------- - -Section 2 - Warnings --------------------- -WARNING:Security:42 - Your software subscription period has lapsed. Your current -version of Xilinx tools will continue to function, but you no longer qualify for -Xilinx software updates or new releases. - -Section 3 - Informational -------------------------- -INFO:Security:56 - Part 'xc6vcx240t' is not a WebPack part. -INFO:MapLib:562 - No environment variables are currently set. -INFO:LIT:244 - All of the single ended outputs in this design are using slew - rate limited output drivers. The delay on speed critical single ended outputs - can be dramatically reduced by designating them as fast outputs. -INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: - 0.000 to 85.000 Celsius) -INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to - 1.050 Volts) -INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report - (.mrp). -INFO:Pack:1650 - Map created a placed design. - -Section 4 - Removed Logic Summary ---------------------------------- - -Section 5 - Removed Logic -------------------------- - -Section 6 - IOB Properties --------------------------- - -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | -| | | | | Term | Strength | Rate | | | Delay | -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ -| cipher_key<0> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<1> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<2> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<3> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<4> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<5> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<6> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<7> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<8> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<9> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<10> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<11> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<12> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<13> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<14> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<15> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<16> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<17> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<18> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<19> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<20> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<21> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<22> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<23> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<24> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<25> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<26> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<27> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<28> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<29> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<30> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<31> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<32> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<33> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<34> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<35> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<36> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<37> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<38> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<39> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<40> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<41> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<42> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<43> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<44> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<45> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<46> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<47> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<48> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<49> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<50> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<51> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<52> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<53> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<54> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<55> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<56> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<57> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<58> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<59> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<60> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<61> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<62> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<63> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<64> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<65> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<66> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<67> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<68> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<69> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<70> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<71> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<72> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<73> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<74> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<75> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<76> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<77> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<78> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<79> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<80> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<81> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<82> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<83> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<84> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<85> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<86> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<87> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<88> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<89> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<90> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<91> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<92> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<93> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<94> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<95> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<96> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<97> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<98> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<99> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<100> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<101> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<102> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<103> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<104> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<105> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<106> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<107> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<108> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<109> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<110> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<111> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<112> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<113> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<114> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<115> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<116> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<117> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<118> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<119> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<120> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<121> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<122> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<123> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<124> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<125> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<126> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_key<127> | IOB | INPUT | LVCMOS25 | | | | | | | -| cipher_text<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<8> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<9> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<10> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<11> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<12> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<13> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<14> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<15> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<16> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<17> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<18> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<19> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<20> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<21> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<22> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<23> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<24> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<25> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<26> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<27> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<28> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<29> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<30> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<31> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<32> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<33> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<34> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<35> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<36> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<37> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<38> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<39> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<40> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<41> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<42> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<43> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<44> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<45> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<46> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<47> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<48> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<49> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<50> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<51> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<52> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<53> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<54> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<55> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<56> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<57> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<58> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<59> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<60> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<61> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<62> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<63> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<64> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<65> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<66> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<67> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<68> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<69> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<70> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<71> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<72> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<73> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<74> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<75> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<76> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<77> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<78> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<79> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<80> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<81> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<82> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<83> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<84> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<85> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<86> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<87> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<88> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<89> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<90> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<91> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<92> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<93> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<94> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<95> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<96> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<97> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<98> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<99> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<100> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<101> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<102> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<103> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<104> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<105> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<106> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<107> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<108> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<109> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<110> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<111> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<112> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<113> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<114> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<115> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<116> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<117> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<118> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<119> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<120> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<121> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<122> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<123> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<124> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<125> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<126> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipher_text<127> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| cipherkey_valid_in | IOB | INPUT | LVCMOS25 | | | | | | | -| clk | IOB | INPUT | LVCMOS25 | | | | | | | -| data_valid_in | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<0> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<1> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<2> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<3> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<4> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<5> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<6> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<7> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<8> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<9> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<10> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<11> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<12> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<13> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<14> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<15> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<16> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<17> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<18> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<19> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<20> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<21> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<22> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<23> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<24> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<25> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<26> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<27> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<28> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<29> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<30> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<31> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<32> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<33> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<34> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<35> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<36> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<37> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<38> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<39> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<40> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<41> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<42> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<43> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<44> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<45> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<46> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<47> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<48> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<49> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<50> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<51> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<52> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<53> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<54> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<55> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<56> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<57> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<58> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<59> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<60> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<61> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<62> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<63> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<64> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<65> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<66> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<67> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<68> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<69> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<70> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<71> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<72> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<73> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<74> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<75> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<76> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<77> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<78> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<79> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<80> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<81> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<82> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<83> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<84> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<85> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<86> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<87> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<88> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<89> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<90> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<91> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<92> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<93> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<94> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<95> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<96> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<97> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<98> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<99> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<100> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<101> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<102> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<103> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<104> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<105> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<106> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<107> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<108> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<109> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<110> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<111> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<112> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<113> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<114> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<115> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<116> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<117> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<118> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<119> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<120> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<121> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<122> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<123> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<124> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<125> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<126> | IOB | INPUT | LVCMOS25 | | | | | | | -| plain_text<127> | IOB | INPUT | LVCMOS25 | | | | | | | -| reset | IOB | INPUT | LVCMOS25 | | | | | | | -| valid_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -+---------------------------------------------------------------------------------------------------------------------------------------------------------+ - -Section 7 - RPMs ----------------- - -Section 8 - Guide Report ------------------------- -Guide not run on this design. - -Section 9 - Area Group and Partition Summary --------------------------------------------- - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Area Group Information ----------------------- - - No area groups were found in this design. - ----------------------- - -Section 10 - Timing Report --------------------------- -A logic-level (pre-route) timing report can be generated by using Xilinx static -timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the -mapped NCD and PCF files. Please note that this timing report will be generated -using estimated delay information. For accurate numbers, please generate a -timing report with the post Place and Route NCD file. - -For more information about the Timing Analyzer, consult the Xilinx Timing -Analyzer Reference Manual; for more information about TRCE, consult the Xilinx -Command Line Tools User Guide "TRACE" chapter. - -Section 11 - Configuration String Details ------------------------------------------ -Use the "-detail" map option to print out Configuration Strings - -Section 12 - Control Set Information ------------------------------------- -Use the "-detail" map option to print out Control Set Information. - -Section 13 - Utilization by Hierarchy -------------------------------------- -Use the "-detail" map option to print out the Utilization by Hierarchy section. Index: aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.twr =================================================================== --- aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.twr (revision 2) +++ aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.twr (nonexistent) @@ -1,291 +0,0 @@ --------------------------------------------------------------------------------- -Release 12.1 Trace (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -E:\ISE12\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3 --fastpaths -xml Top_PipelinedCipher.twx Top_PipelinedCipher.ncd -o -Top_PipelinedCipher.twr Top_PipelinedCipher.pcf -ucf Top_PipelinedCipher.ucf - -Design file: Top_PipelinedCipher.ncd -Physical constraint file: Top_PipelinedCipher.pcf -Device,package,speed: xc6vcx240t,ff784,C,-2 (PRELIMINARY 1.04 2010-04-09) -Report level: verbose report - -Environment Variable Effect --------------------- ------ -NONE No environment variables were set --------------------------------------------------------------------------------- - -INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths - option. All paths that are not constrained will be reported in the - unconstrained paths section(s) of the report. -INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on - a 50 Ohm transmission line loading model. For the details of this model, - and for more information on accounting for different loading conditions, - please see the device datasheet. - -================================================================================ -Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%; - - 75065 paths analyzed, 74633 endpoints analyzed, 0 failing endpoints - 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) - Minimum period is 4.952ns. --------------------------------------------------------------------------------- - -Paths for end point ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_0 (SLICE_X40Y71.CE), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 0.048ns (requirement - (data path - clock path skew + uncertainty)) - Source: U0_ARK/valid_out (FF) - Destination: ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_0 (FF) - Requirement: 5.000ns - Data Path Delay: 4.893ns (Levels of Logic = 0) - Clock Path Skew: -0.024ns (1.569 - 1.593) - Source Clock: clk_BUFGP rising at 0.000ns - Destination Clock: clk_BUFGP rising at 5.000ns - Clock Uncertainty: 0.035ns - - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.070ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Maximum Data Path at Slow Process Corner: U0_ARK/valid_out to ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_0 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X62Y140.AQ Tcko 0.337 U0_ARK/valid_out - U0_ARK/valid_out - SLICE_X40Y71.CE net (fanout=129) 4.272 U0_ARK/valid_out - SLICE_X40Y71.CLK Tceck 0.284 ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout<0> - ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_0 - ------------------------------------------------- --------------------------- - Total 4.893ns (0.621ns logic, 4.272ns route) - (12.7% logic, 87.3% route) - --------------------------------------------------------------------------------- - -Paths for end point ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_1 (SLICE_X43Y72.CE), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 0.150ns (requirement - (data path - clock path skew + uncertainty)) - Source: U0_ARK/valid_out (FF) - Destination: ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_1 (FF) - Requirement: 5.000ns - Data Path Delay: 4.797ns (Levels of Logic = 0) - Clock Path Skew: -0.018ns (1.575 - 1.593) - Source Clock: clk_BUFGP rising at 0.000ns - Destination Clock: clk_BUFGP rising at 5.000ns - Clock Uncertainty: 0.035ns - - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.070ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Maximum Data Path at Slow Process Corner: U0_ARK/valid_out to ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_1 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X62Y140.AQ Tcko 0.337 U0_ARK/valid_out - U0_ARK/valid_out - SLICE_X43Y72.CE net (fanout=129) 4.142 U0_ARK/valid_out - SLICE_X43Y72.CLK Tceck 0.318 ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout<1> - ROUND[0].U_ROUND/U_SUB/ROM[4].ROM/dout_1 - ------------------------------------------------- --------------------------- - Total 4.797ns (0.655ns logic, 4.142ns route) - (13.7% logic, 86.3% route) - --------------------------------------------------------------------------------- - -Paths for end point ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout_2 (SLICE_X43Y76.CE), 1 path --------------------------------------------------------------------------------- -Slack (setup path): 0.159ns (requirement - (data path - clock path skew + uncertainty)) - Source: U0_ARK/valid_out (FF) - Destination: ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout_2 (FF) - Requirement: 5.000ns - Data Path Delay: 4.789ns (Levels of Logic = 0) - Clock Path Skew: -0.017ns (1.576 - 1.593) - Source Clock: clk_BUFGP rising at 0.000ns - Destination Clock: clk_BUFGP rising at 5.000ns - Clock Uncertainty: 0.035ns - - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.070ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Maximum Data Path at Slow Process Corner: U0_ARK/valid_out to ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout_2 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X62Y140.AQ Tcko 0.337 U0_ARK/valid_out - U0_ARK/valid_out - SLICE_X43Y76.CE net (fanout=129) 4.134 U0_ARK/valid_out - SLICE_X43Y76.CLK Tceck 0.318 ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout<2> - ROUND[0].U_ROUND/U_SUB/ROM[3].ROM/dout_2 - ------------------------------------------------- --------------------------- - Total 4.789ns (0.655ns logic, 4.134ns route) - (13.7% logic, 86.3% route) - --------------------------------------------------------------------------------- - -Hold Paths: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%; --------------------------------------------------------------------------------- - -Paths for end point U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed_4 (SLICE_X60Y160.A5), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 0.006ns (requirement - (clock path skew + uncertainty - data path)) - Source: U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout_4 (FF) - Destination: U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed_4 (FF) - Requirement: 0.000ns - Data Path Delay: 0.116ns (Levels of Logic = 1) - Clock Path Skew: 0.110ns (0.784 - 0.674) - Source Clock: clk_BUFGP rising at 5.000ns - Destination Clock: clk_BUFGP rising at 5.000ns - Clock Uncertainty: 0.000ns - - Minimum Data Path at Fast Process Corner: U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout_4 to U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed_4 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X61Y158.BQ Tcko 0.098 U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout<4> - U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout_4 - SLICE_X60Y160.A5 net (fanout=2) 0.119 U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/SUB_U/ROM[0].ROM/dout<4> - SLICE_X60Y160.CLK Tah (-Th) 0.101 U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed<39> - U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/temp_round_key<4>1 - U_KEYEXP/ROUND_KEY_GEN[8].RKGEN_U/round_key_delayed_4 - ------------------------------------------------- --------------------------- - Total 0.116ns (-0.003ns logic, 0.119ns route) - (-2.6% logic, 102.6% route) - --------------------------------------------------------------------------------- - -Paths for end point U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed_12 (SLICE_X40Y160.A5), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 0.016ns (requirement - (clock path skew + uncertainty - data path)) - Source: U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage_12 (FF) - Destination: U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed_12 (FF) - Requirement: 0.000ns - Data Path Delay: 0.124ns (Levels of Logic = 1) - Clock Path Skew: 0.108ns (0.748 - 0.640) - Source Clock: clk_BUFGP rising at 5.000ns - Destination Clock: clk_BUFGP rising at 5.000ns - Clock Uncertainty: 0.000ns - - Minimum Data Path at Fast Process Corner: U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage_12 to U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed_12 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X40Y159.CQ Tcko 0.115 U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage<14> - U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage_12 - SLICE_X40Y160.A5 net (fanout=1) 0.110 U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/Key_SecondStage<12> - SLICE_X40Y160.CLK Tah (-Th) 0.101 U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed<47> - U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/temp_round_key<12>1 - U_KEYEXP/ROUND_KEY_GEN[7].RKGEN_U/round_key_delayed_12 - ------------------------------------------------- --------------------------- - Total 0.124ns (0.014ns logic, 0.110ns route) - (11.3% logic, 88.7% route) - --------------------------------------------------------------------------------- - -Paths for end point ROUND[8].U_ROUND/U_MIX/data_out_38 (SLICE_X54Y160.B6), 1 path --------------------------------------------------------------------------------- -Slack (hold path): 0.028ns (requirement - (clock path skew + uncertainty - data path)) - Source: ROUND[8].U_ROUND/U_SH/data_out_46 (FF) - Destination: ROUND[8].U_ROUND/U_MIX/data_out_38 (FF) - Requirement: 0.000ns - Data Path Delay: 0.137ns (Levels of Logic = 1) - Clock Path Skew: 0.109ns (0.773 - 0.664) - Source Clock: clk_BUFGP rising at 5.000ns - Destination Clock: clk_BUFGP rising at 5.000ns - Clock Uncertainty: 0.000ns - - Minimum Data Path at Fast Process Corner: ROUND[8].U_ROUND/U_SH/data_out_46 to ROUND[8].U_ROUND/U_MIX/data_out_38 - Location Delay type Delay(ns) Physical Resource - Logical Resource(s) - ------------------------------------------------- ------------------- - SLICE_X54Y159.DQ Tcko 0.115 ROUND[8].U_ROUND/U_SH/data_out<46> - ROUND[8].U_ROUND/U_SH/data_out_46 - SLICE_X54Y160.B6 net (fanout=5) 0.099 ROUND[8].U_ROUND/U_SH/data_out<46> - SLICE_X54Y160.CLK Tah (-Th) 0.077 ROUND[8].U_ROUND/U_MIX/data_out<40> - ROUND[8].U_ROUND/U_MIX/Mxor_State_Mulx3[8][7]_State_Mulx2[11][7]_xor_99_OUT_6_xo<0>1 - ROUND[8].U_ROUND/U_MIX/data_out_38 - ------------------------------------------------- --------------------------- - Total 0.137ns (0.038ns logic, 0.099ns route) - (27.7% logic, 72.3% route) - --------------------------------------------------------------------------------- - -Component Switching Limit Checks: TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 50%; --------------------------------------------------------------------------------- -Slack: 3.571ns (period - min period limit) - Period: 5.000ns - Min period limit: 1.429ns (699.790MHz) (Tbcper_I) - Physical resource: clk_BUFGP/BUFG/I0 - Logical resource: clk_BUFGP/BUFG/I0 - Location pin: BUFGCTRL_X0Y0.I0 - Clock network: clk_BUFGP/IBUFG --------------------------------------------------------------------------------- -Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) - Period: 5.000ns - High pulse: 2.500ns - High pulse limit: 0.416ns (Trpw) - Physical resource: U_KEYEXP/ROUND_KEY_GEN[2].RKGEN_U/SUB_U/ROM[2].ROM/dout<5>/SR - Logical resource: U_KEYEXP/ROUND_KEY_GEN[2].RKGEN_U/SUB_U/ROM[2].ROM/dout_5/SR - Location pin: SLICE_X0Y81.SR - Clock network: ROUND[0].U_ROUND/U_KEY/reset_inv_BUFG --------------------------------------------------------------------------------- -Slack: 4.168ns (period - (min high pulse limit / (high pulse / period))) - Period: 5.000ns - High pulse: 2.500ns - High pulse limit: 0.416ns (Trpw) - Physical resource: U_KEYEXP/ROUND_KEY_GEN[2].RKGEN_U/SUB_U/ROM[2].ROM/dout<1>/SR - Logical resource: U_KEYEXP/ROUND_KEY_GEN[2].RKGEN_U/SUB_U/ROM[2].ROM/dout_1/SR - Location pin: SLICE_X0Y85.SR - Clock network: ROUND[0].U_ROUND/U_KEY/reset_inv_BUFG --------------------------------------------------------------------------------- - - -All constraints were met. - - -Data Sheet report: ------------------ -All values displayed in nanoseconds (ns) - -Clock to Setup on destination clock clk ----------------+---------+---------+---------+---------+ - | Src:Rise| Src:Fall| Src:Rise| Src:Fall| -Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ----------------+---------+---------+---------+---------+ -clk | 4.952| | | | ----------------+---------+---------+---------+---------+ - - -Timing summary: ---------------- - -Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) - -Constraints cover 75065 paths, 0 nets, and 69159 connections - -Design statistics: - Minimum period: 4.952ns{1} (Maximum frequency: 201.939MHz) - - -------------------------------------Footnotes----------------------------------- -1) The minimum period statistic assumes all single cycle delays. - -Analysis completed Wed Jul 17 15:21:24 2013 --------------------------------------------------------------------------------- - -Trace Settings: -------------------------- -Trace Settings - -Peak Memory Usage: 873 MB - - - Index: aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.syr =================================================================== --- aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.syr (revision 2) +++ aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.syr (nonexistent) @@ -1,524 +0,0 @@ -Release 12.1 - xst M.53d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. ---> Parameter TMPDIR set to xst/projnav.tmp - - -Total REAL time to Xst completion: 1.00 secs -Total CPU time to Xst completion: 0.15 secs - ---> Parameter xsthdpdir set to xst - - -Total REAL time to Xst completion: 1.00 secs -Total CPU time to Xst completion: 0.15 secs - ---> Reading design: Top_PipelinedCipher.prj - -TABLE OF CONTENTS - 1) Synthesis Options Summary - 2) HDL Parsing - 3) HDL Elaboration - 4) HDL Synthesis - 4.1) HDL Synthesis Report - 5) Advanced HDL Synthesis - 5.1) Advanced HDL Synthesis Report - 6) Low Level Synthesis - 7) Partition Report - 8) Design Summary - 8.1) Primitive and Black Box Usage - 8.2) Device utilization summary - 8.3) Partition Resource Summary - 8.4) Timing Report - 8.4.1) Clock Information - 8.4.2) Asynchronous Control Signals Information - 8.4.3) Timing Summary - 8.4.4) Timing Details - - -========================================================================= -* Synthesis Options Summary * -========================================================================= ----- Source Parameters -Input File Name : "Top_PipelinedCipher.prj" -Input Format : mixed -Ignore Synthesis Constraint File : NO - ----- Target Parameters -Output File Name : "Top_PipelinedCipher" -Output Format : NGC -Target Device : xc6vcx240t-2-ff784 - ----- Source Options -Top Module Name : Top_PipelinedCipher -Automatic FSM Extraction : YES -FSM Encoding Algorithm : Auto -Safe Implementation : No -FSM Style : lut -RAM Extraction : Yes -RAM Style : Auto -ROM Extraction : Yes -Shift Register Extraction : YES -ROM Style : Auto -Resource Sharing : YES -Asynchronous To Synchronous : NO -Shift Register Minimum Size : 2 -Use DSP Block : auto -Automatic Register Balancing : No - ----- Target Options -LUT Combining : auto -Reduce Control Sets : auto -Add IO Buffers : YES -Global Maximum Fanout : 100000 -Add Generic Clock Buffer(BUFG) : 32 -Register Duplication : YES -Optimize Instantiated Primitives : NO -Use Clock Enable : Auto -Use Synchronous Set : Auto -Use Synchronous Reset : Auto -Pack IO Registers into IOBs : auto -Equivalent register Removal : YES - ----- General Options -Optimization Goal : Speed -Optimization Effort : 1 -Power Reduction : NO -Library Search Order : Top_PipelinedCipher.lso -Keep Hierarchy : NO -Netlist Hierarchy : as_optimized -RTL Output : Yes -Global Optimization : AllClockNets -Read Cores : YES -Write Timing Constraints : NO -Cross Clock Analysis : NO -Hierarchy Separator : / -Bus Delimiter : <> -Case Specifier : maintain -Slice Utilization Ratio : 100 -BRAM Utilization Ratio : 100 -DSP48 Utilization Ratio : 100 -Auto BRAM Packing : NO -Slice Utilization Ratio Delta : 5 - -========================================================================= - - -========================================================================= -* HDL Parsing * -========================================================================= -Parsing Verilog file "E:\AES\AES\SBox.v" into library work -Parsing module . -Parsing Verilog file "E:\AES\AES\SubBytes.v" into library work -Parsing module . -Parsing Verilog file "E:\AES\AES\ShiftRows.v" into library work -Parsing module . -Parsing Verilog file "E:\AES\AES\RoundKeyGen.v" into library work -Parsing module . -Parsing Verilog file "E:\AES\AES\MixColumns.v" into library work -Parsing module . -Parsing Verilog file "E:\AES\AES\AddRoundKey.v" into library work -Parsing module . -Parsing Verilog file "E:\AES\AES\Round.v" into library work -Parsing module . -Parsing Verilog file "E:\AES\AES\KeyExpantion.v" into library work -Parsing module . -Parsing Verilog file "E:\AES\AES\Top_PipelinedCipher.v" into library work -Parsing module . - -========================================================================= -* HDL Elaboration * -========================================================================= - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -Elaborating module . - -========================================================================= -* HDL Synthesis * -========================================================================= - -Synthesizing Unit . - Related source file is "e:/aes/aes/top_pipelinedcipher.v". - DATA_W = 128 - KEY_L = 128 - NO_ROUNDS = 10 - Found 128-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 129 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/keyexpantion.v". - DATA_W = 128 - KEY_L = 128 - NO_ROUNDS = 10 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/roundkeygen.v". - KEY_L = 128 - WORD = 32 - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 128-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 515 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/subbytes.v". - DATA_W = 32 - NO_BYTES = 4 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/sbox.v". - Found 8-bit register for signal . - Found 256x8-bit Read Only RAM for signal - Summary: - inferred 1 RAM(s). - inferred 8 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/addroundkey.v". - DATA_W = 128 - Found 128-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 129 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/round.v". - DATA_W = 128 - Summary: - no macro. -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/subbytes.v". - DATA_W = 128 - NO_BYTES = 16 - Found 1-bit register for signal . - Summary: - inferred 1 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/shiftrows.v". - DATA_W = 128 - Found 128-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 129 D-type flip-flop(s). -Unit synthesized. - -Synthesizing Unit . - Related source file is "e:/aes/aes/mixcolumns.v". - DATA_W = 128 - Found 128-bit register for signal . - Found 1-bit register for signal . - Summary: - inferred 129 D-type flip-flop(s). - inferred 16 Multiplexer(s). -Unit synthesized. - -========================================================================= -HDL Synthesis Report - -Macro Statistics -# RAMs : 200 - 256x8-bit single-port Read Only RAM : 200 -# Registers : 352 - 1-bit register : 81 - 128-bit register : 71 - 8-bit register : 200 -# Multiplexers : 144 - 8-bit 2-to-1 multiplexer : 144 -# Xors : 349 - 128-bit xor2 : 11 - 32-bit xor2 : 50 - 8-bit xor2 : 144 - 8-bit xor5 : 144 - -========================================================================= - -========================================================================= -* Advanced HDL Synthesis * -========================================================================= - - -Synthesizing (advanced) Unit . -INFO:Xst:3030 - HDL ADVISOR - Register currently described with an asynchronous reset, could be combined with distributed RAM for implementation on block RAM resources if you made this reset synchronous instead. - ----------------------------------------------------------------------- - | ram_type | Distributed | | - ----------------------------------------------------------------------- - | Port A | - | aspect ratio | 256-word x 8-bit | | - | weA | connected to signal | high | - | addrA | connected to signal | | - | diA | connected to signal | | - | doA | connected to internal node | | - ----------------------------------------------------------------------- -INFO:Xst:3031 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines. -Unit synthesized (advanced). - -========================================================================= -Advanced HDL Synthesis Report - -Macro Statistics -# RAMs : 200 - 256x8-bit single-port distributed Read Only RAM : 200 -# Registers : 10769 - Flip-Flops : 10769 -# Multiplexers : 144 - 8-bit 2-to-1 multiplexer : 144 -# Xors : 349 - 128-bit xor2 : 11 - 32-bit xor2 : 50 - 8-bit xor2 : 144 - 8-bit xor5 : 144 - -========================================================================= - -========================================================================= -* Low Level Synthesis * -========================================================================= - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Optimizing unit ... - -Mapping all equations... -Building and optimizing final netlist ... -Found area constraint ratio of 100 (+ 5) on block Top_PipelinedCipher, actual ratio is 12. - -Final Macro Processing ... - -========================================================================= -Final Register Report - -Macro Statistics -# Registers : 10769 - Flip-Flops : 10769 - -========================================================================= - -========================================================================= -* Partition Report * -========================================================================= - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -========================================================================= -* Design Summary * -========================================================================= - -Top Level Output File Name : Top_PipelinedCipher.ngc - -Primitive and Black Box Usage: ------------------------------- -# BELS : 15403 -# INV : 1 -# LUT2 : 810 -# LUT3 : 320 -# LUT4 : 1600 -# LUT5 : 1040 -# LUT6 : 6832 -# MUXF7 : 3200 -# MUXF8 : 1600 -# FlipFlops/Latches : 10769 -# FDC : 81 -# FDCE : 10688 -# Clock Buffers : 2 -# BUFG : 1 -# BUFGP : 1 -# IO Buffers : 388 -# IBUF : 259 -# OBUF : 129 - -Device utilization summary: ---------------------------- - -Selected Device : 6vcx240tff784-2 - - -Slice Logic Utilization: - Number of Slice Registers: 10769 out of 301440 3% - Number of Slice LUTs: 10603 out of 150720 7% - Number used as Logic: 10603 out of 150720 7% - -Slice Logic Distribution: - Number of LUT Flip Flop pairs used: 15921 - Number with an unused Flip Flop: 5152 out of 15921 32% - Number with an unused LUT: 5318 out of 15921 33% - Number of fully used LUT-FF pairs: 5451 out of 15921 34% - Number of unique control sets: 82 - -IO Utilization: - Number of IOs: 389 - Number of bonded IOBs: 389 out of 400 97% - -Specific Feature Utilization: - Number of BUFG/BUFGCTRLs: 2 out of 32 6% - ---------------------------- -Partition Resource Summary: ---------------------------- - - No Partitions were found in this design. - ---------------------------- - - -========================================================================= -Timing Report - -NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. - FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT - GENERATED AFTER PLACE-and-ROUTE. - -Clock Information: ------------------- ------------------------------------+------------------------+-------+ -Clock Signal | Clock buffer(FF name) | Load | ------------------------------------+------------------------+-------+ -clk | BUFGP | 10769 | ------------------------------------+------------------------+-------+ - -Asynchronous Control Signals Information: ----------------------------------------- -No asynchronous control signals found in this design - -Timing Summary: ---------------- -Speed Grade: -2 - - Minimum period: 1.564ns (Maximum Frequency: 639.391MHz) - Minimum input arrival time before clock: 1.252ns - Maximum output required time after clock: 0.664ns - Maximum combinational path delay: No path found - -Timing Details: ---------------- -All values displayed in nanoseconds (ns) - -========================================================================= -Timing constraint: Default period analysis for Clock 'clk' - Clock period: 1.564ns (frequency: 639.391MHz) - Total number of paths / destination ports: 75065 / 20943 -------------------------------------------------------------------------- -Delay: 1.564ns (Levels of Logic = 3) - Source: U_KEYEXP/RKGEN_U0/Key_FirstStage_24 (FF) - Destination: U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_7 (FF) - Source Clock: clk rising - Destination Clock: clk rising - - Data Path: U_KEYEXP/RKGEN_U0/Key_FirstStage_24 to U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_7 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDCE:C->Q 33 0.317 0.826 U_KEYEXP/RKGEN_U0/Key_FirstStage_24 (U_KEYEXP/RKGEN_U0/Key_FirstStage_24) - LUT6:I0->O 1 0.061 0.000 U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT23 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT23) - MUXF7:I1->O 1 0.211 0.000 U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f7_0 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f71) - MUXF8:I0->O 1 0.149 0.000 U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM_Mram_addr[7]_GND_5_o_wide_mux_0_OUT2_f8 (U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/addr[7]_GND_5_o_wide_mux_0_OUT<1>) - FDCE:D -0.002 U_KEYEXP/RKGEN_U0/SUB_U/ROM[0].ROM/dout_1 - ---------------------------------------- - Total 1.564ns (0.738ns logic, 0.826ns route) - (47.2% logic, 52.8% route) - -========================================================================= -Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' - Total number of paths / destination ports: 771 / 514 -------------------------------------------------------------------------- -Offset: 1.252ns (Levels of Logic = 2) - Source: cipherkey_valid_in (PAD) - Destination: U0_ARK/data_out_127 (FF) - Destination Clock: clk rising - - Data Path: cipherkey_valid_in to U0_ARK/data_out_127 - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - IBUF:I->O 130 0.003 0.505 cipherkey_valid_in_IBUF (cipherkey_valid_in_IBUF) - LUT2:I1->O 129 0.061 0.487 U0_ARK/data_valid_in_key_valid_in_AND_2_o1 (U0_ARK/data_valid_in_key_valid_in_AND_2_o) - FDCE:CE 0.196 U0_ARK/data_out_0 - ---------------------------------------- - Total 1.252ns (0.260ns logic, 0.992ns route) - (20.8% logic, 79.2% route) - -========================================================================= -Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' - Total number of paths / destination ports: 129 / 129 -------------------------------------------------------------------------- -Offset: 0.664ns (Levels of Logic = 1) - Source: U_KEY/data_out_127 (FF) - Destination: cipher_text<127> (PAD) - Source Clock: clk rising - - Data Path: U_KEY/data_out_127 to cipher_text<127> - Gate Net - Cell:in->out fanout Delay Delay Logical Name (Net Name) - ---------------------------------------- ------------ - FDCE:C->Q 2 0.317 0.344 U_KEY/data_out_127 (U_KEY/data_out_127) - OBUF:I->O 0.003 cipher_text_127_OBUF (cipher_text<127>) - ---------------------------------------- - Total 0.664ns (0.320ns logic, 0.344ns route) - (48.2% logic, 51.8% route) - -========================================================================= - - -Total REAL time to Xst completion: 106.00 secs -Total CPU time to Xst completion: 105.60 secs - ---> - -Total memory usage is 397192 kilobytes - -Number of errors : 0 ( 0 filtered) -Number of warnings : 0 ( 0 filtered) -Number of infos : 2 ( 0 filtered) - Index: aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.par =================================================================== --- aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.par (revision 2) +++ aes-128_pipelined_encryption/tags/R0/reports/Top_PipelinedCipher.par (nonexistent) @@ -1,190 +0,0 @@ -Release 12.1 par M.53d (nt64) -Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. - -AMRSALAH-PC:: Wed Jul 17 15:17:40 2013 - -par -w -intstyle ise -ol high Top_PipelinedCipher_map.ncd -Top_PipelinedCipher.ncd Top_PipelinedCipher.pcf - - -Constraints file: Top_PipelinedCipher.pcf. -Loading device for application Rf_Device from file '6vcx240t.nph' in environment E:\ISE12\ISE_DS\ISE. - "Top_PipelinedCipher" is an NCD, version 3.2, device xc6vcx240t, package ff784, speed -2 -vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv -INFO:Security:56 - Part 'xc6vcx240t' is not a WebPack part. -WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue -to function, but you no longer qualify for Xilinx software updates or new releases. - ----------------------------------------------------------------------- - -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) -Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts) - - -Device speed data version: "PRELIMINARY 1.04 2010-04-09". - - - -Device Utilization Summary: - -Slice Logic Utilization: - Number of Slice Registers: 10,769 out of 301,440 3% - Number used as Flip Flops: 10,769 - Number used as Latches: 0 - Number used as Latch-thrus: 0 - Number used as AND/OR logics: 0 - Number of Slice LUTs: 12,475 out of 150,720 8% - Number used as logic: 9,842 out of 150,720 6% - Number using O6 output only: 9,081 - Number using O5 output only: 0 - Number using O5 and O6: 761 - Number used as ROM: 0 - Number used as Memory: 0 out of 58,400 0% - Number used exclusively as route-thrus: 2,633 - Number with same-slice register load: 2,633 - Number with same-slice carry load: 0 - Number with other load: 0 - -Slice Logic Distribution: - Number of occupied Slices: 3,214 out of 37,680 8% - Number of LUT Flip Flop pairs used: 12,527 - Number with an unused Flip Flop: 5,031 out of 12,527 40% - Number with an unused LUT: 52 out of 12,527 1% - Number of fully used LUT-FF pairs: 7,444 out of 12,527 59% - Number of slice register sites lost - to control set restrictions: 0 out of 301,440 0% - - A LUT Flip Flop pair for this architecture represents one LUT paired with - one Flip Flop within a slice. A control set is a unique combination of - clock, reset, set, and enable signals for a registered element. - The Slice Logic Distribution report is not meaningful if the design is - over-mapped for a non-slice resource or if Placement fails. - OVERMAPPING of BRAM resources should be ignored if the design is - over-mapped for a non-BRAM resource or if placement fails. - -IO Utilization: - Number of bonded IOBs: 389 out of 400 97% - -Specific Feature Utilization: - Number of RAMB36E1/FIFO36E1s: 0 out of 416 0% - Number of RAMB18E1/FIFO18E1s: 0 out of 832 0% - Number of BUFG/BUFGCTRLs: 2 out of 32 6% - Number used as BUFGs: 2 - Number used as BUFGCTRLs: 0 - Number of ILOGICE1/ISERDESE1s: 0 out of 720 0% - Number of OLOGICE1/OSERDESE1s: 0 out of 720 0% - Number of BSCANs: 0 out of 4 0% - Number of BUFHCEs: 0 out of 144 0% - Number of BUFIODQSs: 0 out of 72 0% - Number of BUFRs: 0 out of 36 0% - Number of CAPTUREs: 0 out of 1 0% - Number of DSP48E1s: 0 out of 768 0% - Number of EFUSE_USRs: 0 out of 1 0% - Number of GTXE1s: 0 out of 12 0% - Number of IBUFDS_GTXE1s: 0 out of 8 0% - Number of ICAPs: 0 out of 2 0% - Number of IDELAYCTRLs: 0 out of 18 0% - Number of IODELAYE1s: 0 out of 720 0% - Number of MMCM_ADVs: 0 out of 12 0% - Number of PCIE_2_0s: 0 out of 2 0% - Number of STARTUPs: 1 out of 1 100% - Number of SYSMONs: 0 out of 1 0% - Number of TEMAC_SINGLEs: 0 out of 1 0% - - -Overall effort level (-ol): High -Router effort level (-rl): High - -Starting initial Timing Analysis. REAL time: 35 secs -Finished initial Timing Analysis. REAL time: 36 secs - -Starting Router - - -Phase 1 : 77964 unrouted; REAL time: 42 secs - -Phase 2 : 70512 unrouted; REAL time: 54 secs - -Phase 3 : 26862 unrouted; REAL time: 1 mins 44 secs - -Phase 4 : 26860 unrouted; (Setup:0, Hold:1, Component Switching Limit:0) REAL time: 1 mins 56 secs - -Updating file: Top_PipelinedCipher.ncd with current fully routed design. - -Phase 5 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs - -Phase 6 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs - -Phase 7 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs - -Phase 8 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs - -Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 30 secs - -Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 38 secs -Total REAL time to Router completion: 2 mins 38 secs -Total CPU time to Router completion: 2 mins 42 secs - -Partition Implementation Status -------------------------------- - - No Partitions were found in this design. - -------------------------------- - -Generating "PAR" statistics. - -************************** -Generating Clock Report -************************** - -+---------------------+--------------+------+------+------------+-------------+ -| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| -+---------------------+--------------+------+------+------------+-------------+ -| clk_BUFGP | BUFGCTRL_X0Y0| No | 3213 | 0.252 | 1.834 | -+---------------------+--------------+------+------+------------+-------------+ - -* Net Skew is the difference between the minimum and maximum routing -only delays for the net. Note this is different from Clock Skew which -is reported in TRCE timing report. Clock Skew is the difference between -the minimum and maximum path delays which includes logic delays. - -Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) - -Asterisk (*) preceding a constraint indicates it was not met. - This may be due to a setup or hold violation. - ----------------------------------------------------------------------------------------------------------- - Constraint | Check | Worst Case | Best Case | Timing | Timing - | | Slack | Achievable | Errors | Score ----------------------------------------------------------------------------------------------------------- - TS_clk = PERIOD TIMEGRP "clk" 5 ns HIGH 5 | SETUP | 0.048ns| 4.952ns| 0| 0 - 0% | HOLD | 0.006ns| | 0| 0 ----------------------------------------------------------------------------------------------------------- - - -All constraints were met. - - -Generating Pad Report. - -All signals are completely routed. - -Total REAL time to PAR completion: 2 mins 46 secs -Total CPU time to PAR completion: 2 mins 49 secs - -Peak Memory Usage: 1113 MB - -Placer: Placement generated during map. -Routing: Completed - No errors found. -Timing: Completed - No errors found. - -Number of error messages: 0 -Number of warning messages: 0 -Number of info messages: 0 - -Writing design to file Top_PipelinedCipher.ncd - - - -PAR done! Index: aes-128_pipelined_encryption/tags/R0/rtl/Top_PipelinedCipher.v =================================================================== --- aes-128_pipelined_encryption/tags/R0/rtl/Top_PipelinedCipher.v (revision 2) +++ aes-128_pipelined_encryption/tags/R0/rtl/Top_PipelinedCipher.v (nonexistent) @@ -1,82 +0,0 @@ -/* -Project : AES -Standard doc. : FIPS 197 -Module name : Top_AES_PipelinedCipher -Dependancy : -Design doc. : -References : -Description : this is the top module of the design which forms - rounds and connects KeyExpantion using pipelined - architecture -Owner : Amr Salah -*/ - - -`timescale 1 ns/1 ps - -module Top_PipelinedCipher -# -( -parameter DATA_W = 128, //data width -parameter KEY_L = 128, //key length -parameter NO_ROUNDS = 10 //number of rounds -) - -( -input clk, //system clock -input reset, //asynch reset -input data_valid_in, //data valid signal -input cipherkey_valid_in, //cipher key valid signal -input [KEY_L-1:0] cipher_key, //cipher key -input [DATA_W-1:0] plain_text, //plain text -output valid_out, //output valid signal -output [DATA_W-1:0] cipher_text //cipher text -); - -wire [NO_ROUNDS-1:0] valid_round_key; //all round keys valid signals KeyExpantion output -wire [NO_ROUNDS-1:0] valid_round_data; //all rounds ouput data valid signals -wire [DATA_W-1:0] data_round [0:NO_ROUNDS-1]; //all rounds data -wire valid_sub2shift; //for final round connection -wire valid_shift2key; // -wire [DATA_W-1:0]data_sub2shift; // -wire [DATA_W-1:0]data_shift2key; // -wire [(NO_ROUNDS*DATA_W)-1:0] W; //all round keys - -reg[DATA_W-1:0] data_shift2key_delayed; //for delay register -reg valid_shift2key_delayed; - -//instantiate Key Expantion which will feed every round with round key -KeyExpantion #(DATA_W,KEY_L,NO_ROUNDS) U_KEYEXP(clk,reset,cipherkey_valid_in,cipher_key,W,valid_round_key); - -//due to algorithm,first cipher key will be xored witht plain text -AddRoundKey #(DATA_W)U0_ARK(clk,reset,data_valid_in,cipherkey_valid_in,plain_text,cipher_key,valid_round_data[0],data_round[0]); - -//instantiate all rounds , connect them with key expantion -genvar i; -generate -for(i=0;i> 3 //no of bytes = data width / 8 -) -( -input clk, //system clock -input reset, //asynch active low reset -input valid_in, //input valid signal -input [DATA_W-1:0] data_in, //input data -output reg valid_out, //output valid signal -output [DATA_W-1:0] data_out //output data -) -; - -genvar i; -generate //generating sbox roms -for (i=0; i< NO_BYTES ; i=i+1) begin : ROM - SBox ROM(clk,reset,valid_in,data_in[(i*8)+7:(i*8)],data_out[(i*8)+7:(i*8)]); -end -endgenerate - -always@(posedge clk or negedge reset) //valid out register -if(!reset)begin - valid_out <= 1'b0; -end else begin - valid_out <= valid_in; - end -endmodule - - - -

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