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Subversion Repositories amber

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  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw/fpga
    from Rev 63 to Rev 64
    ↔ Reverse comparison
  •

Rev 63 → Rev 64

/bin/xs6_constraints.ucf
59,12 → 59,30
TIMESPEC "TS_MRX_CLK" = PERIOD "MRX_CLK" 40.0 ns HIGH 50 %;
 
# False paths between clocks
PIN "u_mcb_ddr3/memc3_infrastructure_inst/u_pll_adv.CLKOUT3" TNM = "DDR_CLK";
PIN "u_clocks_resets/u_pll_adv.CLKOUT2" TNM = "SYS_CLK";
PIN "u_ddr3/memc3_infrastructure_inst/u_pll_adv.CLKOUT3" TNM = "DDR_CLK";
PIN "u_clocks_resets/u_pll_adv.CLKOUT2" TNM = "CLKOUT2";
TIMESPEC "TS_false2" = FROM "DDR_CLK" TO "CLKOUT2" TIG;
 
TIMESPEC "TS_false1" = FROM "DDR_CLK" TO "SYS_CLK" TIG;
 
############################################################################
# DDR2 requires the MCB to operate in Extended performance mode with higher Vccint
# specification to achieve maximum frequency. Therefore, the following CONFIG constraint
# follows the corresponding GUI option setting. However, DDR3 can operate at higher
# frequencies with any Vcciint value by operating MCB in extended mode. Please do not
# remove/edit the below constraint to avoid false errors.
############################################################################
CONFIG MCB_PERFORMANCE= EXTENDED;
 
 
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
NET "u_ddr3/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "u_ddr3/c?_pll_lock" TIG;
INST "u_ddr3/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
 
 
 
############################################################################
## I/O TERMINATION
############################################################################
91,7 → 109,7
NET "ddr3_reset_n" IOSTANDARD = SSTL15_II;
NET "ddr3_dm[*]" IOSTANDARD = SSTL15_II;
NET "mcb3_rzq" IOSTANDARD = SSTL15_II;
NET "mcb3_zio" IOSTANDARD = SSTL15_II;
#NET "mcb3_zio" IOSTANDARD = SSTL15_II;
NET "brd_clk_p" IOSTANDARD = LVDS_25;
NET "brd_clk_n" IOSTANDARD = LVDS_25;
NET "brd_rst" IOSTANDARD = LVCMOS15;
181,7 → 199,7
 
# The following pins are available for used as RZQ or ZIO pins#
NET "mcb3_rzq" LOC = "K7" ;
NET "mcb3_zio" LOC = "R7" ;
#NET "mcb3_zio" LOC = "R7" ;
 
############################################################################
# Ethernet MII MAC to PHY interface
/bin/xs6_source_files.prj
119,11 → 119,12
verilog work ../../vlog/lib/xs6_sram_1024x128_byte_en.v
 
# Xilinx Spartan-6 DDR3 I/F
verilog work ../../vlog/xs6_ddr3/mcb_ddr3.v
verilog work ../../vlog/xs6_ddr3/ddr3.v
verilog work ../../vlog/xs6_ddr3/iodrp_controller.v
verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v
verilog work ../../vlog/xs6_ddr3/mcb_raw_wrapper.v
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration_top.v
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration.v
verilog work ../../vlog/xs6_ddr3/memc3_infrastructure.v
verilog work ../../vlog/xs6_ddr3/memc3_wrapper.v
verilog work ../../vlog/xs6_ddr3/mcb_ui_top.v
verilog work ../../vlog/xs6_ddr3/infrastructure.v
verilog work ../../vlog/xs6_ddr3/memc_wrapper.v
/bin/Makefile
64,7 → 64,7
BOOT_LOADER_DEF =
endif
 
VERILOG_INCLUDE_PATH = ../../vlog/lib $(BOOT_LOADER_DIR)
VERILOG_INCLUDE_PATH = ../../vlog/lib ../../vlog/tb $(BOOT_LOADER_DIR)
 
# Name of top level verilog file (must be the same as its module name)
RTL_TOP = system

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