URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
Compare Revisions
- This comparison shows the changes necessary to convert path
/amber/trunk/hw/tests
- from Rev 17 to Rev 20
- ↔ Reverse comparison
Rev 17 → Rev 20
/timeouts.txt
1,59 → 1,60
flow4 3936 |
tmp 3396 |
add 1740 |
adc 1380 |
sub 1560 |
sbc 2676 |
barrel_shift 1560 |
barrel_shift_rs 1380 |
change_sbits 2340 |
change_mode 1692 |
bl 1572 |
bcc 1200 |
ldr 4432 |
ldr_str_pc 1612 |
strb 2288 |
ldm1 2628 |
ldm2 2052 |
ldm3 1868 |
ldm4 1856 |
stm1 7588 |
stm2 2440 |
ldm_stm_onetwo 4840 |
stm_stream 52276 |
mul 186960 |
mla 377424 |
swp 2084 |
irq 103828 |
firq 30540 |
swi 1620 |
undefined_ins 2748 |
addr_ex 1772 |
irq_stm 10220 |
cache1 16308 |
cache2 1460 |
cache3 106064 |
cache_swap 69276 |
cacheable_area 5952 |
cache_flush 18408 |
flow1 2976 |
flow2 4960 |
flow3 3348 |
hiboot_mem 1424 |
ddr31 102880 |
ddr32 205992 |
ddr33 21792 |
ethmac_reg 4776 |
ethmac_mem 75844 |
ethmac_tx 18172 |
uart_reg 1824 |
uart_tx 136588 |
uart_rx 132384 |
uart_rxint 127204 |
bic_bug 1524 |
movs_bug 1592 |
flow_bug 1500 |
mlas_bug 1996 |
inflate_bug 1420 |
swp_lock_bug 1368 |
cache_swap_bug 29620 |
tmp 3376 |
add 1704 |
adc 1368 |
sub 1500 |
sbc 2484 |
barrel_shift 1524 |
barrel_shift_rs 1368 |
change_sbits 2184 |
change_mode 1656 |
bl 1548 |
bcc 1188 |
ldr 4000 |
ldr_str_pc 1564 |
strb 2120 |
ldm1 2544 |
ldm2 2016 |
ldm3 1832 |
ldm4 1820 |
stm1 7024 |
stm2 2296 |
ldm_stm_onetwo 4748 |
stm_stream 49188 |
mul 177660 |
mla 365076 |
swp 2004 |
irq 97644 |
firq 28764 |
swi 1596 |
undefined_ins 2616 |
addr_ex 1724 |
irq_stm 9812 |
cache1 16296 |
cache2 1456 |
cache3 98884 |
cache_swap 66196 |
cacheable_area 5580 |
cache_flush 17572 |
flow1 2972 |
flow2 4800 |
flow3 3292 |
hiboot_mem 1376 |
ddr31 96676 |
ddr32 193584 |
ddr33 20820 |
ethmac_reg 4596 |
ethmac_mem 75708 |
ethmac_tx 16692 |
uart_reg 1800 |
uart_tx 137764 |
uart_rx 132024 |
uart_rxint 125032 |
bic_bug 1512 |
movs_bug 1532 |
flow_bug 1428 |
mlas_bug 1948 |
inflate_bug 1360 |
swp_lock_bug 1320 |
cache_swap_bug 29504 |
conflict_rd 2552 |
/conflict_rd.S
0,0 → 1,127
/***************************************************************** |
// // |
// Amber 2 Core Instruction Test // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Tests that a register conflict between a ldr and a regop // |
// that changes the value of the same register is handled // |
// correctly. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
*****************************************************************/ |
|
#include "amber_registers.h" |
|
.section .text |
.globl main |
main: |
|
@ Run through the test 4 times |
@ 1 - cache off |
@ 2 - cache on but empty |
@ 3 - cache on and loaded |
@ 4 - same as 3 |
|
mov r10, #40 |
|
1: mov r1, #1 |
mov r2, #2 |
mov r3, #3 |
mov r4, #4 |
mov r5, #0x1000 |
mov r6, #6 |
str r6, [r5] |
mov sp, #0x800 |
|
@ -------------------------- |
tst r3, #1 |
add r0, r6, r4 |
ldr r1, Data1 |
ldr r3, Data2 |
ldr r2, Data3 |
movne r2, r3 @ always executed |
ldr r3, [r5] |
|
bl 2f |
|
nop |
nop |
nop |
|
2: stmdb sp!, {r1, r2, r3} |
|
nop |
nop |
|
ldr r8, [sp, #4] |
ldr r9, Data2 |
cmp r8, r9 |
addne r10, #1 |
bne testfail |
|
@ --------------------- |
@ Enable the cache |
@ --------------------- |
mvn r0, #0 |
mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area |
mov r0, #1 |
mcr 15, 0, r0, cr2, cr0, 0 @ cache enable |
|
subs r10, r10, #10 |
bne 1b |
|
b testpass |
|
testfail: |
ldr r11, AdrTestStatus |
str r10, [r11] |
b testfail |
|
testpass: |
ldr r11, AdrTestStatus |
mov r10, #17 |
str r10, [r11] |
b testpass |
|
|
/* Write 17 to this address to generate a Test Passed message */ |
AdrTestStatus: .word ADR_AMBER_TEST_STATUS |
AdrHiBootBase: .word ADR_HIBOOT_BASE |
|
Data1: .word 0x1000 |
Data2: .word 0x2000 |
Data3: .word 0x3000 |
|
/* ========================================================================= */ |
/* ========================================================================= */ |
|