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URL https://opencores.org/ocsvn/amber/amber/trunk

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  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw/vlog/amber25
    from Rev 36 to Rev 39
    ↔ Reverse comparison
  •

Rev 36 → Rev 39

/a25_dcache.v
117,16 → 117,13
localparam [3:0] CS_INIT = 4'd0,
CS_IDLE = 4'd1,
CS_FILL0 = 4'd2,
CS_FILL1 = 4'd3,
CS_FILL2 = 4'd4,
CS_FILL3 = 4'd5,
CS_FILL_COMPLETE = 4'd6,
CS_TURN_AROUND = 4'd7,
CS_WRITE_HIT1 = 4'd8,
CS_WRITE_HIT_WAIT_WB = 4'd8,
CS_WRITE_MISS_WAIT_WB = 4'd9,
CS_EX_DELETE = 4'd10;
CS_FILL = 4'd2,
CS_FILL_COMPLETE = 4'd3,
CS_TURN_AROUND = 4'd4,
CS_WRITE_HIT = 4'd5,
CS_WRITE_HIT_WAIT_WB = 4'd6,
CS_WRITE_MISS_WAIT_WB = 4'd7,
CS_EX_DELETE = 4'd8;
 
reg [3:0] c_state = CS_IDLE;
266,11 → 263,11
source_sel <= 1'd1 << C_INVA;
end
else if ( read_miss )
c_state <= CS_FILL3;
c_state <= CS_FILL;
else if ( write_hit )
begin
if ( i_wb_cached_ready )
c_state <= CS_WRITE_HIT1;
c_state <= CS_WRITE_HIT;
else
c_state <= CS_WRITE_HIT_WAIT_WB;
end
279,7 → 276,7
end
CS_FILL3 :
CS_FILL :
// third read of burst of 4
// wb read request asserted, wait for ack
if ( i_wb_cached_ready )
329,7 → 326,7
end
CS_WRITE_HIT1:
CS_WRITE_HIT:
if ( !consecutive_write )
c_state <= CS_IDLE;
 
378,7 → 375,7
 
assign consecutive_write = miss_address[31:4] == i_address[31:4] &&
i_write_enable &&
c_state == CS_WRITE_HIT1 &&
c_state == CS_WRITE_HIT &&
request_pulse;
 
 
388,7 → 385,7
else if ( i_wb_cached_ready && fill_state )
wb_address <= {wb_address[31:4], wb_address[3:2] + 1'd1, 2'd0};
assign fill_state = c_state == CS_FILL0 || c_state == CS_FILL1 || c_state == CS_FILL2 || c_state == CS_FILL3 ;
assign fill_state = c_state == CS_FILL ;
assign wb_hit = i_address == wb_address && i_wb_cached_ready && fill_state;
 
 
531,7 → 528,7
// Need to stall for a write miss to wait for the current wb
// read miss access to complete. Also for a write idle_hit, need
// to stall for 1 cycle while the data cache is being written to
assign write_state = c_state == CS_IDLE || c_state == CS_WRITE_HIT1 ||
assign write_state = c_state == CS_IDLE || c_state == CS_WRITE_HIT ||
c_state == CS_WRITE_HIT_WAIT_WB || c_state == CS_WRITE_MISS_WAIT_WB;
assign write_stall = (write_miss && !(i_wb_cached_ready && write_state)) || (write_hit && !i_wb_cached_ready);
540,7 → 537,7
 
assign cache_busy_stall = c_state == CS_FILL_COMPLETE || c_state == CS_TURN_AROUND || c_state == CS_INIT ||
(fill_state && !rbuf_hit && !wb_hit) ||
(c_state == CS_WRITE_HIT1 && !consecutive_write);
(c_state == CS_WRITE_HIT && !consecutive_write);
 
 
// ======================================
872,18 → 869,15
source_sel[C_INVA] ? "C_INVA" :
"UNKNON" ;
assign xC_STATE = c_state == CS_INIT ? "CS_INIT" :
c_state == CS_IDLE ? "CS_IDLE" :
c_state == CS_FILL0 ? "CS_FILL0" :
c_state == CS_FILL1 ? "CS_FILL1" :
c_state == CS_FILL2 ? "CS_FILL2" :
c_state == CS_FILL3 ? "CS_FILL3" :
c_state == CS_FILL_COMPLETE ? "CS_FILL_COMPLETE" :
c_state == CS_EX_DELETE ? "CS_EX_DELETE" :
c_state == CS_TURN_AROUND ? "CS_TURN_AROUND" :
c_state == CS_WRITE_HIT1 ? "CS_WRITE_HIT1" :
c_state == CS_WRITE_HIT_WAIT_WB ? "CS_WRITE_HIT_WAIT_WB" :
c_state == CS_WRITE_MISS_WAIT_WB ? "CS_WRITE_MISS_WAIT_WB" :
assign xC_STATE = c_state == CS_INIT ? "INIT" :
c_state == CS_IDLE ? "IDLE" :
c_state == CS_FILL ? "FILL" :
c_state == CS_FILL_COMPLETE ? "FILL_COMPLETE" :
c_state == CS_EX_DELETE ? "EX_DELETE" :
c_state == CS_TURN_AROUND ? "TURN_AROUND" :
c_state == CS_WRITE_HIT ? "WRITE_HIT" :
c_state == CS_WRITE_HIT_WAIT_WB ? "WRITE_HIT_WAIT_WB" :
c_state == CS_WRITE_MISS_WAIT_WB ? "WRITE_MISS_WAIT_WB" :
"UNKNOWN" ;
 
 
/a25_wishbone_buf.v
59,7 → 59,7
input [15:0] i_be,
input [31:0] i_addr,
output [127:0] o_rdata,
output o_ready,
output o_ack,
 
// Wishbone side
output o_valid,
76,63 → 76,79
// ----------------------------------------------------
// Signals
// ----------------------------------------------------
reg wbuf_used_r = 'd0;
reg [127:0] wbuf_wdata_r;
reg [31:0] wbuf_addr_r;
reg [15:0] wbuf_be_r;
reg wbuf_write_r = 'd0;
wire in_wreq = i_req && i_write;
reg busy_reading_r = 'd0;
reg [1:0] wbuf_used_r = 'd0;
reg [127:0] wbuf_wdata_r [1:0];
reg [31:0] wbuf_addr_r [1:0];
reg [15:0] wbuf_be_r [1:0];
reg [1:0] wbuf_write_r = 'd0;
reg wbuf_wp_r = 'd0; // write buf write pointer
reg wbuf_rp_r = 'd0; // write buf read pointer
reg busy_reading_r = 'd0;
reg wait_rdata_valid_r = 'd0;
wire in_wreq;
reg ack_owed_r = 'd0;
 
 
// ----------------------------------------------------
// Access Buffer
// ----------------------------------------------------
assign in_wreq = i_req && i_write;
assign push = i_req && !busy_reading_r && (wbuf_used_r == 2'd1 || (wbuf_used_r == 2'd0 && !i_accepted));
assign pop = o_valid && i_accepted && wbuf_used_r != 2'd0;
 
always @(posedge i_clk)
if (i_req && !wbuf_used_r)
if (push && pop)
wbuf_used_r <= wbuf_used_r;
else if (push)
wbuf_used_r <= wbuf_used_r + 1'd1;
else if (pop)
wbuf_used_r <= wbuf_used_r - 1'd1;
 
always @(posedge i_clk)
if (push && in_wreq && !o_ack)
ack_owed_r = 1'd1;
else if (!i_req && o_ack)
ack_owed_r = 1'd0;
always @(posedge i_clk)
if (push)
begin
wbuf_used_r <= !i_accepted;
wbuf_wdata_r <= i_wdata;
wbuf_addr_r <= i_addr;
wbuf_be_r <= i_write ? i_be : 16'hffff;
wbuf_write_r <= i_write;
wbuf_wdata_r [wbuf_wp_r] <= i_wdata;
wbuf_addr_r [wbuf_wp_r] <= i_addr;
wbuf_be_r [wbuf_wp_r] <= i_write ? i_be : 16'hffff;
wbuf_write_r [wbuf_wp_r] <= i_write;
wbuf_wp_r <= !wbuf_wp_r;
end
else if ( i_req && wbuf_used_r && o_valid && i_accepted)
begin
wbuf_used_r <= 1'd1;
wbuf_wdata_r <= i_wdata;
wbuf_addr_r <= i_addr;
wbuf_be_r <= i_write ? i_be : 16'hffff;
wbuf_write_r <= i_write;
end
else if (o_valid && i_accepted && wbuf_write_r)
wbuf_used_r <= 1'd0;
else if (i_rdata_valid && !wbuf_write_r)
wbuf_used_r <= 1'd0;
 
always @(posedge i_clk)
if (pop)
wbuf_rp_r <= !wbuf_rp_r;
 
// ----------------------------------------------------
// Output logic
// ----------------------------------------------------
assign o_wdata = wbuf_used_r ? wbuf_wdata_r : i_wdata;
assign o_write = wbuf_used_r ? wbuf_write_r : i_write;
assign o_addr = wbuf_used_r ? wbuf_addr_r : i_addr;
assign o_be = wbuf_used_r ? wbuf_be_r : i_write ? i_be : 16'hffff;
assign o_wdata = wbuf_used_r != 2'd0 ? wbuf_wdata_r[wbuf_rp_r] : i_wdata;
assign o_write = wbuf_used_r != 2'd0 ? wbuf_write_r[wbuf_rp_r] : i_write;
assign o_addr = wbuf_used_r != 2'd0 ? wbuf_addr_r [wbuf_rp_r] : i_addr;
assign o_be = wbuf_used_r != 2'd0 ? wbuf_be_r [wbuf_rp_r] : i_write ? i_be : 16'hffff;
 
assign o_valid = (wbuf_used_r || i_req) && !busy_reading_r;
assign o_ack = (in_wreq ? (wbuf_used_r == 2'd0) : i_rdata_valid) || (ack_owed_r && pop);
assign o_valid = (wbuf_used_r != 2'd0 || i_req) && !wait_rdata_valid_r;
 
assign o_rdata = i_rdata;
assign o_ready = in_wreq ? (!wbuf_used_r || i_accepted) : i_rdata_valid;
 
 
always@(posedge i_clk)
if (o_valid && !o_write && i_accepted)
if (o_valid && !o_write)
busy_reading_r <= 1'd1;
else if (i_rdata_valid)
busy_reading_r <= 1'd0;
 
 
 
always@(posedge i_clk)
if (o_valid && !o_write && i_accepted)
wait_rdata_valid_r <= 1'd1;
else if (i_rdata_valid)
wait_rdata_valid_r <= 1'd0;
endmodule
 
 
/a25_wishbone.v
64,30 → 64,30
 
// Port 0 - dcache uncached
input i_port0_req,
output o_port0_ack,
input i_port0_write,
input [127:0] i_port0_wdata,
input [15:0] i_port0_be,
input [31:0] i_port0_addr,
output [127:0] o_port0_rdata,
output o_port0_ready,
 
// Port 1 - dcache cached
input i_port1_req,
output o_port1_ack,
input i_port1_write,
input [127:0] i_port1_wdata,
input [15:0] i_port1_be,
input [31:0] i_port1_addr,
output [127:0] o_port1_rdata,
output o_port1_ready,
 
// Port 2 - instruction cache accesses, read only
input i_port2_req,
output o_port2_ack,
input i_port2_write,
input [127:0] i_port2_wdata,
input [15:0] i_port2_be,
input [31:0] i_port2_addr,
output [127:0] o_port2_rdata,
output o_port2_ready,
 
 
// 128-bit Wishbone Bus
130,12 → 130,12
.i_clk ( i_clk ),
 
.i_req ( i_port0_req ),
.o_ack ( o_port0_ack ),
.i_write ( i_port0_write ),
.i_wdata ( i_port0_wdata ),
.i_be ( i_port0_be ),
.i_addr ( i_port0_addr ),
.o_rdata ( o_port0_rdata ),
.o_ready ( o_port0_ready ),
 
.o_valid ( wbuf_valid [0] ),
.i_accepted ( wbuf_accepted [0] ),
152,12 → 152,12
.i_clk ( i_clk ),
 
.i_req ( i_port1_req ),
.o_ack ( o_port1_ack ),
.i_write ( i_port1_write ),
.i_wdata ( i_port1_wdata ),
.i_be ( i_port1_be ),
.i_addr ( i_port1_addr ),
.o_rdata ( o_port1_rdata ),
.o_ready ( o_port1_ready ),
 
.o_valid ( wbuf_valid [1] ),
.i_accepted ( wbuf_accepted [1] ),
174,12 → 174,12
.i_clk ( i_clk ),
 
.i_req ( i_port2_req ),
.o_ack ( o_port2_ack ),
.i_write ( i_port2_write ),
.i_wdata ( i_port2_wdata ),
.i_be ( i_port2_be ),
.i_addr ( i_port2_addr ),
.o_rdata ( o_port2_rdata ),
.o_ready ( o_port2_ready ),
 
.o_valid ( wbuf_valid [2] ),
.i_accepted ( wbuf_accepted [2] ),
/a25_mem.v
68,7 → 68,6
// Wishbone accesses
output o_wb_cached_req, // Cached Request
output o_wb_uncached_req, // Unached Request
output o_wb_qword, // High for a quad-word read request
output o_wb_write, // Read=0, Write=1
output [15:0] o_wb_byte_enable, // byte eable
output [127:0] o_wb_write_data,
150,7 → 149,6
assign o_wb_write_data = {4{i_write_data}};
assign o_wb_cached_req = !cached_wb_stop_r && cached_wb_req;
assign o_wb_uncached_req = !uncached_wb_stop_r && uncached_data_access_p;
assign o_wb_qword = !cached_wb_stop_r && cached_wb_req && !i_write_enable;
 
assign uncached_wb_wait = (o_wb_uncached_req || uncached_wb_req_r) && !i_wb_uncached_ready;
 
/a25_core.v
163,7 → 163,6
wire dcache_wb_cached_req;
wire dcache_wb_uncached_req;
wire dcache_wb_qword;
wire dcache_wb_write;
wire [15:0] dcache_wb_byte_enable;
wire [31:0] dcache_wb_address;
404,7 → 403,6
.o_wb_cached_req ( dcache_wb_cached_req ),
.o_wb_uncached_req ( dcache_wb_uncached_req ),
.o_wb_qword ( dcache_wb_qword ),
.o_wb_write ( dcache_wb_write ),
.o_wb_write_data ( dcache_wb_write_data ),
.o_wb_byte_enable ( dcache_wb_byte_enable ),
447,30 → 445,30
// Port 0 - dcache uncached
.i_port0_req ( dcache_wb_uncached_req ),
.o_port0_ack ( dcache_wb_uncached_ready ),
.i_port0_write ( dcache_wb_write ),
.i_port0_wdata ( dcache_wb_write_data ),
.i_port0_be ( dcache_wb_byte_enable ),
.i_port0_addr ( dcache_wb_address ),
.o_port0_rdata ( dcache_wb_uncached_rdata ),
.o_port0_ready ( dcache_wb_uncached_ready ),
 
// Port 1 - dcache cached
.i_port1_req ( dcache_wb_cached_req ),
.o_port1_ack ( dcache_wb_cached_ready ),
.i_port1_write ( dcache_wb_write ),
.i_port1_wdata ( dcache_wb_write_data ),
.i_port1_be ( dcache_wb_byte_enable ),
.i_port1_addr ( dcache_wb_address ),
.o_port1_rdata ( dcache_wb_cached_rdata ),
.o_port1_ready ( dcache_wb_cached_ready ),
 
// Port 2 - instruction cache accesses, read only
.i_port2_req ( icache_wb_req ),
.o_port2_ack ( icache_wb_ready ),
.i_port2_write ( 1'd0 ),
.i_port2_wdata ( 128'd0 ),
.i_port2_be ( 16'd0 ),
.i_port2_addr ( icache_wb_address ),
.o_port2_rdata ( icache_wb_read_data ),
.o_port2_ready ( icache_wb_ready ),
 
// Wishbone
.o_wb_adr ( o_wb_adr ),

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