OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw/vlog/system
    from Rev 57 to Rev 61
    ↔ Reverse comparison
  •

Rev 57 → Rev 61

/register_addresses.v
55,6 → 55,8
localparam AMBER_TEST_SIM_CTRL = 16'h001c;
localparam AMBER_TEST_MEM_CTRL = 16'h0020;
localparam AMBER_TEST_CYCLES = 16'h0024;
localparam AMBER_TEST_LED = 16'h0028;
localparam AMBER_TEST_PHY_RST = 16'h002c;
 
localparam AMBER_TEST_RANDOM_NUM = 16'h0100;
localparam AMBER_TEST_RANDOM_NUM00 = 16'h0100;
/system.v
95,7 → 95,9
input mcrs_pad_i,
inout md_pad_io,
output mdc_pad_o,
output phy_reset_n
output phy_reset_n,
 
output [3:0] led
);
 
 
331,7 → 333,7
);
 
// Ethernet MII PHY reset
assign phy_reset_n = !sys_rst;
//assign phy_reset_n = !sys_rst;
 
// Halt core until system is ready
assign system_rdy = phy_init_done && !sys_rst;
454,7 → 456,9
.i_wb_cyc ( s_wb_cyc [5] ),
.i_wb_stb ( s_wb_stb [5] ),
.o_wb_ack ( s_wb_ack [5] ),
.o_wb_err ( s_wb_err [5] )
.o_wb_err ( s_wb_err [5] ),
.o_led ( led ),
.o_phy_rst_n ( phy_reset_n )
);
 
 
/test_module.v
58,9 → 58,10
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
output o_wb_err,
output [3:0] o_led,
output o_phy_rst_n
 
 
);
 
`include "register_addresses.v"
89,6 → 90,10
reg [31:0] wb_rdata32 = 'd0;
wire [31:0] wb_wdata32;
 
reg [3:0] led_reg = 'd0;
reg phy_rst_reg = 'd0;
 
 
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
97,11 → 102,12
always @( posedge i_clk )
wb_start_read_d1 <= wb_start_read;
 
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err = 1'd0;
assign o_mem_ctrl = mem_ctrl_reg;
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err = 1'd0;
assign o_mem_ctrl = mem_ctrl_reg;
assign o_led = led_reg;
assign o_phy_rst_n = phy_rst_reg;
 
 
generate
if (WB_DWIDTH == 128)
begin : wb128
119,6 → 125,7
end
endgenerate
 
 
// ========================================================
// Register Reads
// ========================================================
160,6 → 167,8
AMBER_TEST_MEM_CTRL: wb_rdata32 <= {31'd0, mem_ctrl_reg};
AMBER_TEST_CYCLES: wb_rdata32 <= cycles_reg;
AMBER_TEST_LED: wb_rdata32 <= {27'd0, led_reg};
AMBER_TEST_PHY_RST: wb_rdata32 <= {31'd0, phy_rst_reg};
default: wb_rdata32 <= 32'haabbccdd;
endcase
255,12 → 264,14
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
test_status_set <= 1'd1;
 
 
// ======================================
// Cycles counter
// ======================================
always @( posedge i_clk )
cycles_reg <= cycles_reg + 1'd1;
 
// ======================================
// Memory Configuration Register Write
// ======================================
270,6 → 281,22
 
 
// ======================================
// Test LEDs
// ======================================
always @( posedge i_clk )
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_LED )
led_reg <= wb_wdata32[3:0];
 
 
// ======================================
// PHY Reset Register
// ======================================
always @( posedge i_clk )
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_PHY_RST )
phy_rst_reg <= wb_wdata32[0];
 
 
// ======================================
// Test UART registers
// ======================================
// These control the testbench UART, not the real
/wishbone_arbiter.v
49,7 → 49,7
 
input i_wb_clk, // WISHBONE clock
 
// WISHBONE master 0 - Amber
// WISHBONE master 0 - Ethmac
input [31:0] i_m0_wb_adr,
input [WB_SWIDTH-1:0] i_m0_wb_sel,
input i_m0_wb_we,
61,7 → 61,7
output o_m0_wb_err,
 
 
// WISHBONE master 1 - Ethmac
// WISHBONE master 1 - Amber
input [31:0] i_m1_wb_adr,
input [WB_SWIDTH-1:0] i_m1_wb_sel,
input i_m1_wb_we,
/boot_mem128.v
45,7 → 45,7
module boot_mem128 #(
parameter WB_DWIDTH = 128,
parameter WB_SWIDTH = 16,
parameter MADDR_WIDTH = 9
parameter MADDR_WIDTH = 10
)(
input i_wb_clk, // WISHBONE clock
 
121,12 → 121,7
//
`ifdef XILINX_FPGA
 
`ifdef XILINX_SPARTAN6_FPGA
xs6_sram_512x128_byte_en
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_sram_512x128_byte_en
`endif
xs6_sram_1024x128_byte_en
 
#(
// This file holds a software image used for FPGA simulations
137,8 → 132,12
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
// default file
`include "boot-loader_memparams128.v"
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams128.v"
`else
// default file
`include "boot-loader_memparams128.v"
`endif
`endif
 
)
155,7 → 154,7
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 2048 words, 32 bits
.i_address ( address ), // 1024 words, 128 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
/interrupt_controller.v
138,10 → 138,12
// ======================================
assign raw_interrupts = {23'd0,
i_ethmac_int, // 8: Ethernet MAC interrupt
i_tm_timer_int[2], // 7: Timer Module Interrupt 2
i_tm_timer_int[1], // 6: Timer Module Interrupt 1
i_tm_timer_int[0], // 5: Timer Module Interrupt 0
1'd0,
1'd0,
i_uart1_int, // 2: Uart 1 interrupt
i_uart0_int, // 1: Uart 0 interrupt
/memory_configuration.v
43,8 → 43,8
// e.g. 24 for 32MBytes, 26 for 128MBytes
localparam MAIN_MSB = 26;
 
// e.g. 12 for 2k words
localparam BOOT_MSB = 12;
// e.g. 13 for 4k words
localparam BOOT_MSB = 13;
 
localparam MAIN_BASE = 32'h0000_0000; /* Main Memory */
localparam BOOT_BASE = 32'h0000_0000; /* Cachable Boot Memory */
/boot_mem32.v
45,7 → 45,7
module boot_mem32 #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4,
parameter MADDR_WIDTH = 11
parameter MADDR_WIDTH = 12
)(
input i_wb_clk, // WISHBONE clock
 
119,14 → 119,7
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
 
`ifdef XILINX_SPARTAN6_FPGA
xs6_sram_2048x32_byte_en
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_sram_2048x32_byte_en
`endif
 
xs6_sram_4096x32_byte_en
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
136,8 → 129,12
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
// default file
`include "boot-loader_memparams32.v"
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams32.v"
`else
// default file
`include "boot-loader_memparams32.v"
`endif
`endif
 
)

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.