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    /amber/trunk/hw/vlog
    from Rev 60 to Rev 61
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Rev 60 → Rev 61

/ethmac/eth_wishbone.v
428,6 → 428,7
reg [14:11] TxStatus;
 
reg [14:13] RxStatus;
wire [14:13] RxStatus_s;
 
reg TxStartFrm_wb;
reg TxRetry_wb;
1352,8 → 1353,8
assign PerPacketCrcEn = TxStatus[11];
 
 
assign RxIRQEn = RxStatus[14];
assign WrapRxStatusBit = RxStatus[13];
assign RxIRQEn = RxStatus_s[14];
assign WrapRxStatusBit = RxStatus_s[13];
 
 
// Temporary Tx and Rx buffer descriptor address
1387,7 → 1388,7
 
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
 
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus_s, 4'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
 
 
1874,7 → 1875,10
RxStatus <=#Tp ram_do[14:13];
end
 
// Need the RxStatus 1 cycle early when doing an RxStatusWrite immediately after a read
assign RxStatus_s = (RxEn & RxEn_q & RxBDRead) ? ram_do[14:13] : RxStatus;
 
 
// RxReady generation
always @ (posedge WB_CLK_I or posedge Reset)
begin
/system/register_addresses.v
55,6 → 55,8
localparam AMBER_TEST_SIM_CTRL = 16'h001c;
localparam AMBER_TEST_MEM_CTRL = 16'h0020;
localparam AMBER_TEST_CYCLES = 16'h0024;
localparam AMBER_TEST_LED = 16'h0028;
localparam AMBER_TEST_PHY_RST = 16'h002c;
 
localparam AMBER_TEST_RANDOM_NUM = 16'h0100;
localparam AMBER_TEST_RANDOM_NUM00 = 16'h0100;
/system/system.v
95,7 → 95,9
input mcrs_pad_i,
inout md_pad_io,
output mdc_pad_o,
output phy_reset_n
output phy_reset_n,
 
output [3:0] led
);
 
 
331,7 → 333,7
);
 
// Ethernet MII PHY reset
assign phy_reset_n = !sys_rst;
//assign phy_reset_n = !sys_rst;
 
// Halt core until system is ready
assign system_rdy = phy_init_done && !sys_rst;
454,7 → 456,9
.i_wb_cyc ( s_wb_cyc [5] ),
.i_wb_stb ( s_wb_stb [5] ),
.o_wb_ack ( s_wb_ack [5] ),
.o_wb_err ( s_wb_err [5] )
.o_wb_err ( s_wb_err [5] ),
.o_led ( led ),
.o_phy_rst_n ( phy_reset_n )
);
 
 
/system/test_module.v
58,9 → 58,10
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
output o_wb_err,
output [3:0] o_led,
output o_phy_rst_n
 
 
);
 
`include "register_addresses.v"
89,6 → 90,10
reg [31:0] wb_rdata32 = 'd0;
wire [31:0] wb_wdata32;
 
reg [3:0] led_reg = 'd0;
reg phy_rst_reg = 'd0;
 
 
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
97,11 → 102,12
always @( posedge i_clk )
wb_start_read_d1 <= wb_start_read;
 
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err = 1'd0;
assign o_mem_ctrl = mem_ctrl_reg;
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
assign o_wb_err = 1'd0;
assign o_mem_ctrl = mem_ctrl_reg;
assign o_led = led_reg;
assign o_phy_rst_n = phy_rst_reg;
 
 
generate
if (WB_DWIDTH == 128)
begin : wb128
119,6 → 125,7
end
endgenerate
 
 
// ========================================================
// Register Reads
// ========================================================
160,6 → 167,8
AMBER_TEST_MEM_CTRL: wb_rdata32 <= {31'd0, mem_ctrl_reg};
AMBER_TEST_CYCLES: wb_rdata32 <= cycles_reg;
AMBER_TEST_LED: wb_rdata32 <= {27'd0, led_reg};
AMBER_TEST_PHY_RST: wb_rdata32 <= {31'd0, phy_rst_reg};
default: wb_rdata32 <= 32'haabbccdd;
endcase
255,12 → 264,14
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_STATUS )
test_status_set <= 1'd1;
 
 
// ======================================
// Cycles counter
// ======================================
always @( posedge i_clk )
cycles_reg <= cycles_reg + 1'd1;
 
// ======================================
// Memory Configuration Register Write
// ======================================
270,6 → 281,22
 
 
// ======================================
// Test LEDs
// ======================================
always @( posedge i_clk )
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_LED )
led_reg <= wb_wdata32[3:0];
 
 
// ======================================
// PHY Reset Register
// ======================================
always @( posedge i_clk )
if ( wb_start_write && i_wb_adr[15:0] == AMBER_TEST_PHY_RST )
phy_rst_reg <= wb_wdata32[0];
 
 
// ======================================
// Test UART registers
// ======================================
// These control the testbench UART, not the real
/system/wishbone_arbiter.v
49,7 → 49,7
 
input i_wb_clk, // WISHBONE clock
 
// WISHBONE master 0 - Amber
// WISHBONE master 0 - Ethmac
input [31:0] i_m0_wb_adr,
input [WB_SWIDTH-1:0] i_m0_wb_sel,
input i_m0_wb_we,
61,7 → 61,7
output o_m0_wb_err,
 
 
// WISHBONE master 1 - Ethmac
// WISHBONE master 1 - Amber
input [31:0] i_m1_wb_adr,
input [WB_SWIDTH-1:0] i_m1_wb_sel,
input i_m1_wb_we,
/system/boot_mem128.v
45,7 → 45,7
module boot_mem128 #(
parameter WB_DWIDTH = 128,
parameter WB_SWIDTH = 16,
parameter MADDR_WIDTH = 9
parameter MADDR_WIDTH = 10
)(
input i_wb_clk, // WISHBONE clock
 
121,12 → 121,7
//
`ifdef XILINX_FPGA
 
`ifdef XILINX_SPARTAN6_FPGA
xs6_sram_512x128_byte_en
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_sram_512x128_byte_en
`endif
xs6_sram_1024x128_byte_en
 
#(
// This file holds a software image used for FPGA simulations
137,8 → 132,12
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
// default file
`include "boot-loader_memparams128.v"
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams128.v"
`else
// default file
`include "boot-loader_memparams128.v"
`endif
`endif
 
)
155,7 → 154,7
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 2048 words, 32 bits
.i_address ( address ), // 1024 words, 128 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
/system/interrupt_controller.v
138,10 → 138,12
// ======================================
assign raw_interrupts = {23'd0,
i_ethmac_int, // 8: Ethernet MAC interrupt
i_tm_timer_int[2], // 7: Timer Module Interrupt 2
i_tm_timer_int[1], // 6: Timer Module Interrupt 1
i_tm_timer_int[0], // 5: Timer Module Interrupt 0
1'd0,
1'd0,
i_uart1_int, // 2: Uart 1 interrupt
i_uart0_int, // 1: Uart 0 interrupt
/system/memory_configuration.v
43,8 → 43,8
// e.g. 24 for 32MBytes, 26 for 128MBytes
localparam MAIN_MSB = 26;
 
// e.g. 12 for 2k words
localparam BOOT_MSB = 12;
// e.g. 13 for 4k words
localparam BOOT_MSB = 13;
 
localparam MAIN_BASE = 32'h0000_0000; /* Main Memory */
localparam BOOT_BASE = 32'h0000_0000; /* Cachable Boot Memory */
/system/boot_mem32.v
45,7 → 45,7
module boot_mem32 #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4,
parameter MADDR_WIDTH = 11
parameter MADDR_WIDTH = 12
)(
input i_wb_clk, // WISHBONE clock
 
119,14 → 119,7
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
 
`ifdef XILINX_SPARTAN6_FPGA
xs6_sram_2048x32_byte_en
`endif
`ifdef XILINX_VIRTEX6_FPGA
xv6_sram_2048x32_byte_en
`endif
 
xs6_sram_4096x32_byte_en
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
136,8 → 129,12
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
// default file
`include "boot-loader_memparams32.v"
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams32.v"
`else
// default file
`include "boot-loader_memparams32.v"
`endif
`endif
 
)
/tb/debug_functions.v
56,6 → 56,15
endfunction
 
 
function [7:0] hex_chars_to_8bits;
input [8*2-1:0] hex_chars;
begin
hex_chars_to_8bits[ 7: 4] = hex_chars_to_4bits (hex_chars[2*8-1:1*8]);
hex_chars_to_8bits[ 3: 0] = hex_chars_to_4bits (hex_chars[1*8-1: 0]);
end
endfunction
 
 
function [3:0] hex_chars_to_4bits;
input [7:0] hex_chars;
begin
/tb/eth_test.v
0,0 → 1,683
//////////////////////////////////////////////////////////////////
// //
// Top-level module instantiating the entire Amber 2 system. //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// This is the highest level synthesizable module in the //
// project. The ports in this module represent pins on the //
// FPGA. //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2012 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
 
 
module eth_test
(
// MD interface - serial configuration of PHY
inout md_io,
input mdc_i,
 
// MAC interface - packet to DUT
input mtx_clk_i,
output reg [3:0] mtxd_o,
output reg mtxdv_o,
output reg mtxerr_o,
 
 
// MAC interface - packet from DUT
input [3:0] mrxd_i,
input mrxdv_i
);
 
`include "debug_functions.v"
`include "system_functions.v"
 
// mxt state machine
localparam IDLE = 4'd0;
localparam TX_0 = 4'd1;
localparam TX_1 = 4'd2;
localparam WAIT = 4'd3;
localparam PREA = 4'd4;
localparam PREB = 4'd5;
localparam GAP = 4'd6;
localparam CRC0 = 4'd7;
localparam CRCN = 4'd8;
localparam POLL = 4'd9;
 
 
// rx state machine
localparam RX_IDLE = 4'd0;
localparam RX_0 = 4'd1;
localparam RX_1 = 4'd2;
localparam RX_PRE = 4'd3;
localparam RX_DONE = 4'd4;
 
 
// md state machine
localparam MD_REGADDR = 4'd0;
localparam MD_PHYADDR = 4'd1;
localparam MD_WRITE0 = 4'd2;
localparam MD_READ0 = 4'd3;
localparam MD_START1 = 4'd4;
localparam MD_START0 = 4'd5;
localparam MD_IDLE = 4'd6;
localparam MD_TURN0 = 4'd7;
localparam MD_TURN1 = 4'd8;
localparam MD_RDATA = 4'd9;
localparam MD_WDATA = 4'd10;
localparam MD_WXFR = 4'd11;
 
localparam MDREAD = 1'd0;
localparam MDWRITE = 1'd1;
 
 
// MD register addresses
localparam MII_BMCR = 5'd0; /* Basic mode control register */
localparam MII_BMSR = 5'd1; /* Basic mode status register */
localparam MII_CTRL1000 = 5'd9; /* 1000BASE-T control */
 
 
reg [7:0] mem [2**16-1:0];
reg [7:0] eth [13:0];
 
reg [7:0] rxm [2047:0];
 
reg [15:0] line_r = 16'd0;
reg [15:0] rx_line_r;
 
reg [3:0] state_r = IDLE;
reg [3:0] md_state_r = MD_IDLE;
reg [3:0] rx_state_r = RX_IDLE;
reg [15:0] pkt_len_r;
reg [31:0] wcount_r;
reg [15:0] pkt_pos_r;
reg [3:0] pcount_r;
 
reg md_op_r = MDREAD;
reg [4:0] md_count_r;
reg [4:0] md_phy_addr_r;
reg [4:0] md_reg_addr_r;
reg [15:0] md_rdata_r;
reg [15:0] md_wdata_r;
reg [15:0] md_bmcr_r = 'd0;
reg [15:0] md_ctrl1000_r = 16'hffff;
wire init;
wire [31:0] crc;
wire [3:0] crc_dinx;
reg [3:0] crc_din;
wire enable;
reg [3:0] mrxd_r;
 
reg [7:0] last_pkt_num_r = 'd0;
 
 
integer pkt_to_amber_file;
integer pkt_to_amber_ack_file;
integer pkt_from_amber_file;
 
reg [8*20-1:0] pkt_to_amber = "pkt_to_amber.mem";
reg [8*20-1:0] pkt_to_amber_ack = "pkt_to_amber_ack.txt";
reg [8*20-1:0] pkt_from_amber = "pkt_from_amber.mem";
 
reg [4*8-1:0] line;
integer fgets_return;
integer pkt_to_amber_address;
reg [7:0] pkt_to_amber_data;
 
integer x;
reg [7:0] pkt_from_amber_num = 8'd1;
 
 
// initializwe the ack file to 0
// this allows sim_socket to write the first packet
initial
begin
pkt_to_amber_ack_file = $fopen(pkt_to_amber_ack, "w");
$fwrite(pkt_to_amber_ack_file, "0\n");
$fclose(pkt_to_amber_ack_file);
end
// ============================
// packet tx state machine
// ============================
always@(posedge mtx_clk_i)
begin
case (state_r)
IDLE:
begin
mtxd_o <= 'd0;
mtxdv_o <= 'd0;
mtxerr_o <= 'd0;
wcount_r <= 'd0;
if (md_bmcr_r[9]) // autoneg bit set by software
begin
wcount_r <= wcount_r + 1'd1;
if (wcount_r == 32'd10000)
begin
state_r <= POLL;
wcount_r <= 'd0;
$display("Start polling for packets to send to amber");
end
end
end
 
WAIT:
begin
wcount_r <= wcount_r + 1'd1;
if (wcount_r == 32'd100)
begin
wcount_r <= 'd0;
state_r <= POLL;
end
end
 
POLL: // scan for new packets
begin
mtxd_o <= 'd0;
mtxdv_o <= 'd0;
mtxerr_o <= 'd0;
pkt_to_amber_file = $fopen(pkt_to_amber, "r");
fgets_return = $fgets(line, pkt_to_amber_file);
pkt_to_amber_address = 0;
while (fgets_return)
begin
pkt_to_amber_data = hex_chars_to_8bits (line[23:8]);
mem[pkt_to_amber_address] = pkt_to_amber_data[7:0];
pkt_to_amber_address = pkt_to_amber_address + 1;
fgets_return = $fgets(line, pkt_to_amber_file);
end
$fclose(pkt_to_amber_file);
 
if (mem[0] != last_pkt_num_r)
begin
state_r <= PREA;
pkt_len_r <= {mem[1], mem[2]} + 16'd14;
last_pkt_num_r <= mem[0];
line_r <= 'd0;
pkt_pos_r <= 'd0;
pcount_r <= 'd0;
wcount_r <= 'd0;
pkt_to_amber_ack_file = $fopen(pkt_to_amber_ack, "w");
$fwrite(pkt_to_amber_ack_file, "%d\n", mem[0]);
$fclose(pkt_to_amber_ack_file);
end
else begin
state_r <= WAIT;
end
end
PREA: // Preamble
begin
mtxd_o <= 4'b0101;
mtxdv_o <= 1'd1;
pcount_r <= pcount_r + 1'd1;
if (pcount_r == 4'd6)
begin
pcount_r <= 'd0;
state_r <= PREB;
end
end
PREB:
begin
mtxd_o <= 4'b1101;
mtxdv_o <= 1'd1;
state_r <= TX_0;
print_pkt(1'd1, line_r);
end
TX_0: // low 4 bits
begin
mtxd_o <= mem[line_r+3][3:0];
mtxdv_o <= 1'd1;
state_r <= TX_1;
end
TX_1: // high 4 bits
begin
mtxd_o <= mem[line_r+3][7:4];
mtxdv_o <= 1'd1;
line_r <= line_r + 1'd1;
if (pkt_pos_r + 1'd1 == pkt_len_r)
state_r <= CRC0;
else
begin
state_r <= TX_0;
pkt_pos_r <= pkt_pos_r + 1'd1;
end
end
 
CRC0:
begin
mtxd_o <= {~crc[28], ~crc[29], ~crc[30], ~crc[31]};
mtxdv_o <= 1'd1;
state_r <= POLL;
end
endcase
end
 
 
assign init = state_r == PREB;
assign enable = state_r != CRC0;
 
always @*
begin
crc_din = state_r == TX_0 ? mem[line_r+3][3:0] :
state_r == TX_1 ? mem[line_r+3][7:4] :
32'd0 ;
end
assign crc_dinx = {crc_din[0], crc_din[1], crc_din[2], crc_din[3]};
 
 
// Gen CRC, using the EthMac CRC generator
eth_crc eth_crc (
.Clk ( mtx_clk_i ),
.Reset ( 1'd0 ),
.Data ( crc_dinx ),
.Enable ( enable ),
.Initialize ( init ),
 
.Crc ( crc ),
.CrcError ( )
);
 
 
// ============================
// packet rx state machine
// ============================
always@(posedge mtx_clk_i)
begin
case (rx_state_r)
RX_IDLE:
begin
rx_line_r <= 'd0;
if (mrxdv_i) // autoneg bit set by software
begin
rx_state_r <= RX_PRE;
end
end
RX_PRE:
begin
if (mrxd_i == 4'hd)
rx_state_r <= RX_0;
end
RX_0: // low 4 bits
begin
mrxd_r <= mrxd_i;
if (mrxdv_i)
rx_state_r <= RX_1;
else
rx_state_r <= RX_DONE;
end
RX_1: // high 4 bits
begin
rxm[rx_line_r] <= {mrxd_i, mrxd_r};
rx_line_r <= rx_line_r + 1'd1;
if (mrxdv_i)
rx_state_r <= RX_0;
else
rx_state_r <= RX_DONE;
end
 
 
RX_DONE:
begin
print_pkt(1'd0, 16'd0);
rx_state_r <= RX_IDLE;
pkt_from_amber_file = $fopen(pkt_from_amber, "w");
$fwrite(pkt_from_amber_file, "%02h\n", pkt_from_amber_num);
for (x=0;x<rx_line_r;x=x+1)
$fwrite(pkt_from_amber_file, "%02h\n", rxm[x]);
$fclose(pkt_from_amber_file);
if (pkt_from_amber_num == 8'd255)
pkt_from_amber_num <= 8'd1;
else
pkt_from_amber_num <= pkt_from_amber_num + 1'd1;
end
endcase
end
 
 
 
 
// ============================
// management data state machine
// ============================
always@(posedge mdc_i)
begin
case (md_state_r)
MD_IDLE:
begin
md_count_r <= 'd0;
if (md_io == 1'd0)
md_state_r <= MD_START0;
end
MD_START0:
begin
if (md_io == 1'd1)
md_state_r <= MD_START1;
else
md_state_r <= MD_IDLE;
end
MD_START1:
begin
if (md_io == 1'd1)
md_state_r <= MD_READ0;
else
md_state_r <= MD_WRITE0;
end
MD_READ0:
begin
if (md_io == 1'd0)
begin
md_state_r <= MD_PHYADDR;
md_op_r <= MDREAD;
end
else
md_state_r <= MD_IDLE;
end
MD_WRITE0:
begin
if (md_io == 1'd1)
begin
md_state_r <= MD_PHYADDR;
md_op_r <= MDWRITE;
end
else
md_state_r <= MD_IDLE;
end
MD_PHYADDR:
begin
md_count_r <= md_count_r + 1'd1;
md_phy_addr_r <= {md_phy_addr_r[3:0], md_io};
if (md_count_r == 5'd4)
begin
md_state_r <= MD_REGADDR;
md_count_r <= 'd0;
end
end
MD_REGADDR:
begin
md_count_r <= md_count_r + 1'd1;
md_reg_addr_r <= {md_reg_addr_r[3:0], md_io};
if (md_count_r == 5'd4)
begin
md_count_r <= 'd0;
md_state_r <= MD_TURN0;
end
end
 
 
MD_TURN0:
md_state_r <= MD_TURN1;
 
MD_TURN1:
begin
if (md_op_r == MDREAD)
md_state_r <= MD_RDATA;
else
md_state_r <= MD_WDATA;
case (md_reg_addr_r)
MII_BMCR : md_rdata_r <= md_bmcr_r;
MII_BMSR : md_rdata_r <= 16'hfe04;
MII_CTRL1000 : md_rdata_r <= md_ctrl1000_r;
default : md_rdata_r <= 'd0;
endcase
end
MD_RDATA:
begin
md_count_r <= md_count_r + 1'd1;
md_rdata_r <= {md_rdata_r[14:0], 1'd0};
if (md_count_r == 5'd15)
md_state_r <= MD_IDLE;
end
 
 
MD_WDATA:
begin
md_count_r <= md_count_r + 1'd1;
md_wdata_r <= {md_wdata_r[14:0], md_io};
if (md_count_r == 5'd15)
begin
md_state_r <= MD_WXFR;
md_count_r <= 'd0;
end
end
 
 
MD_WXFR:
begin
case (md_reg_addr_r)
MII_BMCR : md_bmcr_r <= md_wdata_r;
MII_CTRL1000 : md_ctrl1000_r <= md_wdata_r;
endcase
md_state_r <= MD_IDLE;
end
endcase
end
 
 
assign md_io = md_state_r == MD_RDATA ? md_rdata_r[15] : 1'bz;
 
 
 
task print_pkt;
input tx; /* 1 for tx, 0 for rx */
input [31:0] start;
reg [15:0] eth_type;
reg [7:0] proto;
reg [31:0] frame;
reg [3:0] ip_hdr_len;
reg [15:0] ip_len;
reg [3:0] tcp_hdr_len;
reg [15:0] tcp_bdy_len;
reg [7:0] tmp;
reg [15:0] arp_op;
 
integer i;
begin
frame = start;
if (tx) $write("%6d pkt to amber ", tb.clk_count);
else $write("%6d pkt from amber ", tb.clk_count);
$display("mac-dst %h:%h:%h:%h:%h:%h, mac-src %h:%h:%h:%h:%h:%h, type %h%h",
rmem(tx,frame+0), rmem(tx,frame+1),rmem(tx,frame+2),rmem(tx,frame+3),rmem(tx,frame+4),rmem(tx,frame+5),
rmem(tx,frame+6), rmem(tx,frame+7),rmem(tx,frame+8),rmem(tx,frame+9),rmem(tx,frame+10),rmem(tx,frame+11),
rmem(tx,frame+12),rmem(tx,frame+13));
eth_type = {rmem(tx,frame+12),rmem(tx,frame+13)};
 
if (eth_type == 16'h0806) // arp
begin
frame = frame + 14;
arp_op = rmem(tx,frame+6) << 8 | rmem(tx,frame+7);
$write("ARP operation %0d", arp_op);
if (arp_op == 16'd1)
$write(" look for ip %0d.%0d.%0d.%0d",
rmem(tx,frame+24), rmem(tx,frame+25),rmem(tx,frame+26),rmem(tx,frame+27));
$write("\n");
end
if (eth_type == 16'h0800) // ip
begin
frame = frame + 14;
proto = rmem(tx,frame+9);
tmp = rmem(tx,frame+0);
ip_hdr_len = tmp[3:0];
ip_len = {rmem(tx,frame+2), rmem(tx,frame+3)};
$display(" ip-dst %0d.%0d.%0d.%0d, ip-src %0d.%0d.%0d.%0d, proto %0d, ip_len %0d, ihl %0d",
rmem(tx,frame+16), rmem(tx,frame+17),rmem(tx,frame+18),rmem(tx,frame+19),
rmem(tx,frame+12), rmem(tx,frame+13),rmem(tx,frame+14),rmem(tx,frame+15),
proto, ip_len, ip_hdr_len*4);
if (proto == 8'd6) // TCP
begin
frame = frame + ip_hdr_len*4;
tmp = rmem(tx,frame+12);
tcp_hdr_len = tmp[7:4];
tcp_bdy_len = ip_len - ({ip_hdr_len,2'd0} + {tcp_hdr_len,2'd0});
$display(" tcp-dst %0d, tcp-src %0d, tcp hdr len %0d, tcp bdy len %0d",
{rmem(tx,frame+2), rmem(tx,frame+3)},
{rmem(tx,frame+0), rmem(tx,frame+1)}, tcp_hdr_len*4, tcp_bdy_len);
$display(" tcp-seq %0d, tcp-ack %0d",
{rmem(tx,frame+4), rmem(tx,frame+5), rmem(tx,frame+6), rmem(tx,frame+7)},
{rmem(tx,frame+8), rmem(tx,frame+9), rmem(tx,frame+10), rmem(tx,frame+11)});
if (tcp_bdy_len != 16'd0)
begin
for (i=0;i<tcp_bdy_len;i=i+1)
if ((rmem(tx,frame+tcp_hdr_len*4+i) > 31 && rmem(tx,frame+tcp_hdr_len*4+i) < 128) ||
(rmem(tx,frame+tcp_hdr_len*4+i) == "\n"))
$write("%c", rmem(tx,frame+tcp_hdr_len*4+i));
end
end
end
$display("----");
end
endtask
 
 
function [7:0] rmem;
input tx; /* 1 for tx, 0 for rx */
input [31:0] addr;
begin
if (tx)
rmem = mem[addr+3];
else
rmem = rxm[addr];
end
endfunction
 
 
wire [8*6-1:0] XSTATE =
state_r == IDLE ? "IDLE" :
state_r == WAIT ? "WAIT" :
state_r == TX_0 ? "TX_0" :
state_r == TX_1 ? "TX_1" :
state_r == PREA ? "PREA" :
state_r == PREB ? "PREB" :
state_r == GAP ? "GAP" :
state_r == CRC0 ? "CRC0" :
state_r == CRCN ? "CRCN" :
state_r == POLL ? "POLL" :
"UNKNOWN" ;
 
wire [8*12-1:0] XRXSTATE =
state_r == RX_IDLE ? "RX_IDLE" :
state_r == RX_0 ? "RX_0" :
state_r == RX_1 ? "RX_1" :
state_r == RX_PRE ? "RX_PRE" :
state_r == RX_DONE ? "RX_DONE" :
"UNKNOWN" ;
 
wire [8*12-1:0] XMDSTATE =
md_state_r == MD_WXFR ? "MD_WXFR" :
md_state_r == MD_WDATA ? "MD_WDATA" :
md_state_r == MD_RDATA ? "MD_RDATA" :
md_state_r == MD_TURN1 ? "MD_TURN1" :
md_state_r == MD_TURN0 ? "MD_TURN0" :
md_state_r == MD_REGADDR ? "MD_REGADDR" :
md_state_r == MD_PHYADDR ? "MD_PHYADDR" :
md_state_r == MD_WRITE0 ? "MD_WRITE0" :
md_state_r == MD_READ0 ? "MD_READ0" :
md_state_r == MD_START1 ? "MD_START1" :
md_state_r == MD_START0 ? "MD_START0" :
md_state_r == MD_IDLE ? "MD_IDLE" :
"UNKNOWN" ;
 
endmodule
 
 
/tb/tb.v
48,6 → 48,7
 
`include "debug_functions.v"
`include "system_functions.v"
`include "memory_configuration.v"
 
reg sysrst;
`ifdef XILINX_VIRTEX6_FPGA
99,7 → 100,8
wire mcb3_zio;
`endif
 
tri1 md_pad_io;
tri1 md; // bi-directional phy config data
wire mdc; // phy config clock
 
wire uart0_cts;
wire uart0_rx;
106,7 → 108,14
wire uart0_rts;
wire uart0_tx;
 
wire [3:0] eth_mtxd;
wire eth_mtxdv;
wire eth_mtxerr;
wire [3:0] eth_mrxd;
wire eth_mrxdv;
 
 
 
// ======================================
// Instantiate FPGA
// ======================================
152,24 → 161,43
 
// Ethernet MII signals
.mtx_clk_pad_i ( clk_25mhz ),
.mtxd_pad_o ( ),
.mtxen_pad_o ( ),
.mtxd_pad_o ( eth_mrxd ),
.mtxen_pad_o ( eth_mrxdv ),
.mtxerr_pad_o ( ),
.mrx_clk_pad_i ( clk_25mhz ),
.mrxd_pad_i ( 4'd0 ),
.mrxdv_pad_i ( 1'd0 ),
.mrxerr_pad_i ( 1'd0 ),
.mrxd_pad_i ( eth_mtxd ),
.mrxdv_pad_i ( eth_mtxdv ),
.mrxerr_pad_i ( eth_mtxerr ),
.mcoll_pad_i ( 1'd0 ),
.mcrs_pad_i ( 1'd0 ), // Assert Carrier Sense from PHY
.phy_reset_n ( ),
// Ethernet MD signals
.md_pad_io ( md_pad_io ),
.mdc_pad_o ( )
// Ethernet Management Data signals
.md_pad_io ( md ),
.mdc_pad_o ( mdc ),
// LEDs
.led ( )
);
 
 
 
// ======================================
// Instantiate Ethernet Test Device
// ======================================
eth_test u_eth_test(
.md_io ( md ),
.mdc_i ( mdc ),
.mtx_clk_i ( clk_25mhz ),
.mtxd_o ( eth_mtxd ),
.mtxdv_o ( eth_mtxdv ),
.mtxerr_o ( eth_mtxerr ),
.mrxd_i ( eth_mrxd ),
.mrxdv_i ( eth_mrxdv )
);
 
 
 
// ======================================
// Instantiate DDR3 Memory Model
// ======================================
202,6 → 230,7
`endif
 
 
 
// ======================================
// Instantiate Testbench UART
// ======================================
214,6 → 243,7
);
 
 
 
// ======================================
// Global module for xilinx hardware simulations
// ======================================
311,13 → 341,13
boot_mem_file_data = hex_chars_to_32bits (aligned_line[110*8-1:102*8]);
`ifdef AMBER_A25_CORE
boot_mem_file_data_128 = `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]];
`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:4]] =
boot_mem_file_data_128 = `U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:4]];
`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:4]] =
insert_32_into_128 ( boot_mem_file_address[3:2],
boot_mem_file_data_128,
boot_mem_file_data );
`else
`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[12:2]] = boot_mem_file_data;
`U_BOOT_MEM.u_mem.mem[boot_mem_file_address[BOOT_MSB:2]] = boot_mem_file_data;
`endif
`ifdef AMBER_LOAD_MEM_DEBUG
/lib/xv6_sram_2048x32_byte_en.v File deleted
/lib/xv6_sram_512x128_byte_en.v File deleted
/lib/xv6_sram_256x128_byte_en.v File deleted
/lib/xv6_sram_256x32_byte_en.v File deleted
/lib/xv6_addsub_n.v File deleted
/lib/xv6_sram_256x21_line_en.v File deleted
/lib/xs6_sram_1024x128_byte_en.v
0,0 → 1,1548
//////////////////////////////////////////////////////////////////
// //
// Wrapper for Xilinx Spartan-6 RAM Block //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 512 words x 128 bits with a per byte write enable //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
module xs6_sram_1024x128_byte_en
#(
parameter SRAM0_INIT_0 = 256'h0,
parameter SRAM0_INIT_1 = 256'h0,
parameter SRAM0_INIT_2 = 256'h0,
parameter SRAM0_INIT_3 = 256'h0,
parameter SRAM0_INIT_4 = 256'h0,
parameter SRAM0_INIT_5 = 256'h0,
parameter SRAM0_INIT_6 = 256'h0,
parameter SRAM0_INIT_7 = 256'h0,
parameter SRAM0_INIT_8 = 256'h0,
parameter SRAM0_INIT_9 = 256'h0,
parameter SRAM0_INIT_10 = 256'h0,
parameter SRAM0_INIT_11 = 256'h0,
parameter SRAM0_INIT_12 = 256'h0,
parameter SRAM0_INIT_13 = 256'h0,
parameter SRAM0_INIT_14 = 256'h0,
parameter SRAM0_INIT_15 = 256'h0,
parameter SRAM0_INIT_16 = 256'h0,
parameter SRAM0_INIT_17 = 256'h0,
parameter SRAM0_INIT_18 = 256'h0,
parameter SRAM0_INIT_19 = 256'h0,
parameter SRAM0_INIT_20 = 256'h0,
parameter SRAM0_INIT_21 = 256'h0,
parameter SRAM0_INIT_22 = 256'h0,
parameter SRAM0_INIT_23 = 256'h0,
parameter SRAM0_INIT_24 = 256'h0,
parameter SRAM0_INIT_25 = 256'h0,
parameter SRAM0_INIT_26 = 256'h0,
parameter SRAM0_INIT_27 = 256'h0,
parameter SRAM0_INIT_28 = 256'h0,
parameter SRAM0_INIT_29 = 256'h0,
parameter SRAM0_INIT_30 = 256'h0,
parameter SRAM0_INIT_31 = 256'h0,
parameter SRAM0_INIT_32 = 256'h0,
parameter SRAM0_INIT_33 = 256'h0,
parameter SRAM0_INIT_34 = 256'h0,
parameter SRAM0_INIT_35 = 256'h0,
parameter SRAM0_INIT_36 = 256'h0,
parameter SRAM0_INIT_37 = 256'h0,
parameter SRAM0_INIT_38 = 256'h0,
parameter SRAM0_INIT_39 = 256'h0,
parameter SRAM0_INIT_40 = 256'h0,
parameter SRAM0_INIT_41 = 256'h0,
parameter SRAM0_INIT_42 = 256'h0,
parameter SRAM0_INIT_43 = 256'h0,
parameter SRAM0_INIT_44 = 256'h0,
parameter SRAM0_INIT_45 = 256'h0,
parameter SRAM0_INIT_46 = 256'h0,
parameter SRAM0_INIT_47 = 256'h0,
parameter SRAM0_INIT_48 = 256'h0,
parameter SRAM0_INIT_49 = 256'h0,
parameter SRAM0_INIT_50 = 256'h0,
parameter SRAM0_INIT_51 = 256'h0,
parameter SRAM0_INIT_52 = 256'h0,
parameter SRAM0_INIT_53 = 256'h0,
parameter SRAM0_INIT_54 = 256'h0,
parameter SRAM0_INIT_55 = 256'h0,
parameter SRAM0_INIT_56 = 256'h0,
parameter SRAM0_INIT_57 = 256'h0,
parameter SRAM0_INIT_58 = 256'h0,
parameter SRAM0_INIT_59 = 256'h0,
parameter SRAM0_INIT_60 = 256'h0,
parameter SRAM0_INIT_61 = 256'h0,
parameter SRAM0_INIT_62 = 256'h0,
parameter SRAM0_INIT_63 = 256'h0,
 
 
parameter SRAM1_INIT_0 = 256'h0,
parameter SRAM1_INIT_1 = 256'h0,
parameter SRAM1_INIT_2 = 256'h0,
parameter SRAM1_INIT_3 = 256'h0,
parameter SRAM1_INIT_4 = 256'h0,
parameter SRAM1_INIT_5 = 256'h0,
parameter SRAM1_INIT_6 = 256'h0,
parameter SRAM1_INIT_7 = 256'h0,
parameter SRAM1_INIT_8 = 256'h0,
parameter SRAM1_INIT_9 = 256'h0,
parameter SRAM1_INIT_10 = 256'h0,
parameter SRAM1_INIT_11 = 256'h0,
parameter SRAM1_INIT_12 = 256'h0,
parameter SRAM1_INIT_13 = 256'h0,
parameter SRAM1_INIT_14 = 256'h0,
parameter SRAM1_INIT_15 = 256'h0,
parameter SRAM1_INIT_16 = 256'h0,
parameter SRAM1_INIT_17 = 256'h0,
parameter SRAM1_INIT_18 = 256'h0,
parameter SRAM1_INIT_19 = 256'h0,
parameter SRAM1_INIT_20 = 256'h0,
parameter SRAM1_INIT_21 = 256'h0,
parameter SRAM1_INIT_22 = 256'h0,
parameter SRAM1_INIT_23 = 256'h0,
parameter SRAM1_INIT_24 = 256'h0,
parameter SRAM1_INIT_25 = 256'h0,
parameter SRAM1_INIT_26 = 256'h0,
parameter SRAM1_INIT_27 = 256'h0,
parameter SRAM1_INIT_28 = 256'h0,
parameter SRAM1_INIT_29 = 256'h0,
parameter SRAM1_INIT_30 = 256'h0,
parameter SRAM1_INIT_31 = 256'h0,
parameter SRAM1_INIT_32 = 256'h0,
parameter SRAM1_INIT_33 = 256'h0,
parameter SRAM1_INIT_34 = 256'h0,
parameter SRAM1_INIT_35 = 256'h0,
parameter SRAM1_INIT_36 = 256'h0,
parameter SRAM1_INIT_37 = 256'h0,
parameter SRAM1_INIT_38 = 256'h0,
parameter SRAM1_INIT_39 = 256'h0,
parameter SRAM1_INIT_40 = 256'h0,
parameter SRAM1_INIT_41 = 256'h0,
parameter SRAM1_INIT_42 = 256'h0,
parameter SRAM1_INIT_43 = 256'h0,
parameter SRAM1_INIT_44 = 256'h0,
parameter SRAM1_INIT_45 = 256'h0,
parameter SRAM1_INIT_46 = 256'h0,
parameter SRAM1_INIT_47 = 256'h0,
parameter SRAM1_INIT_48 = 256'h0,
parameter SRAM1_INIT_49 = 256'h0,
parameter SRAM1_INIT_50 = 256'h0,
parameter SRAM1_INIT_51 = 256'h0,
parameter SRAM1_INIT_52 = 256'h0,
parameter SRAM1_INIT_53 = 256'h0,
parameter SRAM1_INIT_54 = 256'h0,
parameter SRAM1_INIT_55 = 256'h0,
parameter SRAM1_INIT_56 = 256'h0,
parameter SRAM1_INIT_57 = 256'h0,
parameter SRAM1_INIT_58 = 256'h0,
parameter SRAM1_INIT_59 = 256'h0,
parameter SRAM1_INIT_60 = 256'h0,
parameter SRAM1_INIT_61 = 256'h0,
parameter SRAM1_INIT_62 = 256'h0,
parameter SRAM1_INIT_63 = 256'h0,
 
 
 
parameter SRAM2_INIT_0 = 256'h0,
parameter SRAM2_INIT_1 = 256'h0,
parameter SRAM2_INIT_2 = 256'h0,
parameter SRAM2_INIT_3 = 256'h0,
parameter SRAM2_INIT_4 = 256'h0,
parameter SRAM2_INIT_5 = 256'h0,
parameter SRAM2_INIT_6 = 256'h0,
parameter SRAM2_INIT_7 = 256'h0,
parameter SRAM2_INIT_8 = 256'h0,
parameter SRAM2_INIT_9 = 256'h0,
parameter SRAM2_INIT_10 = 256'h0,
parameter SRAM2_INIT_11 = 256'h0,
parameter SRAM2_INIT_12 = 256'h0,
parameter SRAM2_INIT_13 = 256'h0,
parameter SRAM2_INIT_14 = 256'h0,
parameter SRAM2_INIT_15 = 256'h0,
parameter SRAM2_INIT_16 = 256'h0,
parameter SRAM2_INIT_17 = 256'h0,
parameter SRAM2_INIT_18 = 256'h0,
parameter SRAM2_INIT_19 = 256'h0,
parameter SRAM2_INIT_20 = 256'h0,
parameter SRAM2_INIT_21 = 256'h0,
parameter SRAM2_INIT_22 = 256'h0,
parameter SRAM2_INIT_23 = 256'h0,
parameter SRAM2_INIT_24 = 256'h0,
parameter SRAM2_INIT_25 = 256'h0,
parameter SRAM2_INIT_26 = 256'h0,
parameter SRAM2_INIT_27 = 256'h0,
parameter SRAM2_INIT_28 = 256'h0,
parameter SRAM2_INIT_29 = 256'h0,
parameter SRAM2_INIT_30 = 256'h0,
parameter SRAM2_INIT_31 = 256'h0,
parameter SRAM2_INIT_32 = 256'h0,
parameter SRAM2_INIT_33 = 256'h0,
parameter SRAM2_INIT_34 = 256'h0,
parameter SRAM2_INIT_35 = 256'h0,
parameter SRAM2_INIT_36 = 256'h0,
parameter SRAM2_INIT_37 = 256'h0,
parameter SRAM2_INIT_38 = 256'h0,
parameter SRAM2_INIT_39 = 256'h0,
parameter SRAM2_INIT_40 = 256'h0,
parameter SRAM2_INIT_41 = 256'h0,
parameter SRAM2_INIT_42 = 256'h0,
parameter SRAM2_INIT_43 = 256'h0,
parameter SRAM2_INIT_44 = 256'h0,
parameter SRAM2_INIT_45 = 256'h0,
parameter SRAM2_INIT_46 = 256'h0,
parameter SRAM2_INIT_47 = 256'h0,
parameter SRAM2_INIT_48 = 256'h0,
parameter SRAM2_INIT_49 = 256'h0,
parameter SRAM2_INIT_50 = 256'h0,
parameter SRAM2_INIT_51 = 256'h0,
parameter SRAM2_INIT_52 = 256'h0,
parameter SRAM2_INIT_53 = 256'h0,
parameter SRAM2_INIT_54 = 256'h0,
parameter SRAM2_INIT_55 = 256'h0,
parameter SRAM2_INIT_56 = 256'h0,
parameter SRAM2_INIT_57 = 256'h0,
parameter SRAM2_INIT_58 = 256'h0,
parameter SRAM2_INIT_59 = 256'h0,
parameter SRAM2_INIT_60 = 256'h0,
parameter SRAM2_INIT_61 = 256'h0,
parameter SRAM2_INIT_62 = 256'h0,
parameter SRAM2_INIT_63 = 256'h0,
 
parameter SRAM3_INIT_0 = 256'h0,
parameter SRAM3_INIT_1 = 256'h0,
parameter SRAM3_INIT_2 = 256'h0,
parameter SRAM3_INIT_3 = 256'h0,
parameter SRAM3_INIT_4 = 256'h0,
parameter SRAM3_INIT_5 = 256'h0,
parameter SRAM3_INIT_6 = 256'h0,
parameter SRAM3_INIT_7 = 256'h0,
parameter SRAM3_INIT_8 = 256'h0,
parameter SRAM3_INIT_9 = 256'h0,
parameter SRAM3_INIT_10 = 256'h0,
parameter SRAM3_INIT_11 = 256'h0,
parameter SRAM3_INIT_12 = 256'h0,
parameter SRAM3_INIT_13 = 256'h0,
parameter SRAM3_INIT_14 = 256'h0,
parameter SRAM3_INIT_15 = 256'h0,
parameter SRAM3_INIT_16 = 256'h0,
parameter SRAM3_INIT_17 = 256'h0,
parameter SRAM3_INIT_18 = 256'h0,
parameter SRAM3_INIT_19 = 256'h0,
parameter SRAM3_INIT_20 = 256'h0,
parameter SRAM3_INIT_21 = 256'h0,
parameter SRAM3_INIT_22 = 256'h0,
parameter SRAM3_INIT_23 = 256'h0,
parameter SRAM3_INIT_24 = 256'h0,
parameter SRAM3_INIT_25 = 256'h0,
parameter SRAM3_INIT_26 = 256'h0,
parameter SRAM3_INIT_27 = 256'h0,
parameter SRAM3_INIT_28 = 256'h0,
parameter SRAM3_INIT_29 = 256'h0,
parameter SRAM3_INIT_30 = 256'h0,
parameter SRAM3_INIT_31 = 256'h0,
parameter SRAM3_INIT_32 = 256'h0,
parameter SRAM3_INIT_33 = 256'h0,
parameter SRAM3_INIT_34 = 256'h0,
parameter SRAM3_INIT_35 = 256'h0,
parameter SRAM3_INIT_36 = 256'h0,
parameter SRAM3_INIT_37 = 256'h0,
parameter SRAM3_INIT_38 = 256'h0,
parameter SRAM3_INIT_39 = 256'h0,
parameter SRAM3_INIT_40 = 256'h0,
parameter SRAM3_INIT_41 = 256'h0,
parameter SRAM3_INIT_42 = 256'h0,
parameter SRAM3_INIT_43 = 256'h0,
parameter SRAM3_INIT_44 = 256'h0,
parameter SRAM3_INIT_45 = 256'h0,
parameter SRAM3_INIT_46 = 256'h0,
parameter SRAM3_INIT_47 = 256'h0,
parameter SRAM3_INIT_48 = 256'h0,
parameter SRAM3_INIT_49 = 256'h0,
parameter SRAM3_INIT_50 = 256'h0,
parameter SRAM3_INIT_51 = 256'h0,
parameter SRAM3_INIT_52 = 256'h0,
parameter SRAM3_INIT_53 = 256'h0,
parameter SRAM3_INIT_54 = 256'h0,
parameter SRAM3_INIT_55 = 256'h0,
parameter SRAM3_INIT_56 = 256'h0,
parameter SRAM3_INIT_57 = 256'h0,
parameter SRAM3_INIT_58 = 256'h0,
parameter SRAM3_INIT_59 = 256'h0,
parameter SRAM3_INIT_60 = 256'h0,
parameter SRAM3_INIT_61 = 256'h0,
parameter SRAM3_INIT_62 = 256'h0,
parameter SRAM3_INIT_63 = 256'h0,
 
 
parameter SRAM4_INIT_0 = 256'h0,
parameter SRAM4_INIT_1 = 256'h0,
parameter SRAM4_INIT_2 = 256'h0,
parameter SRAM4_INIT_3 = 256'h0,
parameter SRAM4_INIT_4 = 256'h0,
parameter SRAM4_INIT_5 = 256'h0,
parameter SRAM4_INIT_6 = 256'h0,
parameter SRAM4_INIT_7 = 256'h0,
parameter SRAM4_INIT_8 = 256'h0,
parameter SRAM4_INIT_9 = 256'h0,
parameter SRAM4_INIT_10 = 256'h0,
parameter SRAM4_INIT_11 = 256'h0,
parameter SRAM4_INIT_12 = 256'h0,
parameter SRAM4_INIT_13 = 256'h0,
parameter SRAM4_INIT_14 = 256'h0,
parameter SRAM4_INIT_15 = 256'h0,
parameter SRAM4_INIT_16 = 256'h0,
parameter SRAM4_INIT_17 = 256'h0,
parameter SRAM4_INIT_18 = 256'h0,
parameter SRAM4_INIT_19 = 256'h0,
parameter SRAM4_INIT_20 = 256'h0,
parameter SRAM4_INIT_21 = 256'h0,
parameter SRAM4_INIT_22 = 256'h0,
parameter SRAM4_INIT_23 = 256'h0,
parameter SRAM4_INIT_24 = 256'h0,
parameter SRAM4_INIT_25 = 256'h0,
parameter SRAM4_INIT_26 = 256'h0,
parameter SRAM4_INIT_27 = 256'h0,
parameter SRAM4_INIT_28 = 256'h0,
parameter SRAM4_INIT_29 = 256'h0,
parameter SRAM4_INIT_30 = 256'h0,
parameter SRAM4_INIT_31 = 256'h0,
parameter SRAM4_INIT_32 = 256'h0,
parameter SRAM4_INIT_33 = 256'h0,
parameter SRAM4_INIT_34 = 256'h0,
parameter SRAM4_INIT_35 = 256'h0,
parameter SRAM4_INIT_36 = 256'h0,
parameter SRAM4_INIT_37 = 256'h0,
parameter SRAM4_INIT_38 = 256'h0,
parameter SRAM4_INIT_39 = 256'h0,
parameter SRAM4_INIT_40 = 256'h0,
parameter SRAM4_INIT_41 = 256'h0,
parameter SRAM4_INIT_42 = 256'h0,
parameter SRAM4_INIT_43 = 256'h0,
parameter SRAM4_INIT_44 = 256'h0,
parameter SRAM4_INIT_45 = 256'h0,
parameter SRAM4_INIT_46 = 256'h0,
parameter SRAM4_INIT_47 = 256'h0,
parameter SRAM4_INIT_48 = 256'h0,
parameter SRAM4_INIT_49 = 256'h0,
parameter SRAM4_INIT_50 = 256'h0,
parameter SRAM4_INIT_51 = 256'h0,
parameter SRAM4_INIT_52 = 256'h0,
parameter SRAM4_INIT_53 = 256'h0,
parameter SRAM4_INIT_54 = 256'h0,
parameter SRAM4_INIT_55 = 256'h0,
parameter SRAM4_INIT_56 = 256'h0,
parameter SRAM4_INIT_57 = 256'h0,
parameter SRAM4_INIT_58 = 256'h0,
parameter SRAM4_INIT_59 = 256'h0,
parameter SRAM4_INIT_60 = 256'h0,
parameter SRAM4_INIT_61 = 256'h0,
parameter SRAM4_INIT_62 = 256'h0,
parameter SRAM4_INIT_63 = 256'h0,
 
 
parameter SRAM5_INIT_0 = 256'h0,
parameter SRAM5_INIT_1 = 256'h0,
parameter SRAM5_INIT_2 = 256'h0,
parameter SRAM5_INIT_3 = 256'h0,
parameter SRAM5_INIT_4 = 256'h0,
parameter SRAM5_INIT_5 = 256'h0,
parameter SRAM5_INIT_6 = 256'h0,
parameter SRAM5_INIT_7 = 256'h0,
parameter SRAM5_INIT_8 = 256'h0,
parameter SRAM5_INIT_9 = 256'h0,
parameter SRAM5_INIT_10 = 256'h0,
parameter SRAM5_INIT_11 = 256'h0,
parameter SRAM5_INIT_12 = 256'h0,
parameter SRAM5_INIT_13 = 256'h0,
parameter SRAM5_INIT_14 = 256'h0,
parameter SRAM5_INIT_15 = 256'h0,
parameter SRAM5_INIT_16 = 256'h0,
parameter SRAM5_INIT_17 = 256'h0,
parameter SRAM5_INIT_18 = 256'h0,
parameter SRAM5_INIT_19 = 256'h0,
parameter SRAM5_INIT_20 = 256'h0,
parameter SRAM5_INIT_21 = 256'h0,
parameter SRAM5_INIT_22 = 256'h0,
parameter SRAM5_INIT_23 = 256'h0,
parameter SRAM5_INIT_24 = 256'h0,
parameter SRAM5_INIT_25 = 256'h0,
parameter SRAM5_INIT_26 = 256'h0,
parameter SRAM5_INIT_27 = 256'h0,
parameter SRAM5_INIT_28 = 256'h0,
parameter SRAM5_INIT_29 = 256'h0,
parameter SRAM5_INIT_30 = 256'h0,
parameter SRAM5_INIT_31 = 256'h0,
parameter SRAM5_INIT_32 = 256'h0,
parameter SRAM5_INIT_33 = 256'h0,
parameter SRAM5_INIT_34 = 256'h0,
parameter SRAM5_INIT_35 = 256'h0,
parameter SRAM5_INIT_36 = 256'h0,
parameter SRAM5_INIT_37 = 256'h0,
parameter SRAM5_INIT_38 = 256'h0,
parameter SRAM5_INIT_39 = 256'h0,
parameter SRAM5_INIT_40 = 256'h0,
parameter SRAM5_INIT_41 = 256'h0,
parameter SRAM5_INIT_42 = 256'h0,
parameter SRAM5_INIT_43 = 256'h0,
parameter SRAM5_INIT_44 = 256'h0,
parameter SRAM5_INIT_45 = 256'h0,
parameter SRAM5_INIT_46 = 256'h0,
parameter SRAM5_INIT_47 = 256'h0,
parameter SRAM5_INIT_48 = 256'h0,
parameter SRAM5_INIT_49 = 256'h0,
parameter SRAM5_INIT_50 = 256'h0,
parameter SRAM5_INIT_51 = 256'h0,
parameter SRAM5_INIT_52 = 256'h0,
parameter SRAM5_INIT_53 = 256'h0,
parameter SRAM5_INIT_54 = 256'h0,
parameter SRAM5_INIT_55 = 256'h0,
parameter SRAM5_INIT_56 = 256'h0,
parameter SRAM5_INIT_57 = 256'h0,
parameter SRAM5_INIT_58 = 256'h0,
parameter SRAM5_INIT_59 = 256'h0,
parameter SRAM5_INIT_60 = 256'h0,
parameter SRAM5_INIT_61 = 256'h0,
parameter SRAM5_INIT_62 = 256'h0,
parameter SRAM5_INIT_63 = 256'h0,
 
 
 
parameter SRAM6_INIT_0 = 256'h0,
parameter SRAM6_INIT_1 = 256'h0,
parameter SRAM6_INIT_2 = 256'h0,
parameter SRAM6_INIT_3 = 256'h0,
parameter SRAM6_INIT_4 = 256'h0,
parameter SRAM6_INIT_5 = 256'h0,
parameter SRAM6_INIT_6 = 256'h0,
parameter SRAM6_INIT_7 = 256'h0,
parameter SRAM6_INIT_8 = 256'h0,
parameter SRAM6_INIT_9 = 256'h0,
parameter SRAM6_INIT_10 = 256'h0,
parameter SRAM6_INIT_11 = 256'h0,
parameter SRAM6_INIT_12 = 256'h0,
parameter SRAM6_INIT_13 = 256'h0,
parameter SRAM6_INIT_14 = 256'h0,
parameter SRAM6_INIT_15 = 256'h0,
parameter SRAM6_INIT_16 = 256'h0,
parameter SRAM6_INIT_17 = 256'h0,
parameter SRAM6_INIT_18 = 256'h0,
parameter SRAM6_INIT_19 = 256'h0,
parameter SRAM6_INIT_20 = 256'h0,
parameter SRAM6_INIT_21 = 256'h0,
parameter SRAM6_INIT_22 = 256'h0,
parameter SRAM6_INIT_23 = 256'h0,
parameter SRAM6_INIT_24 = 256'h0,
parameter SRAM6_INIT_25 = 256'h0,
parameter SRAM6_INIT_26 = 256'h0,
parameter SRAM6_INIT_27 = 256'h0,
parameter SRAM6_INIT_28 = 256'h0,
parameter SRAM6_INIT_29 = 256'h0,
parameter SRAM6_INIT_30 = 256'h0,
parameter SRAM6_INIT_31 = 256'h0,
parameter SRAM6_INIT_32 = 256'h0,
parameter SRAM6_INIT_33 = 256'h0,
parameter SRAM6_INIT_34 = 256'h0,
parameter SRAM6_INIT_35 = 256'h0,
parameter SRAM6_INIT_36 = 256'h0,
parameter SRAM6_INIT_37 = 256'h0,
parameter SRAM6_INIT_38 = 256'h0,
parameter SRAM6_INIT_39 = 256'h0,
parameter SRAM6_INIT_40 = 256'h0,
parameter SRAM6_INIT_41 = 256'h0,
parameter SRAM6_INIT_42 = 256'h0,
parameter SRAM6_INIT_43 = 256'h0,
parameter SRAM6_INIT_44 = 256'h0,
parameter SRAM6_INIT_45 = 256'h0,
parameter SRAM6_INIT_46 = 256'h0,
parameter SRAM6_INIT_47 = 256'h0,
parameter SRAM6_INIT_48 = 256'h0,
parameter SRAM6_INIT_49 = 256'h0,
parameter SRAM6_INIT_50 = 256'h0,
parameter SRAM6_INIT_51 = 256'h0,
parameter SRAM6_INIT_52 = 256'h0,
parameter SRAM6_INIT_53 = 256'h0,
parameter SRAM6_INIT_54 = 256'h0,
parameter SRAM6_INIT_55 = 256'h0,
parameter SRAM6_INIT_56 = 256'h0,
parameter SRAM6_INIT_57 = 256'h0,
parameter SRAM6_INIT_58 = 256'h0,
parameter SRAM6_INIT_59 = 256'h0,
parameter SRAM6_INIT_60 = 256'h0,
parameter SRAM6_INIT_61 = 256'h0,
parameter SRAM6_INIT_62 = 256'h0,
parameter SRAM6_INIT_63 = 256'h0,
 
parameter SRAM7_INIT_0 = 256'h0,
parameter SRAM7_INIT_1 = 256'h0,
parameter SRAM7_INIT_2 = 256'h0,
parameter SRAM7_INIT_3 = 256'h0,
parameter SRAM7_INIT_4 = 256'h0,
parameter SRAM7_INIT_5 = 256'h0,
parameter SRAM7_INIT_6 = 256'h0,
parameter SRAM7_INIT_7 = 256'h0,
parameter SRAM7_INIT_8 = 256'h0,
parameter SRAM7_INIT_9 = 256'h0,
parameter SRAM7_INIT_10 = 256'h0,
parameter SRAM7_INIT_11 = 256'h0,
parameter SRAM7_INIT_12 = 256'h0,
parameter SRAM7_INIT_13 = 256'h0,
parameter SRAM7_INIT_14 = 256'h0,
parameter SRAM7_INIT_15 = 256'h0,
parameter SRAM7_INIT_16 = 256'h0,
parameter SRAM7_INIT_17 = 256'h0,
parameter SRAM7_INIT_18 = 256'h0,
parameter SRAM7_INIT_19 = 256'h0,
parameter SRAM7_INIT_20 = 256'h0,
parameter SRAM7_INIT_21 = 256'h0,
parameter SRAM7_INIT_22 = 256'h0,
parameter SRAM7_INIT_23 = 256'h0,
parameter SRAM7_INIT_24 = 256'h0,
parameter SRAM7_INIT_25 = 256'h0,
parameter SRAM7_INIT_26 = 256'h0,
parameter SRAM7_INIT_27 = 256'h0,
parameter SRAM7_INIT_28 = 256'h0,
parameter SRAM7_INIT_29 = 256'h0,
parameter SRAM7_INIT_30 = 256'h0,
parameter SRAM7_INIT_31 = 256'h0,
parameter SRAM7_INIT_32 = 256'h0,
parameter SRAM7_INIT_33 = 256'h0,
parameter SRAM7_INIT_34 = 256'h0,
parameter SRAM7_INIT_35 = 256'h0,
parameter SRAM7_INIT_36 = 256'h0,
parameter SRAM7_INIT_37 = 256'h0,
parameter SRAM7_INIT_38 = 256'h0,
parameter SRAM7_INIT_39 = 256'h0,
parameter SRAM7_INIT_40 = 256'h0,
parameter SRAM7_INIT_41 = 256'h0,
parameter SRAM7_INIT_42 = 256'h0,
parameter SRAM7_INIT_43 = 256'h0,
parameter SRAM7_INIT_44 = 256'h0,
parameter SRAM7_INIT_45 = 256'h0,
parameter SRAM7_INIT_46 = 256'h0,
parameter SRAM7_INIT_47 = 256'h0,
parameter SRAM7_INIT_48 = 256'h0,
parameter SRAM7_INIT_49 = 256'h0,
parameter SRAM7_INIT_50 = 256'h0,
parameter SRAM7_INIT_51 = 256'h0,
parameter SRAM7_INIT_52 = 256'h0,
parameter SRAM7_INIT_53 = 256'h0,
parameter SRAM7_INIT_54 = 256'h0,
parameter SRAM7_INIT_55 = 256'h0,
parameter SRAM7_INIT_56 = 256'h0,
parameter SRAM7_INIT_57 = 256'h0,
parameter SRAM7_INIT_58 = 256'h0,
parameter SRAM7_INIT_59 = 256'h0,
parameter SRAM7_INIT_60 = 256'h0,
parameter SRAM7_INIT_61 = 256'h0,
parameter SRAM7_INIT_62 = 256'h0,
parameter SRAM7_INIT_63 = 256'h0,
 
parameter UNUSED = 1'd1
 
)
 
(
input i_clk,
input [127:0] i_write_data,
input i_write_enable,
input [9:0] i_address,
input [15:0] i_byte_enable,
output [127:0] o_read_data
 
);
 
wire [23:0] nc24_00, nc24_01, nc24_02, nc24_03;
wire [15:0] wea_b0;
wire [15:0] wea_b1;
wire [127:0] read_data_b0;
wire [127:0] read_data_b1;
reg address_9_r;
 
 
always @(posedge i_clk)
address_9_r <= i_address[9];
 
assign wea_b0 = {16{i_write_enable & ~i_address[9]}} & i_byte_enable;
assign wea_b1 = {16{i_write_enable & i_address[9]}} & i_byte_enable;
assign o_read_data = address_9_r ? read_data_b1 : read_data_b0;
 
 
// -----------------------------------------
// Bank 0 - first 8kb block
// -----------------------------------------
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM0_INIT_0 ),
.INIT_01 ( SRAM0_INIT_1 ),
.INIT_02 ( SRAM0_INIT_2 ),
.INIT_03 ( SRAM0_INIT_3 ),
.INIT_04 ( SRAM0_INIT_4 ),
.INIT_05 ( SRAM0_INIT_5 ),
.INIT_06 ( SRAM0_INIT_6 ),
.INIT_07 ( SRAM0_INIT_7 ),
.INIT_08 ( SRAM0_INIT_8 ),
.INIT_09 ( SRAM0_INIT_9 ),
.INIT_0A ( SRAM0_INIT_10 ),
.INIT_0B ( SRAM0_INIT_11 ),
.INIT_0C ( SRAM0_INIT_12 ),
.INIT_0D ( SRAM0_INIT_13 ),
.INIT_0E ( SRAM0_INIT_14 ),
.INIT_0F ( SRAM0_INIT_15 ),
.INIT_10 ( SRAM0_INIT_16 ),
.INIT_11 ( SRAM0_INIT_17 ),
.INIT_12 ( SRAM0_INIT_18 ),
.INIT_13 ( SRAM0_INIT_19 ),
.INIT_14 ( SRAM0_INIT_20 ),
.INIT_15 ( SRAM0_INIT_21 ),
.INIT_16 ( SRAM0_INIT_22 ),
.INIT_17 ( SRAM0_INIT_23 ),
.INIT_18 ( SRAM0_INIT_24 ),
.INIT_19 ( SRAM0_INIT_25 ),
.INIT_1A ( SRAM0_INIT_26 ),
.INIT_1B ( SRAM0_INIT_27 ),
.INIT_1C ( SRAM0_INIT_28 ),
.INIT_1D ( SRAM0_INIT_29 ),
.INIT_1E ( SRAM0_INIT_30 ),
.INIT_1F ( SRAM0_INIT_31 ),
.INIT_20 ( SRAM0_INIT_32 ),
.INIT_21 ( SRAM0_INIT_33 ),
.INIT_22 ( SRAM0_INIT_34 ),
.INIT_23 ( SRAM0_INIT_35 ),
.INIT_24 ( SRAM0_INIT_36 ),
.INIT_25 ( SRAM0_INIT_37 ),
.INIT_26 ( SRAM0_INIT_38 ),
.INIT_27 ( SRAM0_INIT_39 ),
.INIT_28 ( SRAM0_INIT_40 ),
.INIT_29 ( SRAM0_INIT_41 ),
.INIT_2A ( SRAM0_INIT_42 ),
.INIT_2B ( SRAM0_INIT_43 ),
.INIT_2C ( SRAM0_INIT_44 ),
.INIT_2D ( SRAM0_INIT_45 ),
.INIT_2E ( SRAM0_INIT_46 ),
.INIT_2F ( SRAM0_INIT_47 ),
.INIT_30 ( SRAM0_INIT_48 ),
.INIT_31 ( SRAM0_INIT_49 ),
.INIT_32 ( SRAM0_INIT_50 ),
.INIT_33 ( SRAM0_INIT_51 ),
.INIT_34 ( SRAM0_INIT_52 ),
.INIT_35 ( SRAM0_INIT_53 ),
.INIT_36 ( SRAM0_INIT_54 ),
.INIT_37 ( SRAM0_INIT_55 ),
.INIT_38 ( SRAM0_INIT_56 ),
.INIT_39 ( SRAM0_INIT_57 ),
.INIT_3A ( SRAM0_INIT_58 ),
.INIT_3B ( SRAM0_INIT_59 ),
.INIT_3C ( SRAM0_INIT_60 ),
.INIT_3D ( SRAM0_INIT_61 ),
.INIT_3E ( SRAM0_INIT_62 ),
.INIT_3F ( SRAM0_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram0 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[3:0] ),
.DOA ( read_data_b0[31:0] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[31:0] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM1_INIT_0 ),
.INIT_01 ( SRAM1_INIT_1 ),
.INIT_02 ( SRAM1_INIT_2 ),
.INIT_03 ( SRAM1_INIT_3 ),
.INIT_04 ( SRAM1_INIT_4 ),
.INIT_05 ( SRAM1_INIT_5 ),
.INIT_06 ( SRAM1_INIT_6 ),
.INIT_07 ( SRAM1_INIT_7 ),
.INIT_08 ( SRAM1_INIT_8 ),
.INIT_09 ( SRAM1_INIT_9 ),
.INIT_0A ( SRAM1_INIT_10 ),
.INIT_0B ( SRAM1_INIT_11 ),
.INIT_0C ( SRAM1_INIT_12 ),
.INIT_0D ( SRAM1_INIT_13 ),
.INIT_0E ( SRAM1_INIT_14 ),
.INIT_0F ( SRAM1_INIT_15 ),
.INIT_10 ( SRAM1_INIT_16 ),
.INIT_11 ( SRAM1_INIT_17 ),
.INIT_12 ( SRAM1_INIT_18 ),
.INIT_13 ( SRAM1_INIT_19 ),
.INIT_14 ( SRAM1_INIT_20 ),
.INIT_15 ( SRAM1_INIT_21 ),
.INIT_16 ( SRAM1_INIT_22 ),
.INIT_17 ( SRAM1_INIT_23 ),
.INIT_18 ( SRAM1_INIT_24 ),
.INIT_19 ( SRAM1_INIT_25 ),
.INIT_1A ( SRAM1_INIT_26 ),
.INIT_1B ( SRAM1_INIT_27 ),
.INIT_1C ( SRAM1_INIT_28 ),
.INIT_1D ( SRAM1_INIT_29 ),
.INIT_1E ( SRAM1_INIT_30 ),
.INIT_1F ( SRAM1_INIT_31 ),
.INIT_20 ( SRAM1_INIT_32 ),
.INIT_21 ( SRAM1_INIT_33 ),
.INIT_22 ( SRAM1_INIT_34 ),
.INIT_23 ( SRAM1_INIT_35 ),
.INIT_24 ( SRAM1_INIT_36 ),
.INIT_25 ( SRAM1_INIT_37 ),
.INIT_26 ( SRAM1_INIT_38 ),
.INIT_27 ( SRAM1_INIT_39 ),
.INIT_28 ( SRAM1_INIT_40 ),
.INIT_29 ( SRAM1_INIT_41 ),
.INIT_2A ( SRAM1_INIT_42 ),
.INIT_2B ( SRAM1_INIT_43 ),
.INIT_2C ( SRAM1_INIT_44 ),
.INIT_2D ( SRAM1_INIT_45 ),
.INIT_2E ( SRAM1_INIT_46 ),
.INIT_2F ( SRAM1_INIT_47 ),
.INIT_30 ( SRAM1_INIT_48 ),
.INIT_31 ( SRAM1_INIT_49 ),
.INIT_32 ( SRAM1_INIT_50 ),
.INIT_33 ( SRAM1_INIT_51 ),
.INIT_34 ( SRAM1_INIT_52 ),
.INIT_35 ( SRAM1_INIT_53 ),
.INIT_36 ( SRAM1_INIT_54 ),
.INIT_37 ( SRAM1_INIT_55 ),
.INIT_38 ( SRAM1_INIT_56 ),
.INIT_39 ( SRAM1_INIT_57 ),
.INIT_3A ( SRAM1_INIT_58 ),
.INIT_3B ( SRAM1_INIT_59 ),
.INIT_3C ( SRAM1_INIT_60 ),
.INIT_3D ( SRAM1_INIT_61 ),
.INIT_3E ( SRAM1_INIT_62 ),
.INIT_3F ( SRAM1_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram1 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[7:4] ),
.DOA ( read_data_b0[63:32] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[63:32] )
);
 
 
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM2_INIT_0 ),
.INIT_01 ( SRAM2_INIT_1 ),
.INIT_02 ( SRAM2_INIT_2 ),
.INIT_03 ( SRAM2_INIT_3 ),
.INIT_04 ( SRAM2_INIT_4 ),
.INIT_05 ( SRAM2_INIT_5 ),
.INIT_06 ( SRAM2_INIT_6 ),
.INIT_07 ( SRAM2_INIT_7 ),
.INIT_08 ( SRAM2_INIT_8 ),
.INIT_09 ( SRAM2_INIT_9 ),
.INIT_0A ( SRAM2_INIT_10 ),
.INIT_0B ( SRAM2_INIT_11 ),
.INIT_0C ( SRAM2_INIT_12 ),
.INIT_0D ( SRAM2_INIT_13 ),
.INIT_0E ( SRAM2_INIT_14 ),
.INIT_0F ( SRAM2_INIT_15 ),
.INIT_10 ( SRAM2_INIT_16 ),
.INIT_11 ( SRAM2_INIT_17 ),
.INIT_12 ( SRAM2_INIT_18 ),
.INIT_13 ( SRAM2_INIT_19 ),
.INIT_14 ( SRAM2_INIT_20 ),
.INIT_15 ( SRAM2_INIT_21 ),
.INIT_16 ( SRAM2_INIT_22 ),
.INIT_17 ( SRAM2_INIT_23 ),
.INIT_18 ( SRAM2_INIT_24 ),
.INIT_19 ( SRAM2_INIT_25 ),
.INIT_1A ( SRAM2_INIT_26 ),
.INIT_1B ( SRAM2_INIT_27 ),
.INIT_1C ( SRAM2_INIT_28 ),
.INIT_1D ( SRAM2_INIT_29 ),
.INIT_1E ( SRAM2_INIT_30 ),
.INIT_1F ( SRAM2_INIT_31 ),
.INIT_20 ( SRAM2_INIT_32 ),
.INIT_21 ( SRAM2_INIT_33 ),
.INIT_22 ( SRAM2_INIT_34 ),
.INIT_23 ( SRAM2_INIT_35 ),
.INIT_24 ( SRAM2_INIT_36 ),
.INIT_25 ( SRAM2_INIT_37 ),
.INIT_26 ( SRAM2_INIT_38 ),
.INIT_27 ( SRAM2_INIT_39 ),
.INIT_28 ( SRAM2_INIT_40 ),
.INIT_29 ( SRAM2_INIT_41 ),
.INIT_2A ( SRAM2_INIT_42 ),
.INIT_2B ( SRAM2_INIT_43 ),
.INIT_2C ( SRAM2_INIT_44 ),
.INIT_2D ( SRAM2_INIT_45 ),
.INIT_2E ( SRAM2_INIT_46 ),
.INIT_2F ( SRAM2_INIT_47 ),
.INIT_30 ( SRAM2_INIT_48 ),
.INIT_31 ( SRAM2_INIT_49 ),
.INIT_32 ( SRAM2_INIT_50 ),
.INIT_33 ( SRAM2_INIT_51 ),
.INIT_34 ( SRAM2_INIT_52 ),
.INIT_35 ( SRAM2_INIT_53 ),
.INIT_36 ( SRAM2_INIT_54 ),
.INIT_37 ( SRAM2_INIT_55 ),
.INIT_38 ( SRAM2_INIT_56 ),
.INIT_39 ( SRAM2_INIT_57 ),
.INIT_3A ( SRAM2_INIT_58 ),
.INIT_3B ( SRAM2_INIT_59 ),
.INIT_3C ( SRAM2_INIT_60 ),
.INIT_3D ( SRAM2_INIT_61 ),
.INIT_3E ( SRAM2_INIT_62 ),
.INIT_3F ( SRAM2_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram2 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[11:8] ),
.DOA ( read_data_b0[95:64] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[95:64] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM3_INIT_0 ),
.INIT_01 ( SRAM3_INIT_1 ),
.INIT_02 ( SRAM3_INIT_2 ),
.INIT_03 ( SRAM3_INIT_3 ),
.INIT_04 ( SRAM3_INIT_4 ),
.INIT_05 ( SRAM3_INIT_5 ),
.INIT_06 ( SRAM3_INIT_6 ),
.INIT_07 ( SRAM3_INIT_7 ),
.INIT_08 ( SRAM3_INIT_8 ),
.INIT_09 ( SRAM3_INIT_9 ),
.INIT_0A ( SRAM3_INIT_10 ),
.INIT_0B ( SRAM3_INIT_11 ),
.INIT_0C ( SRAM3_INIT_12 ),
.INIT_0D ( SRAM3_INIT_13 ),
.INIT_0E ( SRAM3_INIT_14 ),
.INIT_0F ( SRAM3_INIT_15 ),
.INIT_10 ( SRAM3_INIT_16 ),
.INIT_11 ( SRAM3_INIT_17 ),
.INIT_12 ( SRAM3_INIT_18 ),
.INIT_13 ( SRAM3_INIT_19 ),
.INIT_14 ( SRAM3_INIT_20 ),
.INIT_15 ( SRAM3_INIT_21 ),
.INIT_16 ( SRAM3_INIT_22 ),
.INIT_17 ( SRAM3_INIT_23 ),
.INIT_18 ( SRAM3_INIT_24 ),
.INIT_19 ( SRAM3_INIT_25 ),
.INIT_1A ( SRAM3_INIT_26 ),
.INIT_1B ( SRAM3_INIT_27 ),
.INIT_1C ( SRAM3_INIT_28 ),
.INIT_1D ( SRAM3_INIT_29 ),
.INIT_1E ( SRAM3_INIT_30 ),
.INIT_1F ( SRAM3_INIT_31 ),
.INIT_20 ( SRAM3_INIT_32 ),
.INIT_21 ( SRAM3_INIT_33 ),
.INIT_22 ( SRAM3_INIT_34 ),
.INIT_23 ( SRAM3_INIT_35 ),
.INIT_24 ( SRAM3_INIT_36 ),
.INIT_25 ( SRAM3_INIT_37 ),
.INIT_26 ( SRAM3_INIT_38 ),
.INIT_27 ( SRAM3_INIT_39 ),
.INIT_28 ( SRAM3_INIT_40 ),
.INIT_29 ( SRAM3_INIT_41 ),
.INIT_2A ( SRAM3_INIT_42 ),
.INIT_2B ( SRAM3_INIT_43 ),
.INIT_2C ( SRAM3_INIT_44 ),
.INIT_2D ( SRAM3_INIT_45 ),
.INIT_2E ( SRAM3_INIT_46 ),
.INIT_2F ( SRAM3_INIT_47 ),
.INIT_30 ( SRAM3_INIT_48 ),
.INIT_31 ( SRAM3_INIT_49 ),
.INIT_32 ( SRAM3_INIT_50 ),
.INIT_33 ( SRAM3_INIT_51 ),
.INIT_34 ( SRAM3_INIT_52 ),
.INIT_35 ( SRAM3_INIT_53 ),
.INIT_36 ( SRAM3_INIT_54 ),
.INIT_37 ( SRAM3_INIT_55 ),
.INIT_38 ( SRAM3_INIT_56 ),
.INIT_39 ( SRAM3_INIT_57 ),
.INIT_3A ( SRAM3_INIT_58 ),
.INIT_3B ( SRAM3_INIT_59 ),
.INIT_3C ( SRAM3_INIT_60 ),
.INIT_3D ( SRAM3_INIT_61 ),
.INIT_3E ( SRAM3_INIT_62 ),
.INIT_3F ( SRAM3_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram3 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b0[15:12] ),
.DOA ( read_data_b0[127:96] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[127:96] )
);
 
 
// -----------------------------------------
// Bank 1 - second 8kb block
// -----------------------------------------
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM4_INIT_0 ),
.INIT_01 ( SRAM4_INIT_1 ),
.INIT_02 ( SRAM4_INIT_2 ),
.INIT_03 ( SRAM4_INIT_3 ),
.INIT_04 ( SRAM4_INIT_4 ),
.INIT_05 ( SRAM4_INIT_5 ),
.INIT_06 ( SRAM4_INIT_6 ),
.INIT_07 ( SRAM4_INIT_7 ),
.INIT_08 ( SRAM4_INIT_8 ),
.INIT_09 ( SRAM4_INIT_9 ),
.INIT_0A ( SRAM4_INIT_10 ),
.INIT_0B ( SRAM4_INIT_11 ),
.INIT_0C ( SRAM4_INIT_12 ),
.INIT_0D ( SRAM4_INIT_13 ),
.INIT_0E ( SRAM4_INIT_14 ),
.INIT_0F ( SRAM4_INIT_15 ),
.INIT_10 ( SRAM4_INIT_16 ),
.INIT_11 ( SRAM4_INIT_17 ),
.INIT_12 ( SRAM4_INIT_18 ),
.INIT_13 ( SRAM4_INIT_19 ),
.INIT_14 ( SRAM4_INIT_20 ),
.INIT_15 ( SRAM4_INIT_21 ),
.INIT_16 ( SRAM4_INIT_22 ),
.INIT_17 ( SRAM4_INIT_23 ),
.INIT_18 ( SRAM4_INIT_24 ),
.INIT_19 ( SRAM4_INIT_25 ),
.INIT_1A ( SRAM4_INIT_26 ),
.INIT_1B ( SRAM4_INIT_27 ),
.INIT_1C ( SRAM4_INIT_28 ),
.INIT_1D ( SRAM4_INIT_29 ),
.INIT_1E ( SRAM4_INIT_30 ),
.INIT_1F ( SRAM4_INIT_31 ),
.INIT_20 ( SRAM4_INIT_32 ),
.INIT_21 ( SRAM4_INIT_33 ),
.INIT_22 ( SRAM4_INIT_34 ),
.INIT_23 ( SRAM4_INIT_35 ),
.INIT_24 ( SRAM4_INIT_36 ),
.INIT_25 ( SRAM4_INIT_37 ),
.INIT_26 ( SRAM4_INIT_38 ),
.INIT_27 ( SRAM4_INIT_39 ),
.INIT_28 ( SRAM4_INIT_40 ),
.INIT_29 ( SRAM4_INIT_41 ),
.INIT_2A ( SRAM4_INIT_42 ),
.INIT_2B ( SRAM4_INIT_43 ),
.INIT_2C ( SRAM4_INIT_44 ),
.INIT_2D ( SRAM4_INIT_45 ),
.INIT_2E ( SRAM4_INIT_46 ),
.INIT_2F ( SRAM4_INIT_47 ),
.INIT_30 ( SRAM4_INIT_48 ),
.INIT_31 ( SRAM4_INIT_49 ),
.INIT_32 ( SRAM4_INIT_50 ),
.INIT_33 ( SRAM4_INIT_51 ),
.INIT_34 ( SRAM4_INIT_52 ),
.INIT_35 ( SRAM4_INIT_53 ),
.INIT_36 ( SRAM4_INIT_54 ),
.INIT_37 ( SRAM4_INIT_55 ),
.INIT_38 ( SRAM4_INIT_56 ),
.INIT_39 ( SRAM4_INIT_57 ),
.INIT_3A ( SRAM4_INIT_58 ),
.INIT_3B ( SRAM4_INIT_59 ),
.INIT_3C ( SRAM4_INIT_60 ),
.INIT_3D ( SRAM4_INIT_61 ),
.INIT_3E ( SRAM4_INIT_62 ),
.INIT_3F ( SRAM4_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram4 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[3:0] ),
.DOA ( read_data_b1[31:0] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[31:0] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM5_INIT_0 ),
.INIT_01 ( SRAM5_INIT_1 ),
.INIT_02 ( SRAM5_INIT_2 ),
.INIT_03 ( SRAM5_INIT_3 ),
.INIT_04 ( SRAM5_INIT_4 ),
.INIT_05 ( SRAM5_INIT_5 ),
.INIT_06 ( SRAM5_INIT_6 ),
.INIT_07 ( SRAM5_INIT_7 ),
.INIT_08 ( SRAM5_INIT_8 ),
.INIT_09 ( SRAM5_INIT_9 ),
.INIT_0A ( SRAM5_INIT_10 ),
.INIT_0B ( SRAM5_INIT_11 ),
.INIT_0C ( SRAM5_INIT_12 ),
.INIT_0D ( SRAM5_INIT_13 ),
.INIT_0E ( SRAM5_INIT_14 ),
.INIT_0F ( SRAM5_INIT_15 ),
.INIT_10 ( SRAM5_INIT_16 ),
.INIT_11 ( SRAM5_INIT_17 ),
.INIT_12 ( SRAM5_INIT_18 ),
.INIT_13 ( SRAM5_INIT_19 ),
.INIT_14 ( SRAM5_INIT_20 ),
.INIT_15 ( SRAM5_INIT_21 ),
.INIT_16 ( SRAM5_INIT_22 ),
.INIT_17 ( SRAM5_INIT_23 ),
.INIT_18 ( SRAM5_INIT_24 ),
.INIT_19 ( SRAM5_INIT_25 ),
.INIT_1A ( SRAM5_INIT_26 ),
.INIT_1B ( SRAM5_INIT_27 ),
.INIT_1C ( SRAM5_INIT_28 ),
.INIT_1D ( SRAM5_INIT_29 ),
.INIT_1E ( SRAM5_INIT_30 ),
.INIT_1F ( SRAM5_INIT_31 ),
.INIT_20 ( SRAM5_INIT_32 ),
.INIT_21 ( SRAM5_INIT_33 ),
.INIT_22 ( SRAM5_INIT_34 ),
.INIT_23 ( SRAM5_INIT_35 ),
.INIT_24 ( SRAM5_INIT_36 ),
.INIT_25 ( SRAM5_INIT_37 ),
.INIT_26 ( SRAM5_INIT_38 ),
.INIT_27 ( SRAM5_INIT_39 ),
.INIT_28 ( SRAM5_INIT_40 ),
.INIT_29 ( SRAM5_INIT_41 ),
.INIT_2A ( SRAM5_INIT_42 ),
.INIT_2B ( SRAM5_INIT_43 ),
.INIT_2C ( SRAM5_INIT_44 ),
.INIT_2D ( SRAM5_INIT_45 ),
.INIT_2E ( SRAM5_INIT_46 ),
.INIT_2F ( SRAM5_INIT_47 ),
.INIT_30 ( SRAM5_INIT_48 ),
.INIT_31 ( SRAM5_INIT_49 ),
.INIT_32 ( SRAM5_INIT_50 ),
.INIT_33 ( SRAM5_INIT_51 ),
.INIT_34 ( SRAM5_INIT_52 ),
.INIT_35 ( SRAM5_INIT_53 ),
.INIT_36 ( SRAM5_INIT_54 ),
.INIT_37 ( SRAM5_INIT_55 ),
.INIT_38 ( SRAM5_INIT_56 ),
.INIT_39 ( SRAM5_INIT_57 ),
.INIT_3A ( SRAM5_INIT_58 ),
.INIT_3B ( SRAM5_INIT_59 ),
.INIT_3C ( SRAM5_INIT_60 ),
.INIT_3D ( SRAM5_INIT_61 ),
.INIT_3E ( SRAM5_INIT_62 ),
.INIT_3F ( SRAM5_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram5 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[7:4] ),
.DOA ( read_data_b1[63:32] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[63:32] )
);
 
 
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM6_INIT_0 ),
.INIT_01 ( SRAM6_INIT_1 ),
.INIT_02 ( SRAM6_INIT_2 ),
.INIT_03 ( SRAM6_INIT_3 ),
.INIT_04 ( SRAM6_INIT_4 ),
.INIT_05 ( SRAM6_INIT_5 ),
.INIT_06 ( SRAM6_INIT_6 ),
.INIT_07 ( SRAM6_INIT_7 ),
.INIT_08 ( SRAM6_INIT_8 ),
.INIT_09 ( SRAM6_INIT_9 ),
.INIT_0A ( SRAM6_INIT_10 ),
.INIT_0B ( SRAM6_INIT_11 ),
.INIT_0C ( SRAM6_INIT_12 ),
.INIT_0D ( SRAM6_INIT_13 ),
.INIT_0E ( SRAM6_INIT_14 ),
.INIT_0F ( SRAM6_INIT_15 ),
.INIT_10 ( SRAM6_INIT_16 ),
.INIT_11 ( SRAM6_INIT_17 ),
.INIT_12 ( SRAM6_INIT_18 ),
.INIT_13 ( SRAM6_INIT_19 ),
.INIT_14 ( SRAM6_INIT_20 ),
.INIT_15 ( SRAM6_INIT_21 ),
.INIT_16 ( SRAM6_INIT_22 ),
.INIT_17 ( SRAM6_INIT_23 ),
.INIT_18 ( SRAM6_INIT_24 ),
.INIT_19 ( SRAM6_INIT_25 ),
.INIT_1A ( SRAM6_INIT_26 ),
.INIT_1B ( SRAM6_INIT_27 ),
.INIT_1C ( SRAM6_INIT_28 ),
.INIT_1D ( SRAM6_INIT_29 ),
.INIT_1E ( SRAM6_INIT_30 ),
.INIT_1F ( SRAM6_INIT_31 ),
.INIT_20 ( SRAM6_INIT_32 ),
.INIT_21 ( SRAM6_INIT_33 ),
.INIT_22 ( SRAM6_INIT_34 ),
.INIT_23 ( SRAM6_INIT_35 ),
.INIT_24 ( SRAM6_INIT_36 ),
.INIT_25 ( SRAM6_INIT_37 ),
.INIT_26 ( SRAM6_INIT_38 ),
.INIT_27 ( SRAM6_INIT_39 ),
.INIT_28 ( SRAM6_INIT_40 ),
.INIT_29 ( SRAM6_INIT_41 ),
.INIT_2A ( SRAM6_INIT_42 ),
.INIT_2B ( SRAM6_INIT_43 ),
.INIT_2C ( SRAM6_INIT_44 ),
.INIT_2D ( SRAM6_INIT_45 ),
.INIT_2E ( SRAM6_INIT_46 ),
.INIT_2F ( SRAM6_INIT_47 ),
.INIT_30 ( SRAM6_INIT_48 ),
.INIT_31 ( SRAM6_INIT_49 ),
.INIT_32 ( SRAM6_INIT_50 ),
.INIT_33 ( SRAM6_INIT_51 ),
.INIT_34 ( SRAM6_INIT_52 ),
.INIT_35 ( SRAM6_INIT_53 ),
.INIT_36 ( SRAM6_INIT_54 ),
.INIT_37 ( SRAM6_INIT_55 ),
.INIT_38 ( SRAM6_INIT_56 ),
.INIT_39 ( SRAM6_INIT_57 ),
.INIT_3A ( SRAM6_INIT_58 ),
.INIT_3B ( SRAM6_INIT_59 ),
.INIT_3C ( SRAM6_INIT_60 ),
.INIT_3D ( SRAM6_INIT_61 ),
.INIT_3E ( SRAM6_INIT_62 ),
.INIT_3F ( SRAM6_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram6 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[11:8] ),
.DOA ( read_data_b1[95:64] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[95:64] )
);
RAMB16BWER #(
.DATA_WIDTH_A ( 36 ),
.DATA_WIDTH_B ( 36 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0 ),
.INITP_01 ( 256'h0 ),
.INITP_02 ( 256'h0 ),
.INITP_03 ( 256'h0 ),
.INITP_04 ( 256'h0 ),
.INITP_05 ( 256'h0 ),
.INITP_06 ( 256'h0 ),
.INITP_07 ( 256'h0 ),
 
.INIT_00 ( SRAM7_INIT_0 ),
.INIT_01 ( SRAM7_INIT_1 ),
.INIT_02 ( SRAM7_INIT_2 ),
.INIT_03 ( SRAM7_INIT_3 ),
.INIT_04 ( SRAM7_INIT_4 ),
.INIT_05 ( SRAM7_INIT_5 ),
.INIT_06 ( SRAM7_INIT_6 ),
.INIT_07 ( SRAM7_INIT_7 ),
.INIT_08 ( SRAM7_INIT_8 ),
.INIT_09 ( SRAM7_INIT_9 ),
.INIT_0A ( SRAM7_INIT_10 ),
.INIT_0B ( SRAM7_INIT_11 ),
.INIT_0C ( SRAM7_INIT_12 ),
.INIT_0D ( SRAM7_INIT_13 ),
.INIT_0E ( SRAM7_INIT_14 ),
.INIT_0F ( SRAM7_INIT_15 ),
.INIT_10 ( SRAM7_INIT_16 ),
.INIT_11 ( SRAM7_INIT_17 ),
.INIT_12 ( SRAM7_INIT_18 ),
.INIT_13 ( SRAM7_INIT_19 ),
.INIT_14 ( SRAM7_INIT_20 ),
.INIT_15 ( SRAM7_INIT_21 ),
.INIT_16 ( SRAM7_INIT_22 ),
.INIT_17 ( SRAM7_INIT_23 ),
.INIT_18 ( SRAM7_INIT_24 ),
.INIT_19 ( SRAM7_INIT_25 ),
.INIT_1A ( SRAM7_INIT_26 ),
.INIT_1B ( SRAM7_INIT_27 ),
.INIT_1C ( SRAM7_INIT_28 ),
.INIT_1D ( SRAM7_INIT_29 ),
.INIT_1E ( SRAM7_INIT_30 ),
.INIT_1F ( SRAM7_INIT_31 ),
.INIT_20 ( SRAM7_INIT_32 ),
.INIT_21 ( SRAM7_INIT_33 ),
.INIT_22 ( SRAM7_INIT_34 ),
.INIT_23 ( SRAM7_INIT_35 ),
.INIT_24 ( SRAM7_INIT_36 ),
.INIT_25 ( SRAM7_INIT_37 ),
.INIT_26 ( SRAM7_INIT_38 ),
.INIT_27 ( SRAM7_INIT_39 ),
.INIT_28 ( SRAM7_INIT_40 ),
.INIT_29 ( SRAM7_INIT_41 ),
.INIT_2A ( SRAM7_INIT_42 ),
.INIT_2B ( SRAM7_INIT_43 ),
.INIT_2C ( SRAM7_INIT_44 ),
.INIT_2D ( SRAM7_INIT_45 ),
.INIT_2E ( SRAM7_INIT_46 ),
.INIT_2F ( SRAM7_INIT_47 ),
.INIT_30 ( SRAM7_INIT_48 ),
.INIT_31 ( SRAM7_INIT_49 ),
.INIT_32 ( SRAM7_INIT_50 ),
.INIT_33 ( SRAM7_INIT_51 ),
.INIT_34 ( SRAM7_INIT_52 ),
.INIT_35 ( SRAM7_INIT_53 ),
.INIT_36 ( SRAM7_INIT_54 ),
.INIT_37 ( SRAM7_INIT_55 ),
.INIT_38 ( SRAM7_INIT_56 ),
.INIT_39 ( SRAM7_INIT_57 ),
.INIT_3A ( SRAM7_INIT_58 ),
.INIT_3B ( SRAM7_INIT_59 ),
.INIT_3C ( SRAM7_INIT_60 ),
.INIT_3D ( SRAM7_INIT_61 ),
.INIT_3E ( SRAM7_INIT_62 ),
.INIT_3F ( SRAM7_INIT_63 ),
.INIT_FILE ( "NONE" ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.SRVAL_B ( 36'h000000000 ))
u_sram7 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( wea_b1[15:12] ),
.DOA ( read_data_b1[127:96] ),
.ADDRA ( {i_address[8:0], 5'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( i_write_data[127:96] )
);
 
 
endmodule
/lib/xs6_sram_4096x32_byte_en.v
0,0 → 1,1535
//////////////////////////////////////////////////////////////////
// //
// Wrapper for Xilinx Spartan-6 RAM Block //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// 2048 words x 32 bits with a per byte write enable //
// //
// Author(s): //
// - Conor Santifort, csantifort.amber@gmail.com //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
 
module xs6_sram_4096x32_byte_en
#(
parameter SRAM0_INIT_0 = 256'h0,
parameter SRAM0_INIT_1 = 256'h0,
parameter SRAM0_INIT_2 = 256'h0,
parameter SRAM0_INIT_3 = 256'h0,
parameter SRAM0_INIT_4 = 256'h0,
parameter SRAM0_INIT_5 = 256'h0,
parameter SRAM0_INIT_6 = 256'h0,
parameter SRAM0_INIT_7 = 256'h0,
parameter SRAM0_INIT_8 = 256'h0,
parameter SRAM0_INIT_9 = 256'h0,
parameter SRAM0_INIT_10 = 256'h0,
parameter SRAM0_INIT_11 = 256'h0,
parameter SRAM0_INIT_12 = 256'h0,
parameter SRAM0_INIT_13 = 256'h0,
parameter SRAM0_INIT_14 = 256'h0,
parameter SRAM0_INIT_15 = 256'h0,
parameter SRAM0_INIT_16 = 256'h0,
parameter SRAM0_INIT_17 = 256'h0,
parameter SRAM0_INIT_18 = 256'h0,
parameter SRAM0_INIT_19 = 256'h0,
parameter SRAM0_INIT_20 = 256'h0,
parameter SRAM0_INIT_21 = 256'h0,
parameter SRAM0_INIT_22 = 256'h0,
parameter SRAM0_INIT_23 = 256'h0,
parameter SRAM0_INIT_24 = 256'h0,
parameter SRAM0_INIT_25 = 256'h0,
parameter SRAM0_INIT_26 = 256'h0,
parameter SRAM0_INIT_27 = 256'h0,
parameter SRAM0_INIT_28 = 256'h0,
parameter SRAM0_INIT_29 = 256'h0,
parameter SRAM0_INIT_30 = 256'h0,
parameter SRAM0_INIT_31 = 256'h0,
parameter SRAM0_INIT_32 = 256'h0,
parameter SRAM0_INIT_33 = 256'h0,
parameter SRAM0_INIT_34 = 256'h0,
parameter SRAM0_INIT_35 = 256'h0,
parameter SRAM0_INIT_36 = 256'h0,
parameter SRAM0_INIT_37 = 256'h0,
parameter SRAM0_INIT_38 = 256'h0,
parameter SRAM0_INIT_39 = 256'h0,
parameter SRAM0_INIT_40 = 256'h0,
parameter SRAM0_INIT_41 = 256'h0,
parameter SRAM0_INIT_42 = 256'h0,
parameter SRAM0_INIT_43 = 256'h0,
parameter SRAM0_INIT_44 = 256'h0,
parameter SRAM0_INIT_45 = 256'h0,
parameter SRAM0_INIT_46 = 256'h0,
parameter SRAM0_INIT_47 = 256'h0,
parameter SRAM0_INIT_48 = 256'h0,
parameter SRAM0_INIT_49 = 256'h0,
parameter SRAM0_INIT_50 = 256'h0,
parameter SRAM0_INIT_51 = 256'h0,
parameter SRAM0_INIT_52 = 256'h0,
parameter SRAM0_INIT_53 = 256'h0,
parameter SRAM0_INIT_54 = 256'h0,
parameter SRAM0_INIT_55 = 256'h0,
parameter SRAM0_INIT_56 = 256'h0,
parameter SRAM0_INIT_57 = 256'h0,
parameter SRAM0_INIT_58 = 256'h0,
parameter SRAM0_INIT_59 = 256'h0,
parameter SRAM0_INIT_60 = 256'h0,
parameter SRAM0_INIT_61 = 256'h0,
parameter SRAM0_INIT_62 = 256'h0,
parameter SRAM0_INIT_63 = 256'h0,
 
 
parameter SRAM1_INIT_0 = 256'h0,
parameter SRAM1_INIT_1 = 256'h0,
parameter SRAM1_INIT_2 = 256'h0,
parameter SRAM1_INIT_3 = 256'h0,
parameter SRAM1_INIT_4 = 256'h0,
parameter SRAM1_INIT_5 = 256'h0,
parameter SRAM1_INIT_6 = 256'h0,
parameter SRAM1_INIT_7 = 256'h0,
parameter SRAM1_INIT_8 = 256'h0,
parameter SRAM1_INIT_9 = 256'h0,
parameter SRAM1_INIT_10 = 256'h0,
parameter SRAM1_INIT_11 = 256'h0,
parameter SRAM1_INIT_12 = 256'h0,
parameter SRAM1_INIT_13 = 256'h0,
parameter SRAM1_INIT_14 = 256'h0,
parameter SRAM1_INIT_15 = 256'h0,
parameter SRAM1_INIT_16 = 256'h0,
parameter SRAM1_INIT_17 = 256'h0,
parameter SRAM1_INIT_18 = 256'h0,
parameter SRAM1_INIT_19 = 256'h0,
parameter SRAM1_INIT_20 = 256'h0,
parameter SRAM1_INIT_21 = 256'h0,
parameter SRAM1_INIT_22 = 256'h0,
parameter SRAM1_INIT_23 = 256'h0,
parameter SRAM1_INIT_24 = 256'h0,
parameter SRAM1_INIT_25 = 256'h0,
parameter SRAM1_INIT_26 = 256'h0,
parameter SRAM1_INIT_27 = 256'h0,
parameter SRAM1_INIT_28 = 256'h0,
parameter SRAM1_INIT_29 = 256'h0,
parameter SRAM1_INIT_30 = 256'h0,
parameter SRAM1_INIT_31 = 256'h0,
parameter SRAM1_INIT_32 = 256'h0,
parameter SRAM1_INIT_33 = 256'h0,
parameter SRAM1_INIT_34 = 256'h0,
parameter SRAM1_INIT_35 = 256'h0,
parameter SRAM1_INIT_36 = 256'h0,
parameter SRAM1_INIT_37 = 256'h0,
parameter SRAM1_INIT_38 = 256'h0,
parameter SRAM1_INIT_39 = 256'h0,
parameter SRAM1_INIT_40 = 256'h0,
parameter SRAM1_INIT_41 = 256'h0,
parameter SRAM1_INIT_42 = 256'h0,
parameter SRAM1_INIT_43 = 256'h0,
parameter SRAM1_INIT_44 = 256'h0,
parameter SRAM1_INIT_45 = 256'h0,
parameter SRAM1_INIT_46 = 256'h0,
parameter SRAM1_INIT_47 = 256'h0,
parameter SRAM1_INIT_48 = 256'h0,
parameter SRAM1_INIT_49 = 256'h0,
parameter SRAM1_INIT_50 = 256'h0,
parameter SRAM1_INIT_51 = 256'h0,
parameter SRAM1_INIT_52 = 256'h0,
parameter SRAM1_INIT_53 = 256'h0,
parameter SRAM1_INIT_54 = 256'h0,
parameter SRAM1_INIT_55 = 256'h0,
parameter SRAM1_INIT_56 = 256'h0,
parameter SRAM1_INIT_57 = 256'h0,
parameter SRAM1_INIT_58 = 256'h0,
parameter SRAM1_INIT_59 = 256'h0,
parameter SRAM1_INIT_60 = 256'h0,
parameter SRAM1_INIT_61 = 256'h0,
parameter SRAM1_INIT_62 = 256'h0,
parameter SRAM1_INIT_63 = 256'h0,
 
 
 
parameter SRAM2_INIT_0 = 256'h0,
parameter SRAM2_INIT_1 = 256'h0,
parameter SRAM2_INIT_2 = 256'h0,
parameter SRAM2_INIT_3 = 256'h0,
parameter SRAM2_INIT_4 = 256'h0,
parameter SRAM2_INIT_5 = 256'h0,
parameter SRAM2_INIT_6 = 256'h0,
parameter SRAM2_INIT_7 = 256'h0,
parameter SRAM2_INIT_8 = 256'h0,
parameter SRAM2_INIT_9 = 256'h0,
parameter SRAM2_INIT_10 = 256'h0,
parameter SRAM2_INIT_11 = 256'h0,
parameter SRAM2_INIT_12 = 256'h0,
parameter SRAM2_INIT_13 = 256'h0,
parameter SRAM2_INIT_14 = 256'h0,
parameter SRAM2_INIT_15 = 256'h0,
parameter SRAM2_INIT_16 = 256'h0,
parameter SRAM2_INIT_17 = 256'h0,
parameter SRAM2_INIT_18 = 256'h0,
parameter SRAM2_INIT_19 = 256'h0,
parameter SRAM2_INIT_20 = 256'h0,
parameter SRAM2_INIT_21 = 256'h0,
parameter SRAM2_INIT_22 = 256'h0,
parameter SRAM2_INIT_23 = 256'h0,
parameter SRAM2_INIT_24 = 256'h0,
parameter SRAM2_INIT_25 = 256'h0,
parameter SRAM2_INIT_26 = 256'h0,
parameter SRAM2_INIT_27 = 256'h0,
parameter SRAM2_INIT_28 = 256'h0,
parameter SRAM2_INIT_29 = 256'h0,
parameter SRAM2_INIT_30 = 256'h0,
parameter SRAM2_INIT_31 = 256'h0,
parameter SRAM2_INIT_32 = 256'h0,
parameter SRAM2_INIT_33 = 256'h0,
parameter SRAM2_INIT_34 = 256'h0,
parameter SRAM2_INIT_35 = 256'h0,
parameter SRAM2_INIT_36 = 256'h0,
parameter SRAM2_INIT_37 = 256'h0,
parameter SRAM2_INIT_38 = 256'h0,
parameter SRAM2_INIT_39 = 256'h0,
parameter SRAM2_INIT_40 = 256'h0,
parameter SRAM2_INIT_41 = 256'h0,
parameter SRAM2_INIT_42 = 256'h0,
parameter SRAM2_INIT_43 = 256'h0,
parameter SRAM2_INIT_44 = 256'h0,
parameter SRAM2_INIT_45 = 256'h0,
parameter SRAM2_INIT_46 = 256'h0,
parameter SRAM2_INIT_47 = 256'h0,
parameter SRAM2_INIT_48 = 256'h0,
parameter SRAM2_INIT_49 = 256'h0,
parameter SRAM2_INIT_50 = 256'h0,
parameter SRAM2_INIT_51 = 256'h0,
parameter SRAM2_INIT_52 = 256'h0,
parameter SRAM2_INIT_53 = 256'h0,
parameter SRAM2_INIT_54 = 256'h0,
parameter SRAM2_INIT_55 = 256'h0,
parameter SRAM2_INIT_56 = 256'h0,
parameter SRAM2_INIT_57 = 256'h0,
parameter SRAM2_INIT_58 = 256'h0,
parameter SRAM2_INIT_59 = 256'h0,
parameter SRAM2_INIT_60 = 256'h0,
parameter SRAM2_INIT_61 = 256'h0,
parameter SRAM2_INIT_62 = 256'h0,
parameter SRAM2_INIT_63 = 256'h0,
 
parameter SRAM3_INIT_0 = 256'h0,
parameter SRAM3_INIT_1 = 256'h0,
parameter SRAM3_INIT_2 = 256'h0,
parameter SRAM3_INIT_3 = 256'h0,
parameter SRAM3_INIT_4 = 256'h0,
parameter SRAM3_INIT_5 = 256'h0,
parameter SRAM3_INIT_6 = 256'h0,
parameter SRAM3_INIT_7 = 256'h0,
parameter SRAM3_INIT_8 = 256'h0,
parameter SRAM3_INIT_9 = 256'h0,
parameter SRAM3_INIT_10 = 256'h0,
parameter SRAM3_INIT_11 = 256'h0,
parameter SRAM3_INIT_12 = 256'h0,
parameter SRAM3_INIT_13 = 256'h0,
parameter SRAM3_INIT_14 = 256'h0,
parameter SRAM3_INIT_15 = 256'h0,
parameter SRAM3_INIT_16 = 256'h0,
parameter SRAM3_INIT_17 = 256'h0,
parameter SRAM3_INIT_18 = 256'h0,
parameter SRAM3_INIT_19 = 256'h0,
parameter SRAM3_INIT_20 = 256'h0,
parameter SRAM3_INIT_21 = 256'h0,
parameter SRAM3_INIT_22 = 256'h0,
parameter SRAM3_INIT_23 = 256'h0,
parameter SRAM3_INIT_24 = 256'h0,
parameter SRAM3_INIT_25 = 256'h0,
parameter SRAM3_INIT_26 = 256'h0,
parameter SRAM3_INIT_27 = 256'h0,
parameter SRAM3_INIT_28 = 256'h0,
parameter SRAM3_INIT_29 = 256'h0,
parameter SRAM3_INIT_30 = 256'h0,
parameter SRAM3_INIT_31 = 256'h0,
parameter SRAM3_INIT_32 = 256'h0,
parameter SRAM3_INIT_33 = 256'h0,
parameter SRAM3_INIT_34 = 256'h0,
parameter SRAM3_INIT_35 = 256'h0,
parameter SRAM3_INIT_36 = 256'h0,
parameter SRAM3_INIT_37 = 256'h0,
parameter SRAM3_INIT_38 = 256'h0,
parameter SRAM3_INIT_39 = 256'h0,
parameter SRAM3_INIT_40 = 256'h0,
parameter SRAM3_INIT_41 = 256'h0,
parameter SRAM3_INIT_42 = 256'h0,
parameter SRAM3_INIT_43 = 256'h0,
parameter SRAM3_INIT_44 = 256'h0,
parameter SRAM3_INIT_45 = 256'h0,
parameter SRAM3_INIT_46 = 256'h0,
parameter SRAM3_INIT_47 = 256'h0,
parameter SRAM3_INIT_48 = 256'h0,
parameter SRAM3_INIT_49 = 256'h0,
parameter SRAM3_INIT_50 = 256'h0,
parameter SRAM3_INIT_51 = 256'h0,
parameter SRAM3_INIT_52 = 256'h0,
parameter SRAM3_INIT_53 = 256'h0,
parameter SRAM3_INIT_54 = 256'h0,
parameter SRAM3_INIT_55 = 256'h0,
parameter SRAM3_INIT_56 = 256'h0,
parameter SRAM3_INIT_57 = 256'h0,
parameter SRAM3_INIT_58 = 256'h0,
parameter SRAM3_INIT_59 = 256'h0,
parameter SRAM3_INIT_60 = 256'h0,
parameter SRAM3_INIT_61 = 256'h0,
parameter SRAM3_INIT_62 = 256'h0,
parameter SRAM3_INIT_63 = 256'h0,
 
parameter SRAM4_INIT_0 = 256'h0,
parameter SRAM4_INIT_1 = 256'h0,
parameter SRAM4_INIT_2 = 256'h0,
parameter SRAM4_INIT_3 = 256'h0,
parameter SRAM4_INIT_4 = 256'h0,
parameter SRAM4_INIT_5 = 256'h0,
parameter SRAM4_INIT_6 = 256'h0,
parameter SRAM4_INIT_7 = 256'h0,
parameter SRAM4_INIT_8 = 256'h0,
parameter SRAM4_INIT_9 = 256'h0,
parameter SRAM4_INIT_10 = 256'h0,
parameter SRAM4_INIT_11 = 256'h0,
parameter SRAM4_INIT_12 = 256'h0,
parameter SRAM4_INIT_13 = 256'h0,
parameter SRAM4_INIT_14 = 256'h0,
parameter SRAM4_INIT_15 = 256'h0,
parameter SRAM4_INIT_16 = 256'h0,
parameter SRAM4_INIT_17 = 256'h0,
parameter SRAM4_INIT_18 = 256'h0,
parameter SRAM4_INIT_19 = 256'h0,
parameter SRAM4_INIT_20 = 256'h0,
parameter SRAM4_INIT_21 = 256'h0,
parameter SRAM4_INIT_22 = 256'h0,
parameter SRAM4_INIT_23 = 256'h0,
parameter SRAM4_INIT_24 = 256'h0,
parameter SRAM4_INIT_25 = 256'h0,
parameter SRAM4_INIT_26 = 256'h0,
parameter SRAM4_INIT_27 = 256'h0,
parameter SRAM4_INIT_28 = 256'h0,
parameter SRAM4_INIT_29 = 256'h0,
parameter SRAM4_INIT_30 = 256'h0,
parameter SRAM4_INIT_31 = 256'h0,
parameter SRAM4_INIT_32 = 256'h0,
parameter SRAM4_INIT_33 = 256'h0,
parameter SRAM4_INIT_34 = 256'h0,
parameter SRAM4_INIT_35 = 256'h0,
parameter SRAM4_INIT_36 = 256'h0,
parameter SRAM4_INIT_37 = 256'h0,
parameter SRAM4_INIT_38 = 256'h0,
parameter SRAM4_INIT_39 = 256'h0,
parameter SRAM4_INIT_40 = 256'h0,
parameter SRAM4_INIT_41 = 256'h0,
parameter SRAM4_INIT_42 = 256'h0,
parameter SRAM4_INIT_43 = 256'h0,
parameter SRAM4_INIT_44 = 256'h0,
parameter SRAM4_INIT_45 = 256'h0,
parameter SRAM4_INIT_46 = 256'h0,
parameter SRAM4_INIT_47 = 256'h0,
parameter SRAM4_INIT_48 = 256'h0,
parameter SRAM4_INIT_49 = 256'h0,
parameter SRAM4_INIT_50 = 256'h0,
parameter SRAM4_INIT_51 = 256'h0,
parameter SRAM4_INIT_52 = 256'h0,
parameter SRAM4_INIT_53 = 256'h0,
parameter SRAM4_INIT_54 = 256'h0,
parameter SRAM4_INIT_55 = 256'h0,
parameter SRAM4_INIT_56 = 256'h0,
parameter SRAM4_INIT_57 = 256'h0,
parameter SRAM4_INIT_58 = 256'h0,
parameter SRAM4_INIT_59 = 256'h0,
parameter SRAM4_INIT_60 = 256'h0,
parameter SRAM4_INIT_61 = 256'h0,
parameter SRAM4_INIT_62 = 256'h0,
parameter SRAM4_INIT_63 = 256'h0,
 
 
parameter SRAM5_INIT_0 = 256'h0,
parameter SRAM5_INIT_1 = 256'h0,
parameter SRAM5_INIT_2 = 256'h0,
parameter SRAM5_INIT_3 = 256'h0,
parameter SRAM5_INIT_4 = 256'h0,
parameter SRAM5_INIT_5 = 256'h0,
parameter SRAM5_INIT_6 = 256'h0,
parameter SRAM5_INIT_7 = 256'h0,
parameter SRAM5_INIT_8 = 256'h0,
parameter SRAM5_INIT_9 = 256'h0,
parameter SRAM5_INIT_10 = 256'h0,
parameter SRAM5_INIT_11 = 256'h0,
parameter SRAM5_INIT_12 = 256'h0,
parameter SRAM5_INIT_13 = 256'h0,
parameter SRAM5_INIT_14 = 256'h0,
parameter SRAM5_INIT_15 = 256'h0,
parameter SRAM5_INIT_16 = 256'h0,
parameter SRAM5_INIT_17 = 256'h0,
parameter SRAM5_INIT_18 = 256'h0,
parameter SRAM5_INIT_19 = 256'h0,
parameter SRAM5_INIT_20 = 256'h0,
parameter SRAM5_INIT_21 = 256'h0,
parameter SRAM5_INIT_22 = 256'h0,
parameter SRAM5_INIT_23 = 256'h0,
parameter SRAM5_INIT_24 = 256'h0,
parameter SRAM5_INIT_25 = 256'h0,
parameter SRAM5_INIT_26 = 256'h0,
parameter SRAM5_INIT_27 = 256'h0,
parameter SRAM5_INIT_28 = 256'h0,
parameter SRAM5_INIT_29 = 256'h0,
parameter SRAM5_INIT_30 = 256'h0,
parameter SRAM5_INIT_31 = 256'h0,
parameter SRAM5_INIT_32 = 256'h0,
parameter SRAM5_INIT_33 = 256'h0,
parameter SRAM5_INIT_34 = 256'h0,
parameter SRAM5_INIT_35 = 256'h0,
parameter SRAM5_INIT_36 = 256'h0,
parameter SRAM5_INIT_37 = 256'h0,
parameter SRAM5_INIT_38 = 256'h0,
parameter SRAM5_INIT_39 = 256'h0,
parameter SRAM5_INIT_40 = 256'h0,
parameter SRAM5_INIT_41 = 256'h0,
parameter SRAM5_INIT_42 = 256'h0,
parameter SRAM5_INIT_43 = 256'h0,
parameter SRAM5_INIT_44 = 256'h0,
parameter SRAM5_INIT_45 = 256'h0,
parameter SRAM5_INIT_46 = 256'h0,
parameter SRAM5_INIT_47 = 256'h0,
parameter SRAM5_INIT_48 = 256'h0,
parameter SRAM5_INIT_49 = 256'h0,
parameter SRAM5_INIT_50 = 256'h0,
parameter SRAM5_INIT_51 = 256'h0,
parameter SRAM5_INIT_52 = 256'h0,
parameter SRAM5_INIT_53 = 256'h0,
parameter SRAM5_INIT_54 = 256'h0,
parameter SRAM5_INIT_55 = 256'h0,
parameter SRAM5_INIT_56 = 256'h0,
parameter SRAM5_INIT_57 = 256'h0,
parameter SRAM5_INIT_58 = 256'h0,
parameter SRAM5_INIT_59 = 256'h0,
parameter SRAM5_INIT_60 = 256'h0,
parameter SRAM5_INIT_61 = 256'h0,
parameter SRAM5_INIT_62 = 256'h0,
parameter SRAM5_INIT_63 = 256'h0,
 
 
 
parameter SRAM6_INIT_0 = 256'h0,
parameter SRAM6_INIT_1 = 256'h0,
parameter SRAM6_INIT_2 = 256'h0,
parameter SRAM6_INIT_3 = 256'h0,
parameter SRAM6_INIT_4 = 256'h0,
parameter SRAM6_INIT_5 = 256'h0,
parameter SRAM6_INIT_6 = 256'h0,
parameter SRAM6_INIT_7 = 256'h0,
parameter SRAM6_INIT_8 = 256'h0,
parameter SRAM6_INIT_9 = 256'h0,
parameter SRAM6_INIT_10 = 256'h0,
parameter SRAM6_INIT_11 = 256'h0,
parameter SRAM6_INIT_12 = 256'h0,
parameter SRAM6_INIT_13 = 256'h0,
parameter SRAM6_INIT_14 = 256'h0,
parameter SRAM6_INIT_15 = 256'h0,
parameter SRAM6_INIT_16 = 256'h0,
parameter SRAM6_INIT_17 = 256'h0,
parameter SRAM6_INIT_18 = 256'h0,
parameter SRAM6_INIT_19 = 256'h0,
parameter SRAM6_INIT_20 = 256'h0,
parameter SRAM6_INIT_21 = 256'h0,
parameter SRAM6_INIT_22 = 256'h0,
parameter SRAM6_INIT_23 = 256'h0,
parameter SRAM6_INIT_24 = 256'h0,
parameter SRAM6_INIT_25 = 256'h0,
parameter SRAM6_INIT_26 = 256'h0,
parameter SRAM6_INIT_27 = 256'h0,
parameter SRAM6_INIT_28 = 256'h0,
parameter SRAM6_INIT_29 = 256'h0,
parameter SRAM6_INIT_30 = 256'h0,
parameter SRAM6_INIT_31 = 256'h0,
parameter SRAM6_INIT_32 = 256'h0,
parameter SRAM6_INIT_33 = 256'h0,
parameter SRAM6_INIT_34 = 256'h0,
parameter SRAM6_INIT_35 = 256'h0,
parameter SRAM6_INIT_36 = 256'h0,
parameter SRAM6_INIT_37 = 256'h0,
parameter SRAM6_INIT_38 = 256'h0,
parameter SRAM6_INIT_39 = 256'h0,
parameter SRAM6_INIT_40 = 256'h0,
parameter SRAM6_INIT_41 = 256'h0,
parameter SRAM6_INIT_42 = 256'h0,
parameter SRAM6_INIT_43 = 256'h0,
parameter SRAM6_INIT_44 = 256'h0,
parameter SRAM6_INIT_45 = 256'h0,
parameter SRAM6_INIT_46 = 256'h0,
parameter SRAM6_INIT_47 = 256'h0,
parameter SRAM6_INIT_48 = 256'h0,
parameter SRAM6_INIT_49 = 256'h0,
parameter SRAM6_INIT_50 = 256'h0,
parameter SRAM6_INIT_51 = 256'h0,
parameter SRAM6_INIT_52 = 256'h0,
parameter SRAM6_INIT_53 = 256'h0,
parameter SRAM6_INIT_54 = 256'h0,
parameter SRAM6_INIT_55 = 256'h0,
parameter SRAM6_INIT_56 = 256'h0,
parameter SRAM6_INIT_57 = 256'h0,
parameter SRAM6_INIT_58 = 256'h0,
parameter SRAM6_INIT_59 = 256'h0,
parameter SRAM6_INIT_60 = 256'h0,
parameter SRAM6_INIT_61 = 256'h0,
parameter SRAM6_INIT_62 = 256'h0,
parameter SRAM6_INIT_63 = 256'h0,
 
parameter SRAM7_INIT_0 = 256'h0,
parameter SRAM7_INIT_1 = 256'h0,
parameter SRAM7_INIT_2 = 256'h0,
parameter SRAM7_INIT_3 = 256'h0,
parameter SRAM7_INIT_4 = 256'h0,
parameter SRAM7_INIT_5 = 256'h0,
parameter SRAM7_INIT_6 = 256'h0,
parameter SRAM7_INIT_7 = 256'h0,
parameter SRAM7_INIT_8 = 256'h0,
parameter SRAM7_INIT_9 = 256'h0,
parameter SRAM7_INIT_10 = 256'h0,
parameter SRAM7_INIT_11 = 256'h0,
parameter SRAM7_INIT_12 = 256'h0,
parameter SRAM7_INIT_13 = 256'h0,
parameter SRAM7_INIT_14 = 256'h0,
parameter SRAM7_INIT_15 = 256'h0,
parameter SRAM7_INIT_16 = 256'h0,
parameter SRAM7_INIT_17 = 256'h0,
parameter SRAM7_INIT_18 = 256'h0,
parameter SRAM7_INIT_19 = 256'h0,
parameter SRAM7_INIT_20 = 256'h0,
parameter SRAM7_INIT_21 = 256'h0,
parameter SRAM7_INIT_22 = 256'h0,
parameter SRAM7_INIT_23 = 256'h0,
parameter SRAM7_INIT_24 = 256'h0,
parameter SRAM7_INIT_25 = 256'h0,
parameter SRAM7_INIT_26 = 256'h0,
parameter SRAM7_INIT_27 = 256'h0,
parameter SRAM7_INIT_28 = 256'h0,
parameter SRAM7_INIT_29 = 256'h0,
parameter SRAM7_INIT_30 = 256'h0,
parameter SRAM7_INIT_31 = 256'h0,
parameter SRAM7_INIT_32 = 256'h0,
parameter SRAM7_INIT_33 = 256'h0,
parameter SRAM7_INIT_34 = 256'h0,
parameter SRAM7_INIT_35 = 256'h0,
parameter SRAM7_INIT_36 = 256'h0,
parameter SRAM7_INIT_37 = 256'h0,
parameter SRAM7_INIT_38 = 256'h0,
parameter SRAM7_INIT_39 = 256'h0,
parameter SRAM7_INIT_40 = 256'h0,
parameter SRAM7_INIT_41 = 256'h0,
parameter SRAM7_INIT_42 = 256'h0,
parameter SRAM7_INIT_43 = 256'h0,
parameter SRAM7_INIT_44 = 256'h0,
parameter SRAM7_INIT_45 = 256'h0,
parameter SRAM7_INIT_46 = 256'h0,
parameter SRAM7_INIT_47 = 256'h0,
parameter SRAM7_INIT_48 = 256'h0,
parameter SRAM7_INIT_49 = 256'h0,
parameter SRAM7_INIT_50 = 256'h0,
parameter SRAM7_INIT_51 = 256'h0,
parameter SRAM7_INIT_52 = 256'h0,
parameter SRAM7_INIT_53 = 256'h0,
parameter SRAM7_INIT_54 = 256'h0,
parameter SRAM7_INIT_55 = 256'h0,
parameter SRAM7_INIT_56 = 256'h0,
parameter SRAM7_INIT_57 = 256'h0,
parameter SRAM7_INIT_58 = 256'h0,
parameter SRAM7_INIT_59 = 256'h0,
parameter SRAM7_INIT_60 = 256'h0,
parameter SRAM7_INIT_61 = 256'h0,
parameter SRAM7_INIT_62 = 256'h0,
parameter SRAM7_INIT_63 = 256'h0,
 
parameter UNUSED = 1'd1
 
)
 
(
input i_clk,
input [31:0] i_write_data,
input i_write_enable,
input [11:0] i_address,
input [3:0] i_byte_enable,
output [31:0] o_read_data
 
);
 
wire [3:0] wea_b0, wea_b1;
wire [31:0] data_out_b0 [3:0];
wire [31:0] data_out_b1 [3:0];
wire [31:0] read_data_b0;
wire [31:0] read_data_b1;
reg address_11_r;
 
 
assign read_data_b0 = { data_out_b0[3][7:0], data_out_b0[2][7:0],
data_out_b0[1][7:0], data_out_b0[0][7:0] };
assign read_data_b1 = { data_out_b1[3][7:0], data_out_b1[2][7:0],
data_out_b1[1][7:0], data_out_b1[0][7:0] };
 
assign o_read_data = address_11_r ? read_data_b1 : read_data_b0;
assign wea_b0 = {4{i_write_enable & ~i_address[11]}} & i_byte_enable;
assign wea_b1 = {4{i_write_enable & i_address[11]}} & i_byte_enable;
 
always @(posedge i_clk)
address_11_r <= i_address[11];
 
// -----------------------------------------
// Bank 0 - first 8kb block
// -----------------------------------------
RAMB16BWER #(
.INIT_00 ( SRAM0_INIT_0 ),
.INIT_01 ( SRAM0_INIT_1 ),
.INIT_02 ( SRAM0_INIT_2 ),
.INIT_03 ( SRAM0_INIT_3 ),
.INIT_04 ( SRAM0_INIT_4 ),
.INIT_05 ( SRAM0_INIT_5 ),
.INIT_06 ( SRAM0_INIT_6 ),
.INIT_07 ( SRAM0_INIT_7 ),
.INIT_08 ( SRAM0_INIT_8 ),
.INIT_09 ( SRAM0_INIT_9 ),
.INIT_0A ( SRAM0_INIT_10 ),
.INIT_0B ( SRAM0_INIT_11 ),
.INIT_0C ( SRAM0_INIT_12 ),
.INIT_0D ( SRAM0_INIT_13 ),
.INIT_0E ( SRAM0_INIT_14 ),
.INIT_0F ( SRAM0_INIT_15 ),
.INIT_10 ( SRAM0_INIT_16 ),
.INIT_11 ( SRAM0_INIT_17 ),
.INIT_12 ( SRAM0_INIT_18 ),
.INIT_13 ( SRAM0_INIT_19 ),
.INIT_14 ( SRAM0_INIT_20 ),
.INIT_15 ( SRAM0_INIT_21 ),
.INIT_16 ( SRAM0_INIT_22 ),
.INIT_17 ( SRAM0_INIT_23 ),
.INIT_18 ( SRAM0_INIT_24 ),
.INIT_19 ( SRAM0_INIT_25 ),
.INIT_1A ( SRAM0_INIT_26 ),
.INIT_1B ( SRAM0_INIT_27 ),
.INIT_1C ( SRAM0_INIT_28 ),
.INIT_1D ( SRAM0_INIT_29 ),
.INIT_1E ( SRAM0_INIT_30 ),
.INIT_1F ( SRAM0_INIT_31 ),
.INIT_20 ( SRAM0_INIT_32 ),
.INIT_21 ( SRAM0_INIT_33 ),
.INIT_22 ( SRAM0_INIT_34 ),
.INIT_23 ( SRAM0_INIT_35 ),
.INIT_24 ( SRAM0_INIT_36 ),
.INIT_25 ( SRAM0_INIT_37 ),
.INIT_26 ( SRAM0_INIT_38 ),
.INIT_27 ( SRAM0_INIT_39 ),
.INIT_28 ( SRAM0_INIT_40 ),
.INIT_29 ( SRAM0_INIT_41 ),
.INIT_2A ( SRAM0_INIT_42 ),
.INIT_2B ( SRAM0_INIT_43 ),
.INIT_2C ( SRAM0_INIT_44 ),
.INIT_2D ( SRAM0_INIT_45 ),
.INIT_2E ( SRAM0_INIT_46 ),
.INIT_2F ( SRAM0_INIT_47 ),
.INIT_30 ( SRAM0_INIT_48 ),
.INIT_31 ( SRAM0_INIT_49 ),
.INIT_32 ( SRAM0_INIT_50 ),
.INIT_33 ( SRAM0_INIT_51 ),
.INIT_34 ( SRAM0_INIT_52 ),
.INIT_35 ( SRAM0_INIT_53 ),
.INIT_36 ( SRAM0_INIT_54 ),
.INIT_37 ( SRAM0_INIT_55 ),
.INIT_38 ( SRAM0_INIT_56 ),
.INIT_39 ( SRAM0_INIT_57 ),
.INIT_3A ( SRAM0_INIT_58 ),
.INIT_3B ( SRAM0_INIT_59 ),
.INIT_3C ( SRAM0_INIT_60 ),
.INIT_3D ( SRAM0_INIT_61 ),
.INIT_3E ( SRAM0_INIT_62 ),
.INIT_3F ( SRAM0_INIT_63 ),
 
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram0 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( {wea_b0[3], wea_b0[3],
wea_b0[3], wea_b0[3]} ),
.DOA ( data_out_b0[3] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[31:24]} )
);
 
 
RAMB16BWER #(
.INIT_00 ( SRAM1_INIT_0 ),
.INIT_01 ( SRAM1_INIT_1 ),
.INIT_02 ( SRAM1_INIT_2 ),
.INIT_03 ( SRAM1_INIT_3 ),
.INIT_04 ( SRAM1_INIT_4 ),
.INIT_05 ( SRAM1_INIT_5 ),
.INIT_06 ( SRAM1_INIT_6 ),
.INIT_07 ( SRAM1_INIT_7 ),
.INIT_08 ( SRAM1_INIT_8 ),
.INIT_09 ( SRAM1_INIT_9 ),
.INIT_0A ( SRAM1_INIT_10 ),
.INIT_0B ( SRAM1_INIT_11 ),
.INIT_0C ( SRAM1_INIT_12 ),
.INIT_0D ( SRAM1_INIT_13 ),
.INIT_0E ( SRAM1_INIT_14 ),
.INIT_0F ( SRAM1_INIT_15 ),
.INIT_10 ( SRAM1_INIT_16 ),
.INIT_11 ( SRAM1_INIT_17 ),
.INIT_12 ( SRAM1_INIT_18 ),
.INIT_13 ( SRAM1_INIT_19 ),
.INIT_14 ( SRAM1_INIT_20 ),
.INIT_15 ( SRAM1_INIT_21 ),
.INIT_16 ( SRAM1_INIT_22 ),
.INIT_17 ( SRAM1_INIT_23 ),
.INIT_18 ( SRAM1_INIT_24 ),
.INIT_19 ( SRAM1_INIT_25 ),
.INIT_1A ( SRAM1_INIT_26 ),
.INIT_1B ( SRAM1_INIT_27 ),
.INIT_1C ( SRAM1_INIT_28 ),
.INIT_1D ( SRAM1_INIT_29 ),
.INIT_1E ( SRAM1_INIT_30 ),
.INIT_1F ( SRAM1_INIT_31 ),
.INIT_20 ( SRAM1_INIT_32 ),
.INIT_21 ( SRAM1_INIT_33 ),
.INIT_22 ( SRAM1_INIT_34 ),
.INIT_23 ( SRAM1_INIT_35 ),
.INIT_24 ( SRAM1_INIT_36 ),
.INIT_25 ( SRAM1_INIT_37 ),
.INIT_26 ( SRAM1_INIT_38 ),
.INIT_27 ( SRAM1_INIT_39 ),
.INIT_28 ( SRAM1_INIT_40 ),
.INIT_29 ( SRAM1_INIT_41 ),
.INIT_2A ( SRAM1_INIT_42 ),
.INIT_2B ( SRAM1_INIT_43 ),
.INIT_2C ( SRAM1_INIT_44 ),
.INIT_2D ( SRAM1_INIT_45 ),
.INIT_2E ( SRAM1_INIT_46 ),
.INIT_2F ( SRAM1_INIT_47 ),
.INIT_30 ( SRAM1_INIT_48 ),
.INIT_31 ( SRAM1_INIT_49 ),
.INIT_32 ( SRAM1_INIT_50 ),
.INIT_33 ( SRAM1_INIT_51 ),
.INIT_34 ( SRAM1_INIT_52 ),
.INIT_35 ( SRAM1_INIT_53 ),
.INIT_36 ( SRAM1_INIT_54 ),
.INIT_37 ( SRAM1_INIT_55 ),
.INIT_38 ( SRAM1_INIT_56 ),
.INIT_39 ( SRAM1_INIT_57 ),
.INIT_3A ( SRAM1_INIT_58 ),
.INIT_3B ( SRAM1_INIT_59 ),
.INIT_3C ( SRAM1_INIT_60 ),
.INIT_3D ( SRAM1_INIT_61 ),
.INIT_3E ( SRAM1_INIT_62 ),
.INIT_3F ( SRAM1_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram1 (
.REGCEA(1'd0),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ({wea_b0[2], wea_b0[2],
wea_b0[2], wea_b0[2]} ),
.DOA ( data_out_b0[2] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[23:16]} )
);
 
 
RAMB16BWER #(
.INIT_00 ( SRAM2_INIT_0 ),
.INIT_01 ( SRAM2_INIT_1 ),
.INIT_02 ( SRAM2_INIT_2 ),
.INIT_03 ( SRAM2_INIT_3 ),
.INIT_04 ( SRAM2_INIT_4 ),
.INIT_05 ( SRAM2_INIT_5 ),
.INIT_06 ( SRAM2_INIT_6 ),
.INIT_07 ( SRAM2_INIT_7 ),
.INIT_08 ( SRAM2_INIT_8 ),
.INIT_09 ( SRAM2_INIT_9 ),
.INIT_0A ( SRAM2_INIT_10 ),
.INIT_0B ( SRAM2_INIT_11 ),
.INIT_0C ( SRAM2_INIT_12 ),
.INIT_0D ( SRAM2_INIT_13 ),
.INIT_0E ( SRAM2_INIT_14 ),
.INIT_0F ( SRAM2_INIT_15 ),
.INIT_10 ( SRAM2_INIT_16 ),
.INIT_11 ( SRAM2_INIT_17 ),
.INIT_12 ( SRAM2_INIT_18 ),
.INIT_13 ( SRAM2_INIT_19 ),
.INIT_14 ( SRAM2_INIT_20 ),
.INIT_15 ( SRAM2_INIT_21 ),
.INIT_16 ( SRAM2_INIT_22 ),
.INIT_17 ( SRAM2_INIT_23 ),
.INIT_18 ( SRAM2_INIT_24 ),
.INIT_19 ( SRAM2_INIT_25 ),
.INIT_1A ( SRAM2_INIT_26 ),
.INIT_1B ( SRAM2_INIT_27 ),
.INIT_1C ( SRAM2_INIT_28 ),
.INIT_1D ( SRAM2_INIT_29 ),
.INIT_1E ( SRAM2_INIT_30 ),
.INIT_1F ( SRAM2_INIT_31 ),
.INIT_20 ( SRAM2_INIT_32 ),
.INIT_21 ( SRAM2_INIT_33 ),
.INIT_22 ( SRAM2_INIT_34 ),
.INIT_23 ( SRAM2_INIT_35 ),
.INIT_24 ( SRAM2_INIT_36 ),
.INIT_25 ( SRAM2_INIT_37 ),
.INIT_26 ( SRAM2_INIT_38 ),
.INIT_27 ( SRAM2_INIT_39 ),
.INIT_28 ( SRAM2_INIT_40 ),
.INIT_29 ( SRAM2_INIT_41 ),
.INIT_2A ( SRAM2_INIT_42 ),
.INIT_2B ( SRAM2_INIT_43 ),
.INIT_2C ( SRAM2_INIT_44 ),
.INIT_2D ( SRAM2_INIT_45 ),
.INIT_2E ( SRAM2_INIT_46 ),
.INIT_2F ( SRAM2_INIT_47 ),
.INIT_30 ( SRAM2_INIT_48 ),
.INIT_31 ( SRAM2_INIT_49 ),
.INIT_32 ( SRAM2_INIT_50 ),
.INIT_33 ( SRAM2_INIT_51 ),
.INIT_34 ( SRAM2_INIT_52 ),
.INIT_35 ( SRAM2_INIT_53 ),
.INIT_36 ( SRAM2_INIT_54 ),
.INIT_37 ( SRAM2_INIT_55 ),
.INIT_38 ( SRAM2_INIT_56 ),
.INIT_39 ( SRAM2_INIT_57 ),
.INIT_3A ( SRAM2_INIT_58 ),
.INIT_3B ( SRAM2_INIT_59 ),
.INIT_3C ( SRAM2_INIT_60 ),
.INIT_3D ( SRAM2_INIT_61 ),
.INIT_3E ( SRAM2_INIT_62 ),
.INIT_3F ( SRAM2_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
 
)
u_sram2 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( {wea_b0[1], wea_b0[1],
wea_b0[1], wea_b0[1]} ),
.DOA ( data_out_b0[1] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[15:08]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM3_INIT_0 ),
.INIT_01 ( SRAM3_INIT_1 ),
.INIT_02 ( SRAM3_INIT_2 ),
.INIT_03 ( SRAM3_INIT_3 ),
.INIT_04 ( SRAM3_INIT_4 ),
.INIT_05 ( SRAM3_INIT_5 ),
.INIT_06 ( SRAM3_INIT_6 ),
.INIT_07 ( SRAM3_INIT_7 ),
.INIT_08 ( SRAM3_INIT_8 ),
.INIT_09 ( SRAM3_INIT_9 ),
.INIT_0A ( SRAM3_INIT_10 ),
.INIT_0B ( SRAM3_INIT_11 ),
.INIT_0C ( SRAM3_INIT_12 ),
.INIT_0D ( SRAM3_INIT_13 ),
.INIT_0E ( SRAM3_INIT_14 ),
.INIT_0F ( SRAM3_INIT_15 ),
.INIT_10 ( SRAM3_INIT_16 ),
.INIT_11 ( SRAM3_INIT_17 ),
.INIT_12 ( SRAM3_INIT_18 ),
.INIT_13 ( SRAM3_INIT_19 ),
.INIT_14 ( SRAM3_INIT_20 ),
.INIT_15 ( SRAM3_INIT_21 ),
.INIT_16 ( SRAM3_INIT_22 ),
.INIT_17 ( SRAM3_INIT_23 ),
.INIT_18 ( SRAM3_INIT_24 ),
.INIT_19 ( SRAM3_INIT_25 ),
.INIT_1A ( SRAM3_INIT_26 ),
.INIT_1B ( SRAM3_INIT_27 ),
.INIT_1C ( SRAM3_INIT_28 ),
.INIT_1D ( SRAM3_INIT_29 ),
.INIT_1E ( SRAM3_INIT_30 ),
.INIT_1F ( SRAM3_INIT_31 ),
.INIT_20 ( SRAM3_INIT_32 ),
.INIT_21 ( SRAM3_INIT_33 ),
.INIT_22 ( SRAM3_INIT_34 ),
.INIT_23 ( SRAM3_INIT_35 ),
.INIT_24 ( SRAM3_INIT_36 ),
.INIT_25 ( SRAM3_INIT_37 ),
.INIT_26 ( SRAM3_INIT_38 ),
.INIT_27 ( SRAM3_INIT_39 ),
.INIT_28 ( SRAM3_INIT_40 ),
.INIT_29 ( SRAM3_INIT_41 ),
.INIT_2A ( SRAM3_INIT_42 ),
.INIT_2B ( SRAM3_INIT_43 ),
.INIT_2C ( SRAM3_INIT_44 ),
.INIT_2D ( SRAM3_INIT_45 ),
.INIT_2E ( SRAM3_INIT_46 ),
.INIT_2F ( SRAM3_INIT_47 ),
.INIT_30 ( SRAM3_INIT_48 ),
.INIT_31 ( SRAM3_INIT_49 ),
.INIT_32 ( SRAM3_INIT_50 ),
.INIT_33 ( SRAM3_INIT_51 ),
.INIT_34 ( SRAM3_INIT_52 ),
.INIT_35 ( SRAM3_INIT_53 ),
.INIT_36 ( SRAM3_INIT_54 ),
.INIT_37 ( SRAM3_INIT_55 ),
.INIT_38 ( SRAM3_INIT_56 ),
.INIT_39 ( SRAM3_INIT_57 ),
.INIT_3A ( SRAM3_INIT_58 ),
.INIT_3B ( SRAM3_INIT_59 ),
.INIT_3C ( SRAM3_INIT_60 ),
.INIT_3D ( SRAM3_INIT_61 ),
.INIT_3E ( SRAM3_INIT_62 ),
.INIT_3F ( SRAM3_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram3 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.WEA ({wea_b0[0], wea_b0[0],
wea_b0[0], wea_b0[0]} ),
.DOA ( data_out_b0[0] ),
.ADDRA ({i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIA ( {24'd0, i_write_data[7:0]} ),
.DIB ( 32'd0 ),
.DIPA ( 4'd0 ),
.DIPB ( 4'd0 ),
.DOPA ( ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 )
);
 
 
 
// -----------------------------------------
// Bank 1 - second 8kb block
// -----------------------------------------
RAMB16BWER #(
.INIT_00 ( SRAM4_INIT_0 ),
.INIT_01 ( SRAM4_INIT_1 ),
.INIT_02 ( SRAM4_INIT_2 ),
.INIT_03 ( SRAM4_INIT_3 ),
.INIT_04 ( SRAM4_INIT_4 ),
.INIT_05 ( SRAM4_INIT_5 ),
.INIT_06 ( SRAM4_INIT_6 ),
.INIT_07 ( SRAM4_INIT_7 ),
.INIT_08 ( SRAM4_INIT_8 ),
.INIT_09 ( SRAM4_INIT_9 ),
.INIT_0A ( SRAM4_INIT_10 ),
.INIT_0B ( SRAM4_INIT_11 ),
.INIT_0C ( SRAM4_INIT_12 ),
.INIT_0D ( SRAM4_INIT_13 ),
.INIT_0E ( SRAM4_INIT_14 ),
.INIT_0F ( SRAM4_INIT_15 ),
.INIT_10 ( SRAM4_INIT_16 ),
.INIT_11 ( SRAM4_INIT_17 ),
.INIT_12 ( SRAM4_INIT_18 ),
.INIT_13 ( SRAM4_INIT_19 ),
.INIT_14 ( SRAM4_INIT_20 ),
.INIT_15 ( SRAM4_INIT_21 ),
.INIT_16 ( SRAM4_INIT_22 ),
.INIT_17 ( SRAM4_INIT_23 ),
.INIT_18 ( SRAM4_INIT_24 ),
.INIT_19 ( SRAM4_INIT_25 ),
.INIT_1A ( SRAM4_INIT_26 ),
.INIT_1B ( SRAM4_INIT_27 ),
.INIT_1C ( SRAM4_INIT_28 ),
.INIT_1D ( SRAM4_INIT_29 ),
.INIT_1E ( SRAM4_INIT_30 ),
.INIT_1F ( SRAM4_INIT_31 ),
.INIT_20 ( SRAM4_INIT_32 ),
.INIT_21 ( SRAM4_INIT_33 ),
.INIT_22 ( SRAM4_INIT_34 ),
.INIT_23 ( SRAM4_INIT_35 ),
.INIT_24 ( SRAM4_INIT_36 ),
.INIT_25 ( SRAM4_INIT_37 ),
.INIT_26 ( SRAM4_INIT_38 ),
.INIT_27 ( SRAM4_INIT_39 ),
.INIT_28 ( SRAM4_INIT_40 ),
.INIT_29 ( SRAM4_INIT_41 ),
.INIT_2A ( SRAM4_INIT_42 ),
.INIT_2B ( SRAM4_INIT_43 ),
.INIT_2C ( SRAM4_INIT_44 ),
.INIT_2D ( SRAM4_INIT_45 ),
.INIT_2E ( SRAM4_INIT_46 ),
.INIT_2F ( SRAM4_INIT_47 ),
.INIT_30 ( SRAM4_INIT_48 ),
.INIT_31 ( SRAM4_INIT_49 ),
.INIT_32 ( SRAM4_INIT_50 ),
.INIT_33 ( SRAM4_INIT_51 ),
.INIT_34 ( SRAM4_INIT_52 ),
.INIT_35 ( SRAM4_INIT_53 ),
.INIT_36 ( SRAM4_INIT_54 ),
.INIT_37 ( SRAM4_INIT_55 ),
.INIT_38 ( SRAM4_INIT_56 ),
.INIT_39 ( SRAM4_INIT_57 ),
.INIT_3A ( SRAM4_INIT_58 ),
.INIT_3B ( SRAM4_INIT_59 ),
.INIT_3C ( SRAM4_INIT_60 ),
.INIT_3D ( SRAM4_INIT_61 ),
.INIT_3E ( SRAM4_INIT_62 ),
.INIT_3F ( SRAM4_INIT_63 ),
 
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram4 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( {wea_b1[3], wea_b1[3],
wea_b1[3], wea_b1[3]} ),
.DOA ( data_out_b1[3] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[31:24]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM5_INIT_0 ),
.INIT_01 ( SRAM5_INIT_1 ),
.INIT_02 ( SRAM5_INIT_2 ),
.INIT_03 ( SRAM5_INIT_3 ),
.INIT_04 ( SRAM5_INIT_4 ),
.INIT_05 ( SRAM5_INIT_5 ),
.INIT_06 ( SRAM5_INIT_6 ),
.INIT_07 ( SRAM5_INIT_7 ),
.INIT_08 ( SRAM5_INIT_8 ),
.INIT_09 ( SRAM5_INIT_9 ),
.INIT_0A ( SRAM5_INIT_10 ),
.INIT_0B ( SRAM5_INIT_11 ),
.INIT_0C ( SRAM5_INIT_12 ),
.INIT_0D ( SRAM5_INIT_13 ),
.INIT_0E ( SRAM5_INIT_14 ),
.INIT_0F ( SRAM5_INIT_15 ),
.INIT_10 ( SRAM5_INIT_16 ),
.INIT_11 ( SRAM5_INIT_17 ),
.INIT_12 ( SRAM5_INIT_18 ),
.INIT_13 ( SRAM5_INIT_19 ),
.INIT_14 ( SRAM5_INIT_20 ),
.INIT_15 ( SRAM5_INIT_21 ),
.INIT_16 ( SRAM5_INIT_22 ),
.INIT_17 ( SRAM5_INIT_23 ),
.INIT_18 ( SRAM5_INIT_24 ),
.INIT_19 ( SRAM5_INIT_25 ),
.INIT_1A ( SRAM5_INIT_26 ),
.INIT_1B ( SRAM5_INIT_27 ),
.INIT_1C ( SRAM5_INIT_28 ),
.INIT_1D ( SRAM5_INIT_29 ),
.INIT_1E ( SRAM5_INIT_30 ),
.INIT_1F ( SRAM5_INIT_31 ),
.INIT_20 ( SRAM5_INIT_32 ),
.INIT_21 ( SRAM5_INIT_33 ),
.INIT_22 ( SRAM5_INIT_34 ),
.INIT_23 ( SRAM5_INIT_35 ),
.INIT_24 ( SRAM5_INIT_36 ),
.INIT_25 ( SRAM5_INIT_37 ),
.INIT_26 ( SRAM5_INIT_38 ),
.INIT_27 ( SRAM5_INIT_39 ),
.INIT_28 ( SRAM5_INIT_40 ),
.INIT_29 ( SRAM5_INIT_41 ),
.INIT_2A ( SRAM5_INIT_42 ),
.INIT_2B ( SRAM5_INIT_43 ),
.INIT_2C ( SRAM5_INIT_44 ),
.INIT_2D ( SRAM5_INIT_45 ),
.INIT_2E ( SRAM5_INIT_46 ),
.INIT_2F ( SRAM5_INIT_47 ),
.INIT_30 ( SRAM5_INIT_48 ),
.INIT_31 ( SRAM5_INIT_49 ),
.INIT_32 ( SRAM5_INIT_50 ),
.INIT_33 ( SRAM5_INIT_51 ),
.INIT_34 ( SRAM5_INIT_52 ),
.INIT_35 ( SRAM5_INIT_53 ),
.INIT_36 ( SRAM5_INIT_54 ),
.INIT_37 ( SRAM5_INIT_55 ),
.INIT_38 ( SRAM5_INIT_56 ),
.INIT_39 ( SRAM5_INIT_57 ),
.INIT_3A ( SRAM5_INIT_58 ),
.INIT_3B ( SRAM5_INIT_59 ),
.INIT_3C ( SRAM5_INIT_60 ),
.INIT_3D ( SRAM5_INIT_61 ),
.INIT_3E ( SRAM5_INIT_62 ),
.INIT_3F ( SRAM5_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram5 (
.REGCEA(1'd0),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ({wea_b1[2], wea_b1[2],
wea_b1[2], wea_b1[2]} ),
.DOA ( data_out_b1[2] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[23:16]} )
);
 
 
RAMB16BWER #(
.INIT_00 ( SRAM6_INIT_0 ),
.INIT_01 ( SRAM6_INIT_1 ),
.INIT_02 ( SRAM6_INIT_2 ),
.INIT_03 ( SRAM6_INIT_3 ),
.INIT_04 ( SRAM6_INIT_4 ),
.INIT_05 ( SRAM6_INIT_5 ),
.INIT_06 ( SRAM6_INIT_6 ),
.INIT_07 ( SRAM6_INIT_7 ),
.INIT_08 ( SRAM6_INIT_8 ),
.INIT_09 ( SRAM6_INIT_9 ),
.INIT_0A ( SRAM6_INIT_10 ),
.INIT_0B ( SRAM6_INIT_11 ),
.INIT_0C ( SRAM6_INIT_12 ),
.INIT_0D ( SRAM6_INIT_13 ),
.INIT_0E ( SRAM6_INIT_14 ),
.INIT_0F ( SRAM6_INIT_15 ),
.INIT_10 ( SRAM6_INIT_16 ),
.INIT_11 ( SRAM6_INIT_17 ),
.INIT_12 ( SRAM6_INIT_18 ),
.INIT_13 ( SRAM6_INIT_19 ),
.INIT_14 ( SRAM6_INIT_20 ),
.INIT_15 ( SRAM6_INIT_21 ),
.INIT_16 ( SRAM6_INIT_22 ),
.INIT_17 ( SRAM6_INIT_23 ),
.INIT_18 ( SRAM6_INIT_24 ),
.INIT_19 ( SRAM6_INIT_25 ),
.INIT_1A ( SRAM6_INIT_26 ),
.INIT_1B ( SRAM6_INIT_27 ),
.INIT_1C ( SRAM6_INIT_28 ),
.INIT_1D ( SRAM6_INIT_29 ),
.INIT_1E ( SRAM6_INIT_30 ),
.INIT_1F ( SRAM6_INIT_31 ),
.INIT_20 ( SRAM6_INIT_32 ),
.INIT_21 ( SRAM6_INIT_33 ),
.INIT_22 ( SRAM6_INIT_34 ),
.INIT_23 ( SRAM6_INIT_35 ),
.INIT_24 ( SRAM6_INIT_36 ),
.INIT_25 ( SRAM6_INIT_37 ),
.INIT_26 ( SRAM6_INIT_38 ),
.INIT_27 ( SRAM6_INIT_39 ),
.INIT_28 ( SRAM6_INIT_40 ),
.INIT_29 ( SRAM6_INIT_41 ),
.INIT_2A ( SRAM6_INIT_42 ),
.INIT_2B ( SRAM6_INIT_43 ),
.INIT_2C ( SRAM6_INIT_44 ),
.INIT_2D ( SRAM6_INIT_45 ),
.INIT_2E ( SRAM6_INIT_46 ),
.INIT_2F ( SRAM6_INIT_47 ),
.INIT_30 ( SRAM6_INIT_48 ),
.INIT_31 ( SRAM6_INIT_49 ),
.INIT_32 ( SRAM6_INIT_50 ),
.INIT_33 ( SRAM6_INIT_51 ),
.INIT_34 ( SRAM6_INIT_52 ),
.INIT_35 ( SRAM6_INIT_53 ),
.INIT_36 ( SRAM6_INIT_54 ),
.INIT_37 ( SRAM6_INIT_55 ),
.INIT_38 ( SRAM6_INIT_56 ),
.INIT_39 ( SRAM6_INIT_57 ),
.INIT_3A ( SRAM6_INIT_58 ),
.INIT_3B ( SRAM6_INIT_59 ),
.INIT_3C ( SRAM6_INIT_60 ),
.INIT_3D ( SRAM6_INIT_61 ),
.INIT_3E ( SRAM6_INIT_62 ),
.INIT_3F ( SRAM6_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
 
)
u_sram6 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.DIPA ( 4'd0 ),
.WEA ( {wea_b1[1], wea_b1[1],
wea_b1[1], wea_b1[1]} ),
.DOA ( data_out_b1[1] ),
.ADDRA ( {i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIB ( 32'd0 ),
.DOPA ( ),
.DIPB ( 4'd0 ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 ),
.DIA ( {24'd0, i_write_data[15:08]} )
);
RAMB16BWER #(
.INIT_00 ( SRAM7_INIT_0 ),
.INIT_01 ( SRAM7_INIT_1 ),
.INIT_02 ( SRAM7_INIT_2 ),
.INIT_03 ( SRAM7_INIT_3 ),
.INIT_04 ( SRAM7_INIT_4 ),
.INIT_05 ( SRAM7_INIT_5 ),
.INIT_06 ( SRAM7_INIT_6 ),
.INIT_07 ( SRAM7_INIT_7 ),
.INIT_08 ( SRAM7_INIT_8 ),
.INIT_09 ( SRAM7_INIT_9 ),
.INIT_0A ( SRAM7_INIT_10 ),
.INIT_0B ( SRAM7_INIT_11 ),
.INIT_0C ( SRAM7_INIT_12 ),
.INIT_0D ( SRAM7_INIT_13 ),
.INIT_0E ( SRAM7_INIT_14 ),
.INIT_0F ( SRAM7_INIT_15 ),
.INIT_10 ( SRAM7_INIT_16 ),
.INIT_11 ( SRAM7_INIT_17 ),
.INIT_12 ( SRAM7_INIT_18 ),
.INIT_13 ( SRAM7_INIT_19 ),
.INIT_14 ( SRAM7_INIT_20 ),
.INIT_15 ( SRAM7_INIT_21 ),
.INIT_16 ( SRAM7_INIT_22 ),
.INIT_17 ( SRAM7_INIT_23 ),
.INIT_18 ( SRAM7_INIT_24 ),
.INIT_19 ( SRAM7_INIT_25 ),
.INIT_1A ( SRAM7_INIT_26 ),
.INIT_1B ( SRAM7_INIT_27 ),
.INIT_1C ( SRAM7_INIT_28 ),
.INIT_1D ( SRAM7_INIT_29 ),
.INIT_1E ( SRAM7_INIT_30 ),
.INIT_1F ( SRAM7_INIT_31 ),
.INIT_20 ( SRAM7_INIT_32 ),
.INIT_21 ( SRAM7_INIT_33 ),
.INIT_22 ( SRAM7_INIT_34 ),
.INIT_23 ( SRAM7_INIT_35 ),
.INIT_24 ( SRAM7_INIT_36 ),
.INIT_25 ( SRAM7_INIT_37 ),
.INIT_26 ( SRAM7_INIT_38 ),
.INIT_27 ( SRAM7_INIT_39 ),
.INIT_28 ( SRAM7_INIT_40 ),
.INIT_29 ( SRAM7_INIT_41 ),
.INIT_2A ( SRAM7_INIT_42 ),
.INIT_2B ( SRAM7_INIT_43 ),
.INIT_2C ( SRAM7_INIT_44 ),
.INIT_2D ( SRAM7_INIT_45 ),
.INIT_2E ( SRAM7_INIT_46 ),
.INIT_2F ( SRAM7_INIT_47 ),
.INIT_30 ( SRAM7_INIT_48 ),
.INIT_31 ( SRAM7_INIT_49 ),
.INIT_32 ( SRAM7_INIT_50 ),
.INIT_33 ( SRAM7_INIT_51 ),
.INIT_34 ( SRAM7_INIT_52 ),
.INIT_35 ( SRAM7_INIT_53 ),
.INIT_36 ( SRAM7_INIT_54 ),
.INIT_37 ( SRAM7_INIT_55 ),
.INIT_38 ( SRAM7_INIT_56 ),
.INIT_39 ( SRAM7_INIT_57 ),
.INIT_3A ( SRAM7_INIT_58 ),
.INIT_3B ( SRAM7_INIT_59 ),
.INIT_3C ( SRAM7_INIT_60 ),
.INIT_3D ( SRAM7_INIT_61 ),
.INIT_3E ( SRAM7_INIT_62 ),
.INIT_3F ( SRAM7_INIT_63 ),
.DATA_WIDTH_A ( 9 ),
.DATA_WIDTH_B ( 9 ),
.DOA_REG ( 0 ),
.DOB_REG ( 0 ),
.EN_RSTRAM_A ( "FALSE" ),
.EN_RSTRAM_B ( "FALSE" ),
.SRVAL_A ( 36'h000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.RSTTYPE ( "SYNC" ),
.RST_PRIORITY_A ( "CE" ),
.RST_PRIORITY_B ( "CE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_DEVICE ( "SPARTAN6" ),
.INIT_A ( 36'h000000000 ),
.INIT_B ( 36'h000000000 ),
.WRITE_MODE_A ( "READ_FIRST" ),
.WRITE_MODE_B ( "READ_FIRST" ),
.SRVAL_B ( 36'h000000000 )
)
u_sram7 (
.REGCEA ( 1'd0 ),
.CLKA ( i_clk ),
.ENB ( 1'd0 ),
.RSTB ( 1'd0 ),
.CLKB ( 1'd0 ),
.REGCEB ( 1'd0 ),
.RSTA ( 1'd0 ),
.ENA ( 1'd1 ),
.WEA ({wea_b1[0], wea_b1[0],
wea_b1[0], wea_b1[0]} ),
.DOA ( data_out_b1[0] ),
.ADDRA ({i_address[10:0], 3'd0} ),
.ADDRB ( 14'd0 ),
.DIA ( {24'd0, i_write_data[7:0]} ),
.DIB ( 32'd0 ),
.DIPA ( 4'd0 ),
.DIPB ( 4'd0 ),
.DOPA ( ),
.DOPB ( ),
.DOB ( ),
.WEB ( 4'd0 )
);
 
endmodule

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