OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw/vlog
    from Rev 64 to Rev 71
    ↔ Reverse comparison
  •

Rev 64 → Rev 71

/amber23/a23_core.v
100,6 → 100,9
wire [3:0] rm_sel;
wire [3:0] rds_sel;
wire [3:0] rn_sel;
wire [3:0] rm_sel_nxt;
wire [3:0] rds_sel_nxt;
wire [3:0] rn_sel_nxt;
wire [1:0] barrel_shift_amount_sel;
wire [1:0] barrel_shift_data_sel;
wire [1:0] barrel_shift_function;
120,6 → 123,7
wire base_address_wen;
wire pc_wen;
wire [14:0] reg_bank_wen;
wire [3:0] reg_bank_wsel;
 
wire [2:0] copro_opcode1;
wire [2:0] copro_opcode2;
204,7 → 208,7
.i_execute_status_bits ( execute_status_bits ),
.i_multiply_done ( multiply_done ),
.o_status_bits_mode ( status_bits_mode ),
.o_status_bits_mode ( status_bits_mode ),
.o_status_bits_irq_mask ( status_bits_irq_mask ),
.o_status_bits_firq_mask ( status_bits_firq_mask ),
.o_imm32 ( imm32 ),
216,6 → 220,9
.o_rm_sel ( rm_sel ),
.o_rds_sel ( rds_sel ),
.o_rn_sel ( rn_sel ),
.o_rm_sel_nxt ( rm_sel_nxt ),
.o_rds_sel_nxt ( rds_sel_nxt ),
.o_rn_sel_nxt ( rn_sel_nxt ),
.o_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
.o_barrel_shift_data_sel ( barrel_shift_data_sel ),
.o_barrel_shift_function ( barrel_shift_function ),
234,6 → 241,7
.o_base_address_wen ( base_address_wen ),
.o_pc_wen ( pc_wen ),
.o_reg_bank_wen ( reg_bank_wen ),
.o_reg_bank_wsel ( reg_bank_wsel ),
.o_status_bits_flags_wen ( status_bits_flags_wen ),
.o_status_bits_mode_wen ( status_bits_mode_wen ),
.o_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
291,6 → 299,9
.i_rm_sel ( rm_sel ),
.i_rds_sel ( rds_sel ),
.i_rn_sel ( rn_sel ),
.i_rm_sel_nxt ( rm_sel_nxt ),
.i_rds_sel_nxt ( rds_sel_nxt ),
.i_rn_sel_nxt ( rn_sel_nxt ),
.i_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
.i_barrel_shift_data_sel ( barrel_shift_data_sel ),
.i_barrel_shift_function ( barrel_shift_function ),
309,6 → 320,7
.i_base_address_wen ( base_address_wen ),
.i_pc_wen ( pc_wen ),
.i_reg_bank_wen ( reg_bank_wen ),
.i_reg_bank_wsel ( reg_bank_wsel ),
.i_status_bits_flags_wen ( status_bits_flags_wen ),
.i_status_bits_mode_wen ( status_bits_mode_wen ),
.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
/amber23/a23_execute.v
88,6 → 88,9
input [3:0] i_rm_sel,
input [3:0] i_rds_sel,
input [3:0] i_rn_sel,
input [3:0] i_rm_sel_nxt,
input [3:0] i_rds_sel_nxt,
input [3:0] i_rn_sel_nxt,
input [1:0] i_barrel_shift_amount_sel,
input [1:0] i_barrel_shift_data_sel,
input [1:0] i_barrel_shift_function,
102,6 → 105,7
input i_user_mode_regs_load,
input i_user_mode_regs_store_nxt,
input i_firq_not_user_mode,
input i_firq_not_user_mode_nxt,
 
input i_write_data_wen,
input i_base_address_wen, // save LDM base address register,
108,6 → 112,7
// in case of data abort
input i_pc_wen,
input [14:0] i_reg_bank_wen,
input [3:0] i_reg_bank_wsel,
input i_status_bits_flags_wen,
input i_status_bits_mode_wen,
input i_status_bits_irq_mask_wen,
147,7 → 152,12
wire [3:0] status_bits_flags_nxt;
reg [3:0] status_bits_flags = 'd0;
wire [1:0] status_bits_mode_nxt;
wire [1:0] status_bits_mode_nr;
reg [1:0] status_bits_mode = SVC;
// raw rs select
wire [1:0] status_bits_mode_rds_nxt;
wire [1:0] status_bits_mode_rds_nr;
reg [1:0] status_bits_mode_rds;
// one-hot encoded rs select
wire [3:0] status_bits_mode_rds_oh_nxt;
reg [3:0] status_bits_mode_rds_oh = 1'd1 << OH_SVC;
161,6 → 171,7
wire [31:0] reg_write_nxt;
wire pc_wen;
wire [14:0] reg_bank_wen;
wire [3:0] reg_bank_wsel;
wire [31:0] multiply_out;
wire [1:0] multiply_flags;
reg [31:0] base_address = 'd0; // Saves base address during LDM instruction in
218,12 → 229,15
// i_user_mode_regs_store_nxt signal back into the previous stage -
// so its really part of the decode stage even though the logic is right here
// In addition the signal is one-hot encoded to further speed up the logic
// Raw version is also kept for ram-based register bank implementation.
 
assign status_bits_mode_rds_oh_nxt = i_user_mode_regs_store_nxt ? 1'd1 << OH_USR :
status_bits_mode_update ? oh_status_bits_mode(status_bits_mode_nxt) :
oh_status_bits_mode(status_bits_mode) ;
assign status_bits_mode_rds_nxt = i_user_mode_regs_store_nxt ? OH_USR :
status_bits_mode_update ? status_bits_mode_nxt :
status_bits_mode ;
 
assign status_bits_mode_rds_oh_nxt = oh_status_bits_mode(status_bits_mode_rds_nxt);
 
 
assign status_bits_irq_mask_nxt = i_status_bits_sel == 3'd0 ? i_status_bits_irq_mask :
i_status_bits_sel == 3'd1 ? alu_out [27] :
i_copro_read_data [27] ;
380,7 → 394,9
// only update register bank if current instruction executes
assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
 
assign reg_bank_wsel = {{4{~execute}} | i_reg_bank_wsel};
 
 
// ========================================================
// Priviledged output flag
// ========================================================
416,7 → 432,12
assign status_bits_irq_mask_update = !i_fetch_stall && execute && i_status_bits_irq_mask_wen;
assign status_bits_firq_mask_update = !i_fetch_stall && execute && i_status_bits_firq_mask_wen;
 
assign status_bits_mode_rds_nr = status_bits_mode_rds_oh_update ? status_bits_mode_rds_nxt :
status_bits_mode_rds ;
 
assign status_bits_mode_nr = status_bits_mode_update ? status_bits_mode_nxt :
status_bits_mode ;
 
always @( posedge i_clk )
begin
o_priviledged <= priviledged_update ? priviledged_nxt : o_priviledged;
433,8 → 454,9
base_address <= base_address_update ? rn : base_address;
 
status_bits_flags <= status_bits_flags_update ? status_bits_flags_nxt : status_bits_flags;
status_bits_mode <= status_bits_mode_update ? status_bits_mode_nxt : status_bits_mode;
status_bits_mode <= status_bits_mode_nr;
status_bits_mode_rds_oh <= status_bits_mode_rds_oh_update ? status_bits_mode_rds_oh_nxt : status_bits_mode_rds_oh;
status_bits_mode_rds <= status_bits_mode_rds_nr;
status_bits_irq_mask <= status_bits_irq_mask_update ? status_bits_irq_mask_nxt : status_bits_irq_mask;
status_bits_firq_mask <= status_bits_firq_mask_update ? status_bits_firq_mask_nxt : status_bits_firq_mask;
end
/amber23/a23_decode.v
79,6 → 79,9
output reg [3:0] o_rm_sel = 'd0,
output reg [3:0] o_rds_sel = 'd0,
output reg [3:0] o_rn_sel = 'd0,
output [3:0] o_rm_sel_nxt,
output [3:0] o_rds_sel_nxt,
output [3:0] o_rn_sel_nxt,
output reg [1:0] o_barrel_shift_amount_sel = 'd0,
output reg [1:0] o_barrel_shift_data_sel = 'd0,
output reg [1:0] o_barrel_shift_function = 'd0,
99,6 → 102,7
// in case of data abort
output reg o_pc_wen = 1'd1,
output reg [14:0] o_reg_bank_wen = 'd0,
output reg [3:0] o_reg_bank_wsel = 'd0,
output reg o_status_bits_flags_wen = 'd0,
output reg o_status_bits_mode_wen = 'd0,
output reg o_status_bits_irq_mask_wen = 'd0,
201,9 → 205,6
reg status_bits_irq_mask_nxt;
reg status_bits_firq_mask_nxt;
 
wire [3:0] rm_sel_nxt;
wire [3:0] rds_sel_nxt;
wire [3:0] rn_sel_nxt;
reg [1:0] barrel_shift_amount_sel_nxt;
reg [1:0] barrel_shift_data_sel_nxt;
reg [3:0] address_sel_nxt;
225,7 → 226,7
reg copro_write_data_wen_nxt;
reg base_address_wen_nxt;
reg pc_wen_nxt;
reg [14:0] reg_bank_wen_nxt;
reg [3:0] reg_bank_wsel_nxt;
reg status_bits_flags_wen_nxt;
reg status_bits_mode_wen_nxt;
reg status_bits_irq_mask_wen_nxt;
383,12 → 384,12
assign opcode = instruction[24:21];
assign condition_nxt = instruction[31:28];
 
assign rm_sel_nxt = instruction[3:0];
assign o_rm_sel_nxt = instruction[3:0];
assign rn_sel_nxt = branch ? 4'd15 : // Use PC to calculate branch destination
assign o_rn_sel_nxt = branch ? 4'd15 : // Use PC to calculate branch destination
instruction[19:16] ;
 
assign rds_sel_nxt = control_state == SWAP_WRITE ? instruction[3:0] : // Rm gets written out to memory
assign o_rds_sel_nxt = control_state == SWAP_WRITE ? instruction[3:0] : // Rm gets written out to memory
type == MTRANS ? mtrans_reg :
branch ? 4'd15 : // Update the PC
rds_use_rs ? instruction[11:8] :
617,7 → 618,7
byte_enable_sel_nxt = 'd0;
status_bits_sel_nxt = 'd0;
reg_write_sel_nxt = 'd0;
user_mode_regs_load_nxt = 'd0;
user_mode_regs_load_nxt = 'd0;
o_user_mode_regs_store_nxt = 'd0;
// ALU Muxes
632,7 → 633,7
copro_write_data_wen_nxt = 'd0;
base_address_wen_nxt = 'd0;
pc_wen_nxt = 'd1;
reg_bank_wen_nxt = 'd0; // Don't select any
reg_bank_wsel_nxt = 'hF; // Don't select any
status_bits_flags_wen_nxt = 'd0;
status_bits_mode_wen_nxt = 'd0;
status_bits_irq_mask_wen_nxt = 'd0;
651,7 → 652,7
address_sel_nxt = 4'd1; // alu_out
end
else
reg_bank_wen_nxt = decode (instruction[15:12]);
reg_bank_wsel_nxt = instruction[15:12];
end
if ( !immediate_shifter_operand )
775,10 → 776,10
if ( mem_op_pre_indexed || mem_op_post_indexed )
begin
// Check is the load destination is the PC
if ( rn_sel_nxt == 4'd15 )
if ( o_rn_sel_nxt == 4'd15 )
pc_sel_nxt = 2'd1;
else
reg_bank_wen_nxt = decode ( rn_sel_nxt );
reg_bank_wsel_nxt = o_rn_sel_nxt;
end
// if post-indexed, then use Rn rather than ALU output, as address
805,7 → 806,7
if ( instruction[24] ) // Link
begin
reg_bank_wen_nxt = decode (4'd14); // Save PC to LR
reg_bank_wsel_nxt = 4'd14; // Save PC to LR
reg_write_sel_nxt = 3'd1; // pc - 32'd4
end
end
861,7 → 862,7
// update the base register ?
if ( instruction[21] ) // the W bit
reg_bank_wen_nxt = decode (rn_sel_nxt);
reg_bank_wsel_nxt = o_rn_sel_nxt;
end
914,7 → 915,7
begin
// save address of next instruction to Supervisor Mode LR
reg_write_sel_nxt = 3'd1; // pc -4
reg_bank_wen_nxt = decode (4'd14); // LR
reg_bank_wsel_nxt = 4'd14; // LR
address_sel_nxt = 4'd2; // interrupt_vector
pc_sel_nxt = 2'd2; // interrupt_vector
970,7 → 971,7
else
reg_write_sel_nxt = 3'd1; // pc -4
reg_bank_wen_nxt = decode (4'd14); // LR
reg_bank_wsel_nxt = 4'd14; // LR
address_sel_nxt = 4'd2; // interrupt_vector
pc_sel_nxt = 2'd2; // interrupt_vector
1030,7 → 1031,7
address_sel_nxt = 4'd1; // alu_out
end
else
reg_bank_wen_nxt = decode (instruction[15:12]);
reg_bank_wsel_nxt = instruction[15:12];
end
end
1078,7 → 1079,7
// Can never be loading the PC in this state, as the PC is always
// the last register in the set to be loaded
if ( !dabt )
reg_bank_wen_nxt = decode (mtrans_reg_d2);
reg_bank_wsel_nxt = mtrans_reg_d2;
end
else // Store
write_data_wen_nxt = 1'd1;
1103,7 → 1104,7
// Can never be loading the PC in this state, as the PC is always
// the last register in the set to be loaded
if ( instruction[20] && !dabt ) // Load
reg_bank_wen_nxt = decode (mtrans_reg_d2);
reg_bank_wsel_nxt = mtrans_reg_d2;
// LDM: load into user mode registers, when in priviledged mode
if ( {instruction[22:20],mtrans_r15} == 4'b1010 )
1167,7 → 1168,7
end
else
begin
reg_bank_wen_nxt = decode (mtrans_reg_d2);
reg_bank_wsel_nxt = mtrans_reg_d2;
end
end
end
1196,7 → 1197,7
if (restore_base_address) // LDM with base address in register list
begin
reg_write_sel_nxt = 3'd6; // write base_register
reg_bank_wen_nxt = decode ( instruction[19:16] ); // to Rn
reg_bank_wsel_nxt = instruction[19:16]; // to Rn
end
end
1233,9 → 1234,9
multiply_function_nxt = o_multiply_function;
if ( type == MULT ) // 32-bit
reg_bank_wen_nxt = decode (instruction[19:16]); // Rd
reg_bank_wsel_nxt = instruction[19:16]; // Rd
else // 64-bit / Long
reg_bank_wen_nxt = decode (instruction[15:12]); // RdLo
reg_bank_wsel_nxt = instruction[15:12]; // RdLo
if ( instruction[20] ) // the 'S' bit
begin
1303,7 → 1304,7
address_sel_nxt = 4'd1; // alu_out
end
else
reg_bank_wen_nxt = decode (instruction[15:12]);
reg_bank_wsel_nxt = instruction[15:12];
end
end
1331,7 → 1332,7
end
end
else
reg_bank_wen_nxt = decode (instruction[15:12]);
reg_bank_wsel_nxt = instruction[15:12];
reg_write_sel_nxt = 3'd5; // i_copro_data
end
1529,9 → 1530,9
o_exclusive_exec <= exclusive_exec_nxt;
o_data_access_exec <= data_access_exec_nxt;
o_rm_sel <= rm_sel_nxt;
o_rds_sel <= rds_sel_nxt;
o_rn_sel <= rn_sel_nxt;
o_rm_sel <= o_rm_sel_nxt;
o_rds_sel <= o_rds_sel_nxt;
o_rn_sel <= o_rn_sel_nxt;
o_barrel_shift_amount_sel <= barrel_shift_amount_sel_nxt;
o_barrel_shift_data_sel <= barrel_shift_data_sel_nxt;
o_barrel_shift_function <= barrel_shift_function_nxt;
1548,7 → 1549,8
o_write_data_wen <= write_data_wen_nxt;
o_base_address_wen <= base_address_wen_nxt;
o_pc_wen <= pc_wen_nxt;
o_reg_bank_wen <= reg_bank_wen_nxt;
o_reg_bank_wsel <= reg_bank_wsel_nxt;
o_reg_bank_wen <= decode ( reg_bank_wsel_nxt );
o_status_bits_flags_wen <= status_bits_flags_wen_nxt;
o_status_bits_mode_wen <= status_bits_mode_wen_nxt;
o_status_bits_irq_mask_wen <= status_bits_irq_mask_wen_nxt;

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