URL
https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
Compare Revisions
- This comparison shows the changes necessary to convert path
/amber/trunk/hw
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/tools/all.sh
54,7 → 54,7
cache1 cache2 cache3 cache_swap \ |
cacheable_area cache_flush \ |
\ |
flow1 flow2 flow3 \ |
flow1 flow2 flow3 conflict_rd \ |
\ |
hiboot_mem ddr31 ddr32 ddr33 \ |
\ |
/tests/timeouts.txt
1,59 → 1,60
flow4 3936 |
tmp 3396 |
add 1740 |
adc 1380 |
sub 1560 |
sbc 2676 |
barrel_shift 1560 |
barrel_shift_rs 1380 |
change_sbits 2340 |
change_mode 1692 |
bl 1572 |
bcc 1200 |
ldr 4432 |
ldr_str_pc 1612 |
strb 2288 |
ldm1 2628 |
ldm2 2052 |
ldm3 1868 |
ldm4 1856 |
stm1 7588 |
stm2 2440 |
ldm_stm_onetwo 4840 |
stm_stream 52276 |
mul 186960 |
mla 377424 |
swp 2084 |
irq 103828 |
firq 30540 |
swi 1620 |
undefined_ins 2748 |
addr_ex 1772 |
irq_stm 10220 |
cache1 16308 |
cache2 1460 |
cache3 106064 |
cache_swap 69276 |
cacheable_area 5952 |
cache_flush 18408 |
flow1 2976 |
flow2 4960 |
flow3 3348 |
hiboot_mem 1424 |
ddr31 102880 |
ddr32 205992 |
ddr33 21792 |
ethmac_reg 4776 |
ethmac_mem 75844 |
ethmac_tx 18172 |
uart_reg 1824 |
uart_tx 136588 |
uart_rx 132384 |
uart_rxint 127204 |
bic_bug 1524 |
movs_bug 1592 |
flow_bug 1500 |
mlas_bug 1996 |
inflate_bug 1420 |
swp_lock_bug 1368 |
cache_swap_bug 29620 |
tmp 3376 |
add 1704 |
adc 1368 |
sub 1500 |
sbc 2484 |
barrel_shift 1524 |
barrel_shift_rs 1368 |
change_sbits 2184 |
change_mode 1656 |
bl 1548 |
bcc 1188 |
ldr 4000 |
ldr_str_pc 1564 |
strb 2120 |
ldm1 2544 |
ldm2 2016 |
ldm3 1832 |
ldm4 1820 |
stm1 7024 |
stm2 2296 |
ldm_stm_onetwo 4748 |
stm_stream 49188 |
mul 177660 |
mla 365076 |
swp 2004 |
irq 97644 |
firq 28764 |
swi 1596 |
undefined_ins 2616 |
addr_ex 1724 |
irq_stm 9812 |
cache1 16296 |
cache2 1456 |
cache3 98884 |
cache_swap 66196 |
cacheable_area 5580 |
cache_flush 17572 |
flow1 2972 |
flow2 4800 |
flow3 3292 |
hiboot_mem 1376 |
ddr31 96676 |
ddr32 193584 |
ddr33 20820 |
ethmac_reg 4596 |
ethmac_mem 75708 |
ethmac_tx 16692 |
uart_reg 1800 |
uart_tx 137764 |
uart_rx 132024 |
uart_rxint 125032 |
bic_bug 1512 |
movs_bug 1532 |
flow_bug 1428 |
mlas_bug 1948 |
inflate_bug 1360 |
swp_lock_bug 1320 |
cache_swap_bug 29504 |
conflict_rd 2552 |
/tests/conflict_rd.S
0,0 → 1,127
/***************************************************************** |
// // |
// Amber 2 Core Instruction Test // |
// // |
// This file is part of the Amber project // |
// http://www.opencores.org/project,amber // |
// // |
// Description // |
// Tests that a register conflict between a ldr and a regop // |
// that changes the value of the same register is handled // |
// correctly. // |
// // |
// Author(s): // |
// - Conor Santifort, csantifort.amber@gmail.com // |
// // |
////////////////////////////////////////////////////////////////// |
// // |
// Copyright (C) 2010 Authors and OPENCORES.ORG // |
// // |
// This source file may be used and distributed without // |
// restriction provided that this copyright statement is not // |
// removed from the file and that any derivative work contains // |
// the original copyright notice and the associated disclaimer. // |
// // |
// This source file is free software; you can redistribute it // |
// and/or modify it under the terms of the GNU Lesser General // |
// Public License as published by the Free Software Foundation; // |
// either version 2.1 of the License, or (at your option) any // |
// later version. // |
// // |
// This source is distributed in the hope that it will be // |
// useful, but WITHOUT ANY WARRANTY; without even the implied // |
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
// PURPOSE. See the GNU Lesser General Public License for more // |
// details. // |
// // |
// You should have received a copy of the GNU Lesser General // |
// Public License along with this source; if not, download it // |
// from http://www.opencores.org/lgpl.shtml // |
// // |
*****************************************************************/ |
|
#include "amber_registers.h" |
|
.section .text |
.globl main |
main: |
|
@ Run through the test 4 times |
@ 1 - cache off |
@ 2 - cache on but empty |
@ 3 - cache on and loaded |
@ 4 - same as 3 |
|
mov r10, #40 |
|
1: mov r1, #1 |
mov r2, #2 |
mov r3, #3 |
mov r4, #4 |
mov r5, #0x1000 |
mov r6, #6 |
str r6, [r5] |
mov sp, #0x800 |
|
@ -------------------------- |
tst r3, #1 |
add r0, r6, r4 |
ldr r1, Data1 |
ldr r3, Data2 |
ldr r2, Data3 |
movne r2, r3 @ always executed |
ldr r3, [r5] |
|
bl 2f |
|
nop |
nop |
nop |
|
2: stmdb sp!, {r1, r2, r3} |
|
nop |
nop |
|
ldr r8, [sp, #4] |
ldr r9, Data2 |
cmp r8, r9 |
addne r10, #1 |
bne testfail |
|
@ --------------------- |
@ Enable the cache |
@ --------------------- |
mvn r0, #0 |
mcr 15, 0, r0, cr3, cr0, 0 @ cacheable area |
mov r0, #1 |
mcr 15, 0, r0, cr2, cr0, 0 @ cache enable |
|
subs r10, r10, #10 |
bne 1b |
|
b testpass |
|
testfail: |
ldr r11, AdrTestStatus |
str r10, [r11] |
b testfail |
|
testpass: |
ldr r11, AdrTestStatus |
mov r10, #17 |
str r10, [r11] |
b testpass |
|
|
/* Write 17 to this address to generate a Test Passed message */ |
AdrTestStatus: .word ADR_AMBER_TEST_STATUS |
AdrHiBootBase: .word ADR_HIBOOT_BASE |
|
Data1: .word 0x1000 |
Data2: .word 0x2000 |
Data3: .word 0x3000 |
|
/* ========================================================================= */ |
/* ========================================================================= */ |
|
/vlog/amber25/a25_decode.v
125,9 → 125,12
output o_dabt_trigger, |
output [31:0] o_dabt_address, |
output [7:0] o_dabt_status, |
output o_conflict |
output o_conflict, |
output reg o_rn_use_read, |
output reg o_rm_use_read, |
output reg o_rs_use_read, |
output reg o_rd_use_read |
|
|
); |
|
`include "a25_localparams.v" |
270,6 → 273,7
|
wire instruction_valid; |
wire instruction_execute; |
reg instruction_execute_r = 'd0; |
|
reg [3:0] mtrans_reg1; // the current register being accessed as part of stm/ldm |
reg [3:0] mtrans_reg2; // the next register being accessed as part of stm/ldm |
327,6 → 331,10
wire conflict2; // Register conflict1 with ldr operation |
wire conflict; // Register conflict1 with ldr operation |
reg conflict_r = 'd0; |
reg rn_conflict1_r = 'd0; |
reg rm_conflict1_r = 'd0; |
reg rs_conflict1_r = 'd0; |
reg rd_conflict1_r = 'd0; |
|
|
// ======================================================== |
512,32 → 520,32
// ======================================================== |
// Register Conflict Detection |
// ======================================================== |
assign rn_valid = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS; |
assign rm_valid = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op); |
assign rs_valid = rds_use_rs; |
assign rd_valid = type == TRANS && store_op; // str instruction |
assign stm_valid = type == MTRANS && !instruction[20]; // stm instruction |
|
assign rn_conflict1 = rn_valid && ( load_rd_d1_nxt[4] && rn_sel_nxt == load_rd_d1_nxt[3:0] ); |
assign rn_conflict2 = rn_valid && ( load_rd_d1 [4] && rn_sel_nxt == load_rd_d1 [3:0] ); |
assign rm_conflict1 = rm_valid && ( load_rd_d1_nxt[4] && rm_sel_nxt == load_rd_d1_nxt[3:0] ); |
assign rm_conflict2 = rm_valid && ( load_rd_d1 [4] && rm_sel_nxt == load_rd_d1 [3:0] ); |
assign rs_conflict1 = rs_valid && ( load_rd_d1_nxt[4] && rs_sel_nxt == load_rd_d1_nxt[3:0] ); |
assign rs_conflict2 = rs_valid && ( load_rd_d1 [4] && rs_sel_nxt == load_rd_d1 [3:0] ); |
assign rd_conflict1 = rd_valid && ( load_rd_d1_nxt[4] && instruction[15:12] == load_rd_d1_nxt[3:0] ); |
assign rd_conflict2 = rd_valid && ( load_rd_d1 [4] && instruction[15:12] == load_rd_d1 [3:0] ); |
assign stm_conflict1a = stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg1 == load_rd_d1_nxt[3:0] ); |
assign stm_conflict1b = stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg2 == load_rd_d1_nxt[3:0] ); |
assign stm_conflict2a = stm_valid && ( load_rd_d1 [4] && mtrans_reg1 == load_rd_d1 [3:0] ); |
assign stm_conflict2b = stm_valid && ( load_rd_d1 [4] && mtrans_reg2 == load_rd_d1 [3:0] ); |
assign rn_valid = type == REGOP || type == MULT || type == SWAP || type == TRANS || type == MTRANS || type == CODTRANS; |
assign rm_valid = type == REGOP || type == MULT || type == SWAP || (type == TRANS && immediate_shift_op); |
assign rs_valid = rds_use_rs; |
assign rd_valid = (type == TRANS && store_op) || (type == REGOP || type == SWAP); |
assign stm_valid = type == MTRANS && !instruction[20]; // stm instruction |
|
|
assign rn_conflict1 = instruction_execute && rn_valid && ( load_rd_d1_nxt[4] && rn_sel_nxt == load_rd_d1_nxt[3:0] ); |
assign rn_conflict2 = instruction_execute_r && rn_valid && ( load_rd_d1 [4] && rn_sel_nxt == load_rd_d1 [3:0] ); |
assign rm_conflict1 = instruction_execute && rm_valid && ( load_rd_d1_nxt[4] && rm_sel_nxt == load_rd_d1_nxt[3:0] ); |
assign rm_conflict2 = instruction_execute_r && rm_valid && ( load_rd_d1 [4] && rm_sel_nxt == load_rd_d1 [3:0] ); |
assign rs_conflict1 = instruction_execute && rs_valid && ( load_rd_d1_nxt[4] && rs_sel_nxt == load_rd_d1_nxt[3:0] ); |
assign rs_conflict2 = instruction_execute_r && rs_valid && ( load_rd_d1 [4] && rs_sel_nxt == load_rd_d1 [3:0] ); |
assign rd_conflict1 = instruction_execute && rd_valid && ( load_rd_d1_nxt[4] && instruction[15:12] == load_rd_d1_nxt[3:0] ); |
assign rd_conflict2 = instruction_execute_r && rd_valid && ( load_rd_d1 [4] && instruction[15:12] == load_rd_d1 [3:0] ); |
|
assign stm_conflict1a = instruction_execute && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg1 == load_rd_d1_nxt[3:0] ); |
assign stm_conflict1b = instruction_execute && stm_valid && ( load_rd_d1_nxt[4] && mtrans_reg2 == load_rd_d1_nxt[3:0] ); |
assign stm_conflict2a = instruction_execute_r && stm_valid && ( load_rd_d1 [4] && mtrans_reg1 == load_rd_d1 [3:0] ); |
assign stm_conflict2b = instruction_execute_r && stm_valid && ( load_rd_d1 [4] && mtrans_reg2 == load_rd_d1 [3:0] ); |
|
assign conflict1 = instruction_valid && |
(rn_conflict1 || rm_conflict1 || rs_conflict1 || rd_conflict1 || |
stm_conflict1a || stm_conflict1b); |
|
assign conflict2 = instruction_valid && |
(rn_conflict2 || rm_conflict2 || rs_conflict2 || rd_conflict2 || |
stm_conflict2a || stm_conflict2b); |
assign conflict2 = instruction_valid && (stm_conflict2a || stm_conflict2b); |
|
assign conflict = conflict1 || conflict2; |
|
545,7 → 553,16
always @( posedge i_clk ) |
if ( !i_access_stall ) |
begin |
conflict_r <= conflict; |
conflict_r <= conflict; |
instruction_execute_r <= instruction_execute; |
rn_conflict1_r <= rn_conflict1 && instruction_execute; |
rm_conflict1_r <= rm_conflict1 && instruction_execute; |
rs_conflict1_r <= rs_conflict1 && instruction_execute; |
rd_conflict1_r <= rd_conflict1 && instruction_execute; |
o_rn_use_read <= instruction_valid && ( rn_conflict1_r || rn_conflict2 ); |
o_rm_use_read <= instruction_valid && ( rm_conflict1_r || rm_conflict2 ); |
o_rs_use_read <= instruction_valid && ( rs_conflict1_r || rs_conflict2 ); |
o_rd_use_read <= instruction_valid && ( rd_conflict1_r || rd_conflict2 ); |
end |
|
assign o_conflict = conflict; |
/vlog/amber25/a25_core.v
178,8 → 178,11
wire icache_wb_ready; |
|
wire conflict; |
wire rn_use_read; |
wire rm_use_read; |
wire rs_use_read; |
wire rd_use_read; |
|
|
// data abort has priority |
assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status; |
assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address; |
287,7 → 290,11
.o_dabt_address ( dabt_fault_address ), |
.o_dabt_status ( dabt_fault_status ), |
|
.o_conflict ( conflict ) |
.o_conflict ( conflict ), |
.o_rn_use_read ( rn_use_read ), |
.o_rm_use_read ( rm_use_read ), |
.o_rs_use_read ( rs_use_read ), |
.o_rd_use_read ( rd_use_read ) |
); |
|
|
360,7 → 367,11
.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ), |
.i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ), |
.i_copro_write_data_wen ( copro_write_data_wen ), |
.i_conflict ( conflict ) |
.i_conflict ( conflict ), |
.i_rn_use_read ( rn_use_read ), |
.i_rm_use_read ( rm_use_read ), |
.i_rs_use_read ( rs_use_read ), |
.i_rd_use_read ( rd_use_read ) |
); |
|
|
/vlog/amber25/a25_execute.v
119,8 → 119,11
input i_status_bits_irq_mask_wen, |
input i_status_bits_firq_mask_wen, |
input i_copro_write_data_wen, |
input i_conflict |
|
input i_conflict, |
input i_rn_use_read, |
input i_rm_use_read, |
input i_rs_use_read, |
input i_rd_use_read |
); |
|
`include "a25_localparams.v" |
142,6 → 145,10
wire [31:0] rs; |
wire [31:0] rd; |
wire [31:0] rn; |
wire [31:0] reg_bank_rn; |
wire [31:0] reg_bank_rm; |
wire [31:0] reg_bank_rs; |
wire [31:0] reg_bank_rd; |
wire [31:0] pc; |
wire [31:0] pc_nxt; |
wire [31:0] interrupt_vector; |
173,6 → 180,10
// case of data abort |
wire [31:0] read_data_filtered1; |
wire [31:0] read_data_filtered; |
wire [31:0] read_data_filtered_c; |
reg [31:0] read_data_filtered_r = 'd0; |
reg [3:0] load_rd_r = 'd0; |
wire [3:0] load_rd_c; |
|
wire write_enable_nxt; |
wire daddress_valid_nxt; |
446,10 → 457,34
// Address Valid |
// ======================================================== |
assign daddress_valid_nxt = execute && i_decode_daccess && !i_access_stall; |
assign iaddress_valid_nxt = i_decode_iaccess; |
|
// For some multi-cycle instructions, the stream of instrution |
// reads can be paused. However if the instruction does not execute |
// then the read stream must not be interrupted. |
assign iaddress_valid_nxt = i_decode_iaccess || !execute; |
|
|
// ======================================================== |
// Use read value from data memory instead of from register |
// ======================================================== |
assign rn = i_rn_use_read && i_rn_sel == load_rd_c ? read_data_filtered_c : reg_bank_rn; |
assign rm = i_rm_use_read && i_rm_sel == load_rd_c ? read_data_filtered_c : reg_bank_rm; |
assign rs = i_rs_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rs; |
assign rd = i_rd_use_read && i_rs_sel == load_rd_c ? read_data_filtered_c : reg_bank_rd; |
|
|
always@( posedge i_clk ) |
if ( i_wb_read_data_valid ) |
begin |
read_data_filtered_r <= read_data_filtered; |
load_rd_r <= i_wb_load_rd[3:0]; |
end |
|
assign read_data_filtered_c = i_wb_read_data_valid ? read_data_filtered : read_data_filtered_r; |
assign load_rd_c = i_wb_read_data_valid ? i_wb_load_rd[3:0] : load_rd_r; |
|
|
// ======================================================== |
// Register Update |
// ======================================================== |
|
576,14 → 611,15
// use one-hot version for speed, combine with i_user_mode_regs_store |
.i_mode_rds_exec ( status_bits_mode_rds_oh ), |
|
.o_rm ( rm ), |
.o_rs ( rs ), |
.o_rd ( rd ), |
.o_rn ( rn ), |
.o_rm ( reg_bank_rm ), |
.o_rs ( reg_bank_rs ), |
.o_rd ( reg_bank_rd ), |
.o_rn ( reg_bank_rn ), |
.o_pc ( pc ) |
); |
|
|
|
// ======================================================== |
// Debug - non-synthesizable code |
// ======================================================== |
/sim/wave.do
31,36 → 31,48
add wave -noupdate -group System -group {DDR3 Bus} -format Logic /tb/u_system/ddr3_reset_n |
add wave -noupdate -group System -group {DDR3 Bus} -format Logic /tb/u_system/ddr3_we_n |
add wave -noupdate -expand -group Amber -format Logic /tb/u_system/u_amber/fetch_stall |
add wave -noupdate -expand -group Amber -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/o_fetch_stall |
add wave -noupdate -expand -group Amber -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/sel_cache |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/o_stall |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/read_stall |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/o_wb_req |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal -radix ascii /tb/u_system/u_amber/u_fetch/u_cache/xC_STATE |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/miss_address |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/read_miss |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/o_read_data |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_coprocessor/o_cache_enable |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/i_core_stall |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/i_select |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/sel_cache |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/tag_wdata |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/tag_address |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/tag_wenable |
add wave -noupdate -expand -group Amber -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/data_wdata |
add wave -noupdate -expand -group Amber -format Logic /tb/u_system/u_amber/mem_stall |
add wave -noupdate -expand -group Amber -expand -group Fetch -format Literal /tb/u_system/u_amber/u_fetch/i_iaddress |
add wave -noupdate -expand -group Amber -expand -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/i_iaddress_valid |
add wave -noupdate -expand -group Amber -expand -group Fetch -format Literal /tb/u_system/u_amber/u_fetch/o_fetch_instruction |
add wave -noupdate -expand -group Amber -expand -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/o_wb_req |
add wave -noupdate -expand -group Amber -expand -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/o_fetch_stall |
add wave -noupdate -expand -group Amber -expand -group Fetch -format Logic /tb/u_system/u_amber/u_fetch/sel_cache |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/o_stall |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/read_stall |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/o_wb_req |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Literal -radix ascii /tb/u_system/u_amber/u_fetch/u_cache/xC_STATE |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/miss_address |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/read_miss |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/o_read_data |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_coprocessor/o_cache_enable |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/i_core_stall |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/i_select |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/sel_cache |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/tag_wdata |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/tag_address |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Logic /tb/u_system/u_amber/u_fetch/u_cache/tag_wenable |
add wave -noupdate -expand -group Amber -expand -group Fetch -group {Instruction Cache} -format Literal /tb/u_system/u_amber/u_fetch/u_cache/data_wdata |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal -radix ascii /tb/u_system/u_amber/u_decode/xTYPE |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal -radix ascii /tb/u_system/u_amber/u_decode/xMODE |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal -radix ascii /tb/u_system/u_amber/u_decode/xCONTROL_STATE |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/instruction_execute |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/decode_iaccess_nxt |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/interrupt |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal /tb/u_system/u_amber/u_decode/mtrans_num_registers |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/pre_fetch_instruction_wen |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal /tb/u_system/u_amber/u_decode/fetch_instruction_r |
add wave -noupdate -expand -group Amber -expand -group Decode -format Literal /tb/u_system/u_amber/u_decode/instruction |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/instruction_valid |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/instruction_execute |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/saved_current_instruction_wen |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/use_saved_current_instruction |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/pc_wen_nxt |
add wave -noupdate -expand -group Amber -expand -group Decode -format Logic /tb/u_system/u_amber/u_decode/write_pc |
add wave -noupdate -expand -group Amber -expand -group Decode -expand -group Conflict -format Logic /tb/u_system/u_amber/u_decode/instruction_valid |
add wave -noupdate -expand -group Amber -expand -group Decode -expand -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rn_conflict1 |
add wave -noupdate -expand -group Amber -expand -group Decode -expand -group Conflict -format Logic /tb/u_system/u_amber/u_decode/rn_conflict2 |
add wave -noupdate -expand -group Amber -expand -group Decode -expand -group Conflict -format Logic /tb/u_system/u_amber/u_decode/conflict1 |
add wave -noupdate -expand -group Amber -expand -group Decode -expand -group Conflict -format Logic /tb/u_system/u_amber/u_decode/conflict2 |
add wave -noupdate -expand -group Amber -group Execute -format Logic /tb/u_system/u_amber/u_execute/execute |
add wave -noupdate -expand -group Amber -group Execute -format Literal -radix ascii /tb/u_system/u_amber/u_decode/u_decompile/xINSTRUCTION_EXECUTE |
add wave -noupdate -expand -group Amber -group Execute -format Literal /tb/u_system/u_amber/u_execute/i_pc_sel |
add wave -noupdate -expand -group Amber -group Execute -expand -group Registers -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r0 |
95,6 → 107,7
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_cyc |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_stb |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/i_wb_ack |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/u_wishbone/o_wb_adr |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/o_wb_dat |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Literal /tb/u_system/u_amber/o_wb_sel |
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/o_wb_we |
102,12 → 115,8
add wave -noupdate -expand -group Amber -group Wishbone -expand -group {WB Bus} -format Logic /tb/u_system/u_amber/i_wb_err |
add wave -noupdate -expand -group Amber -group Co-Processor -format Literal /tb/u_system/u_amber/u_coprocessor/fault_address |
add wave -noupdate -expand -group Amber -group Co-Processor -format Literal /tb/u_system/u_amber/u_coprocessor/fault_status |
add wave -noupdate -format Literal /tb/u_system/u_amber/u_execute/pc |
add wave -noupdate -format Literal /tb/u_system/u_amber/u_execute/u_register_bank/r14_irq |
add wave -noupdate -format Literal /tb/u_system/u_amber/u_execute/i_pc_sel |
add wave -noupdate -format Logic /tb/u_system/u_amber/u_execute/pc_wen |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {44481286 ps} 0} {{Cursor 3} {10386717250 ps} 0} |
WaveRestoreCursors {{Cursor 1} {1138913 ps} 0} {{Cursor 3} {10386717250 ps} 0} |
configure wave -namecolwidth 279 |
configure wave -valuecolwidth 174 |
configure wave -justifyvalue left |
122,4 → 131,4
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {57117684 ps} {57628017 ps} |
WaveRestoreZoom {913193 ps} {1614177 ps} |