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URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

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  • This comparison shows the changes necessary to convert path 
    /amber/trunk/hw
    from Rev 42 to Rev 43
    ↔ Reverse comparison
  •

Rev 42 → Rev 43

/vlog/system/clocks_resets.v
167,7 → 167,7
(
.CLKIN1_PERIOD ( 5 ), // 200 MHz
.CLKOUT2_DIVIDE ( `AMBER_CLK_DIVIDER ),
.CLKFBOUT_MULT_F ( 5 ) // 200 MHz x 5 = 1000 MHz
.CLKFBOUT_MULT_F ( 6 ) // 200 MHz x 6 = 1200 MHz
)
u_pll_adv
(
/vlog/system/system_config_defines.v
55,7 → 55,11
//
// Note that for FPGA synthesis this value is overridden
// by a value specified in $AMBER_BASE/hw/fpga/bin/Makefile
`define AMBER_CLK_DIVIDER 20
`ifdef XILINX_VIRTEX6_FPGA
`define AMBER_CLK_DIVIDER 13
`else
`define AMBER_CLK_DIVIDER 20
`endif
 
// Specify a device, if none defined then the
// generic library is used which is the fastest for simulations
/vlog/amber23/a23_config_defines.v
49,7 → 49,7
// 3 ways -> 12KB cache
// 4 ways -> 16KB cache
// 8 ways -> 32KB cache
`define A23_CACHE_WAYS 8
`define A23_CACHE_WAYS 4
 
// --------------------------------------------------------------------
// Debug switches
/sim/run_log_a23.do
1,7 → 1,7
log -r /tb/u_system/u_amber/u_fetch/*
log -r /tb/u_system/u_amber/u_execute/*
log -r /tb/u_system/u_amber/u_decode/*
log /tb/u_system/u_amber/u_execute/u_register_bank/*
log /tb/u_system/u_amber/u_decode/*
 
log /tb/clk_count
log /tb/u_system/u_uart0/i_uart_rxd
/fpga/bin/Makefile
71,7 → 71,7
# For Spartan-6 divide 800MHz by this number to get the frequency
# e.g. AMBER_CLK_DIVIDER=24
# 800 MHz / 24 = 33.33 MHz
# For Virtex-6 divide 1000MHz by this number to get the frequency
# For Virtex-6 divide 1200MHz by this number to get the frequency
 
# Select either the A23 or A25 core
ifdef A25
85,7 → 85,7
ifdef VIRTEX6
# Virtex-6 device
XILINX_FPGA = xc6vlx75tff784-3
XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=12
XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=15
# Xilinx placement and timing constraints
XST_CONST_FILE = xv6_constraints.ucf
# List of verilog source files for Xilinx Virtex-6 device
93,7 → 93,7
else
# The spartan6 device used on SP605 Development board
XILINX_FPGA = xc6slx45tfgg484-3
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=18
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20
# Xilinx placement and timing constraints
XST_CONST_FILE = xs6_constraints.ucf
# List of verilog source files for Xilinx Spartan-6 device
236,20 → 236,20
# ----------------------------------------------------
$(WORK_FOLDER)/$(RTL_TOP).map.ncd : $(WORK_FOLDER)/$(RTL_TOP).ngd
cd $(WORK_FOLDER); \
map -intstyle xflow \
-p $(XILINX_FPGA) \
-ol high \
-t $(MAP_SEED) \
-w \
-ignore_keep_hierarchy \
-detail \
-timing \
-register_duplication \
-lc auto \
-xe c -mt off -ir off \
-pr off -power off \
-o $(RTL_TOP).map.ncd \
$(RTL_TOP).ngd \
map -intstyle xflow \
-p $(XILINX_FPGA) \
-ol high \
-t $(MAP_SEED) \
-w \
-ignore_keep_hierarchy \
-detail \
-timing \
-register_duplication on \
-lc auto \
-xe c -mt off -ir off \
-pr off -power off \
-o $(RTL_TOP).map.ncd \
$(RTL_TOP).ngd \
$(RTL_TOP).pcf
cp $(WORK_FOLDER)/$(RTL_TOP).map.mrp $(LOG_FOLDER)/$(RTL_TOP).map.$(RUN_ID).mrp
/fpga
fpga Property changes : Modified: svn:ignore ## -1,3 +1,4 ## bitfiles work0 +work1 logs

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