OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /amber/trunk
    from Rev 62 to Rev 63
    ↔ Reverse comparison
  •

Rev 62 → Rev 63

/hw/tools/all.sh
66,7 → 66,7
mlas_bug inflate_bug swp_lock_bug \
cache_swap_bug \
"
LOG_FILE=$1
LOG_FILE=tests.log
 
echo "----------------------------------" >> ${LOG_FILE}
date >> ${LOG_FILE}
73,7 → 73,7
 
for i in $TEST_LIST; do
echo "Run test $i"
../tools/run.sh ${i} $2 $3
../tools/run.sh ${i} $1 $2 $3
done
 
echo "----------------------------------" >> ${LOG_FILE}
/hw/isim/amber-isim.prj
0,0 → 1,80
verilog work ../vlog/system/boot_mem32.v
verilog work ../vlog/system/boot_mem128.v
verilog work ../vlog/system/clocks_resets.v
verilog work ../vlog/system/interrupt_controller.v
verilog work ../vlog/system/system.v
verilog work ../vlog/system/test_module.v
verilog work ../vlog/system/timer_module.v
verilog work ../vlog/system/uart.v
verilog work ../vlog/system/wb_xs6_ddr3_bridge.v
verilog work ../vlog/system/wishbone_arbiter.v
verilog work ../vlog/system/afifo.v
verilog work ../vlog/system/ddr3_afifo.v
verilog work ../vlog/system/ethmac_wb.v
verilog work ../vlog/system/main_mem.v
 
verilog work ../vlog/ethmac/eth_clockgen.v
verilog work ../vlog/ethmac/eth_crc.v
verilog work ../vlog/ethmac/eth_fifo.v
verilog work ../vlog/ethmac/eth_maccontrol.v
verilog work ../vlog/ethmac/eth_macstatus.v
verilog work ../vlog/ethmac/eth_miim.v
verilog work ../vlog/ethmac/eth_outputcontrol.v
verilog work ../vlog/ethmac/eth_random.v
verilog work ../vlog/ethmac/eth_receivecontrol.v
verilog work ../vlog/ethmac/eth_registers.v
verilog work ../vlog/ethmac/eth_register.v
verilog work ../vlog/ethmac/eth_rxaddrcheck.v
verilog work ../vlog/ethmac/eth_rxcounters.v
verilog work ../vlog/ethmac/eth_rxethmac.v
verilog work ../vlog/ethmac/eth_rxstatem.v
verilog work ../vlog/ethmac/eth_shiftreg.v
verilog work ../vlog/ethmac/eth_spram_256x32.v
verilog work ../vlog/ethmac/eth_top.v
verilog work ../vlog/ethmac/eth_transmitcontrol.v
verilog work ../vlog/ethmac/eth_txcounters.v
verilog work ../vlog/ethmac/eth_txethmac.v
verilog work ../vlog/ethmac/eth_txstatem.v
verilog work ../vlog/ethmac/eth_wishbone.v
verilog work ../vlog/ethmac/xilinx_dist_ram_16x32.v
 
verilog work ../vlog/amber23/a23_alu.v
verilog work ../vlog/amber23/a23_barrel_shift.v
verilog work ../vlog/amber23/a23_cache.v
verilog work ../vlog/amber23/a23_coprocessor.v
verilog work ../vlog/amber23/a23_core.v
verilog work ../vlog/amber23/a23_decode.v
verilog work ../vlog/amber23/a23_decompile.v
verilog work ../vlog/amber23/a23_execute.v
verilog work ../vlog/amber23/a23_fetch.v
verilog work ../vlog/amber23/a23_multiply.v
verilog work ../vlog/amber23/a23_register_bank.v
verilog work ../vlog/amber23/a23_wishbone.v
 
 
verilog work ../vlog/amber25/a25_alu.v
verilog work ../vlog/amber25/a25_barrel_shift.v
verilog work ../vlog/amber25/a25_shifter.v
verilog work ../vlog/amber25/a25_coprocessor.v
verilog work ../vlog/amber25/a25_core.v
verilog work ../vlog/amber25/a25_dcache.v
verilog work ../vlog/amber25/a25_decode.v
verilog work ../vlog/amber25/a25_decompile.v
verilog work ../vlog/amber25/a25_execute.v
verilog work ../vlog/amber25/a25_fetch.v
verilog work ../vlog/amber25/a25_icache.v
verilog work ../vlog/amber25/a25_mem.v
verilog work ../vlog/amber25/a25_multiply.v
verilog work ../vlog/amber25/a25_register_bank.v
verilog work ../vlog/amber25/a25_wishbone.v
verilog work ../vlog/amber25/a25_wishbone_buf.v
verilog work ../vlog/amber25/a25_write_back.v
 
verilog work ../vlog/lib/generic_iobuf.v
verilog work ../vlog/lib/generic_sram_byte_en.v
verilog work ../vlog/lib/generic_sram_line_en.v
 
verilog work ../vlog/tb/tb_uart.v
verilog work ../vlog/tb/eth_test.v
verilog work ../vlog/tb/dumpvcd.v
verilog work ../vlog/tb/tb.v
/hw/isim/all.sh
0,0 → 1,80
#!/bin/bash
 
#--------------------------------------------------------------#
# #
# all.sh #
# #
# This file is part of the Amber project #
# http://www.opencores.org/project,amber #
# #
# Description #
# Runa list of tests from the $AMBER_BASE/hw/tests directory #
# #
# Author(s): #
# - Conor Santifort, santifort@opencores.org #
# #
#//////////////////////////////////////////////////////////////#
# #
# Copyright (C) 2010 Authors and OPENCORES.ORG #
# #
# This source file may be used and distributed without #
# restriction provided that this copyright statement is not #
# removed from the file and that any derivative work contains #
# the original copyright notice and the associated disclaimer. #
# #
# This source file is free software; you can redistribute it #
# and/or modify it under the terms of the GNU Lesser General #
# Public License as published by the Free Software Foundation; #
# either version 2.1 of the License, or (at your option) any #
# later version. #
# #
# This source is distributed in the hope that it will be #
# useful, but WITHOUT ANY WARRANTY; without even the implied #
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #
# PURPOSE. See the GNU Lesser General Public License for more #
# details. #
# #
# You should have received a copy of the GNU Lesser General #
# Public License along with this source; if not, download it #
# from http://www.opencores.org/lgpl.shtml #
# #
#--------------------------------------------------------------#
 
TEST_LIST="
add adc sub sbc barrel_shift barrel_shift_rs \
change_sbits change_mode \
bl bcc \
ldr ldr_str_pc strb \
ldm1 ldm2 ldm3 ldm4 stm1 stm2 ldm_stm_onetwo stm_stream \
mul mla \
swp \
\
irq firq swi undefined_ins addr_ex irq_stm irq_disable \
\
cache1 cache2 cache3 cache_swap \
cacheable_area cache_flush \
\
flow1 flow2 flow3 conflict_rd \
\
hiboot_mem ddr31 ddr32 ddr33 \
\
ethmac_reg ethmac_mem ethmac_tx \
\
uart_reg uart_tx uart_rx uart_rxint \
\
bic_bug movs_bug flow_bug \
mlas_bug inflate_bug swp_lock_bug \
cache_swap_bug \
"
LOG_FILE=all.log
 
echo "----------------------------------" >> ${LOG_FILE}
date >> ${LOG_FILE}
 
for i in $TEST_LIST; do
echo "Run test $i"
./run.sh ${i} $2 $3
done
 
echo "----------------------------------" >> ${LOG_FILE}
 
hw/isim/all.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hw/isim/run.do =================================================================== --- hw/isim/run.do (nonexistent) +++ hw/isim/run.do (revision 63) @@ -0,0 +1 @@ +run all Index: hw/isim/run.sh =================================================================== --- hw/isim/run.sh (nonexistent) +++ hw/isim/run.sh (revision 63) @@ -0,0 +1,277 @@ +#!/bin/bash + +#--------------------------------------------------------------# +# # +# run.sh # +# # +# This file is part of the Amber project # +# http://www.opencores.org/project,amber # +# # +# Description # +# Run a Verilog simulation using Modelsim # +# # +# Author(s): # +# - Conor Santifort, csantifort.amber@gmail.com # +# # +#//////////////////////////////////////////////////////////////# +# # +# Copyright (C) 2013 Authors and OPENCORES.ORG # +# # +# This source file may be used and distributed without # +# restriction provided that this copyright statement is not # +# removed from the file and that any derivative work contains # +# the original copyright notice and the associated disclaimer. # +# # +# This source file is free software; you can redistribute it # +# and/or modify it under the terms of the GNU Lesser General # +# Public License as published by the Free Software Foundation; # +# either version 2.1 of the License, or (at your option) any # +# later version. # +# # +# This source is distributed in the hope that it will be # +# useful, but WITHOUT ANY WARRANTY; without even the implied # +# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR # +# PURPOSE. See the GNU Lesser General Public License for more # +# details. # +# # +# You should have received a copy of the GNU Lesser General # +# Public License along with this source; if not, download it # +# from http://www.opencores.org/lgpl.shtml # +# # +#--------------------------------------------------------------# + +#-------------------------------------------------------- +# Defaults +#-------------------------------------------------------- +AMBER_LOAD_MAIN_MEM=" " +AMBER_TIMEOUT=0 +AMBER_LOG_FILE="tests.log" +SET_G=0 +SET_M=0 +SET_T=0 +SET_S=0 +SET_A=0 +SET_5=0 +SET_L=0 + + +# show program usage +show_usage() { + echo "Usage:" + echo "run [-a] [-g] [-d] [-t] [-s] [-v]" + echo " -h : Help" + echo " -a : Run hardware tests (all tests in \$AMBER_BASE/hw/tests)" + echo " -g : Use ISIM GUI" + echo " -l : Create dump of complete design" + echo " -s : Use Xilinx Spatran6 Libraries (slower sim)" + echo " -5 : Use Amber25 core instead of Amber23 core" + echo "" + exit +} + + +#-------------------------------------------------------- +# Parse command-line options +#-------------------------------------------------------- + +# Minimum number of arguments needed by this program +MINARGS=1 + +# show usage if '-h' or '--help' is the first argument or no argument is given +case $1 in + ""|"-h"|"--help"|"help"|"?") show_usage ;; +esac + +# get the number of command-line arguments given +ARGC=$# + +# check to make sure enough arguments were given or exit +if [[ $ARGC -lt $MINARGS ]] ; then + echo "Too few arguments given (Minimum:$MINARGS)" + echo + show_usage +fi + +# self-sorting argument types LongEquals, ShortSingle, ShortSplit, and ShortMulti +# process command-line arguments +while [ "$1" ] +do + case $1 in + -*) true ; + case $1 in + -a) SET_A=1 # all tests + shift ;; + -s) SET_S=1 # Xilinx Spartan6 libs + shift ;; + -5) SET_5=1 # Amber25 core (default is Amber23 core) + shift ;; + -g) SET_G=1 # Bring up GUI + shift ;; + -l) SET_L=1 # Create wave dump file + shift ;; + -*) + echo "Unrecognized argument $1" + shift ;; + esac ;; + * ) AMBER_TEST_NAME=$1 + shift ;; + + esac +done + + +if [ $SET_5 == 1 ]; then + AMBER_CORE="+define+AMBER_A25_CORE" +else + AMBER_CORE=" " +fi + + + +#-------------------------------------------------------- +# Compile the test +#-------------------------------------------------------- + +# First check if its an assembly test +if [ -f ../tests/${AMBER_TEST_NAME}.S ]; then + # hw-test + TEST_TYPE=1 +elif [ ${AMBER_TEST_NAME} == vmlinux ]; then + TEST_TYPE=3 +elif [ -d ../../sw/${AMBER_TEST_NAME} ]; then + # Does this test type need the boot-loader ? + if [ -e ../../sw/${AMBER_TEST_NAME}/sections.lds ]; then + grep 8000 ../../sw/${AMBER_TEST_NAME}/sections.lds > /dev/null + if [ $? == 0 ]; then + # Needs boot loader, starts at 0x8000 + TEST_TYPE=4 + else + TEST_TYPE=2 + fi + else + TEST_TYPE=2 + fi +else + echo "Test ${AMBER_TEST_NAME} not found" + exit +fi + +echo "Test ${AMBER_TEST_NAME}, type $TEST_TYPE" + +# Uncompress the vmlinux.mem file +if [ $TEST_TYPE == 3 ]; then + pushd ../../sw/${AMBER_TEST_NAME} > /dev/null + if [ ! -e vmlinux.mem ]; then + bzip2 -dk vmlinux.mem.bz2 + bzip2 -dk vmlinux.dis.bz2 + fi + popd > /dev/null +fi + + +# Now compile the test +if [ $TEST_TYPE == 1 ]; then + # hw assembly test + echo "Compile ../tests/${AMBER_TEST_NAME}.S" + pushd ../tests > /dev/null + make --quiet TEST=${AMBER_TEST_NAME} + MAKE_STATUS=$? + + popd > /dev/null + BOOT_MEM_FILE="../tests/${AMBER_TEST_NAME}.mem" + + if [ $SET_5 == 1 ]; then + BOOT_MEM_PARAMS_FILE="../tests/${AMBER_TEST_NAME}_memparams128.v" + else + BOOT_MEM_PARAMS_FILE="../tests/${AMBER_TEST_NAME}_memparams32.v" + fi + +elif [ $TEST_TYPE == 2 ]; then + # sw Stand-alone C test + pushd ../../sw/${AMBER_TEST_NAME} > /dev/null + make CPPFLAGS=-DSIM_MODE + MAKE_STATUS=$? + popd > /dev/null + BOOT_MEM_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}.mem" + if [ $SET_5 == 1 ]; then + BOOT_MEM_PARAMS_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}_memparams128.v" + else + BOOT_MEM_PARAMS_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}_memparams32.v" + fi + +elif [ $TEST_TYPE == 3 ] || [ $TEST_TYPE == 4 ]; then + # sw test using boot loader + pushd ../../sw/boot-loader > /dev/null + make + MAKE_STATUS=$? + popd > /dev/null + if [ $MAKE_STATUS != 0 ]; then + echo "Error compiling boot-loader" + exit 1 + fi + + pushd ../../sw/${AMBER_TEST_NAME} > /dev/null + if [ -e Makefile ]; then + make + fi + MAKE_STATUS=$? + popd > /dev/null + + BOOT_MEM_FILE="../../sw/boot-loader/boot-loader.mem" + if [ $SET_5 == 1 ]; then + BOOT_MEM_PARAMS_FILE="../../sw/boot-loader/boot-loader_memparams128.v" + else + BOOT_MEM_PARAMS_FILE="../../sw/boot-loader/boot-loader_memparams32.v" + fi + MAIN_MEM_FILE="../../sw/${AMBER_TEST_NAME}/${AMBER_TEST_NAME}.mem" + AMBER_LOAD_MAIN_MEM="-d AMBER_LOAD_MAIN_MEM" + +else + echo "Error unrecognized test type" +fi + +if [ $MAKE_STATUS != 0 ]; then + echo "Failed " $AMBER_TEST_NAME " compile error" >> $AMBER_LOG_FILE + exit +fi + + + +#-------------------------------------------------------- +# ISIM +#-------------------------------------------------------- +fuse tb -o amber-test.exe -prj amber-isim.prj \ + -d BOOT_MEM_FILE=\"$BOOT_MEM_FILE\" \ + -d BOOT_MEM_PARAMS_FILE=\"$BOOT_MEM_PARAMS_FILE\" \ + -d MAIN_MEM_FILE=\"$MAIN_MEM_FILE\" \ + -d AMBER_LOG_FILE=\"$AMBER_LOG_FILE\" \ + -d AMBER_TEST_NAME=\"$AMBER_TEST_NAME\" \ + -d AMBER_SIM_CTRL=$TEST_TYPE \ + -d AMBER_TIMEOUT=$AMBER_TIMEOUT \ + $AMBER_LOAD_MAIN_MEM \ + -incremental \ + -i ../vlog/lib \ + -i ../vlog/system \ + -i ../vlog/amber23 \ + -i ../vlog/amber25 \ + -i ../vlog/tb + +if [ $? != 0 ]; then exit; fi + +if [ $SET_G == 1 ]; then + ./amber-test.exe -tclbatch run.do -gui +else + ./amber-test.exe -tclbatch run.do +fi + + +# Set a timeout value for the test if it passed +if [ $TEST_TYPE == 1 ]; then + tail -1 < ${AMBER_LOG_FILE} | grep Passed > /dev/null + if [ $? == 0 ]; then + TICKS=`tail -1 < ${AMBER_LOG_FILE} | awk '{print $3}'` + TOTICKS=$(( $TICKS * 4 + 1000 )) + ../tools/set_timeout.sh ${AMBER_TEST_NAME} $TOTICKS + fi +fi +
hw/isim/run.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: hw/vlog/xv6_ddr3 =================================================================== --- hw/vlog/xv6_ddr3 (revision 62) +++ hw/vlog/xv6_ddr3 (nonexistent)
hw/vlog/xv6_ddr3 Property changes : Deleted: svn:ignore ## -1,53 +0,0 ## -arb_mux.v -arb_row_col.v -arb_select.v -bank_cntrl.v -bank_common.v -bank_compare.v -bank_mach.v -bank_queue.v -bank_state.v -circ_buffer.v -clk_ibuf.v -col_mach.v -ddr2_ddr3_chipscope.v -ecc_buf.v -ecc_dec_fix.v -ecc_gen.v -ecc_merge_enc.v -infrastructure.v -iodelay_ctrl.v -mc.v -memc_ui_top.v -mem_intfc.v -phy_ck_iob.v -phy_clock_io.v -phy_control_io.v -phy_data_io.v -phy_dly_ctrl.v -phy_dm_iob.v -phy_dq_iob.v -phy_dqs_iob.v -phy_init.v -phy_ocb_mon_top.v -phy_ocb_mon.v -phy_pd_top.v -phy_pd.v -phy_rdclk_gen.v -phy_rdctrl_sync.v -phy_rddata_sync.v -phy_rdlvl.v -phy_read.v -phy_top.v -phy_write.v -phy_wrlvl.v -rank_cntrl.v -rank_common.v -rank_mach.v -rd_bitslip.v -round_robin_arb.v -ui_cmd.v -ui_rd_data.v -ui_top.v -ui_wr_data.v -xv6_ddr3.v Index: hw/vlog/system/wb_xv6_ddr3_bridge.v =================================================================== --- hw/vlog/system/wb_xv6_ddr3_bridge.v (revision 62) +++ hw/vlog/system/wb_xv6_ddr3_bridge.v (nonexistent) @@ -1,291 +0,0 @@ -////////////////////////////////////////////////////////////////// -// // -// Wishbone Slave to Xilinx Virtex-6 DDR3 controller // -// Bridge // -// // -// This file is part of the Amber project // -// http://www.opencores.org/project,amber // -// // -// Description // -// Converts wishbone read and write accesses to the signalling // -// used by the Xilinx DDR3 Controller in Virtex-6 FPGAs. // -// // -// The MCB is confgiured with a single 128-bit port. // -// // -// Author(s): // -// - Conor Santifort, csantifort.amber@gmail.com // -// // -////////////////////////////////////////////////////////////////// -// // -// Copyright (C) 2010 Authors and OPENCORES.ORG // -// // -// This source file may be used and distributed without // -// restriction provided that this copyright statement is not // -// removed from the file and that any derivative work contains // -// the original copyright notice and the associated disclaimer. // -// // -// This source file is free software; you can redistribute it // -// and/or modify it under the terms of the GNU Lesser General // -// Public License as published by the Free Software Foundation; // -// either version 2.1 of the License, or (at your option) any // -// later version. // -// // -// This source is distributed in the hope that it will be // -// useful, but WITHOUT ANY WARRANTY; without even the implied // -// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // -// PURPOSE. See the GNU Lesser General Public License for more // -// details. // -// // -// You should have received a copy of the GNU Lesser General // -// Public License along with this source; if not, download it // -// from http://www.opencores.org/lgpl.shtml // -// // -////////////////////////////////////////////////////////////////// - - -module wb_xv6_ddr3_bridge #( -parameter WB_DWIDTH = 32, -parameter WB_SWIDTH = 4 -)( -input i_sys_clk, -input i_ddr_clk, - -input i_mem_ctrl, // 0=128MB, 1=32MB - -// Wishbone Ports -input [31:0] i_wb_adr, -input [WB_SWIDTH-1:0] i_wb_sel, -input i_wb_we, -output [WB_DWIDTH-1:0] o_wb_dat, -input [WB_DWIDTH-1:0] i_wb_dat, -input i_wb_cyc, -input i_wb_stb, -output o_wb_ack, -output o_wb_err, - -input i_phy_init_done, -output o_phy_init_done, - -output o_ddr_cmd_en, // Command Enable -output [2:0] o_ddr_cmd_instr, // write = 000, read = 001 -output [26:0] o_ddr_cmd_byte_addr, // Memory address -input i_ddr_cmd_full, // DDR3 I/F Command FIFO is full - -input i_ddr_wr_full, // DDR3 I/F Write Data FIFO is full -output o_ddr_wr_en, // Write data enable -output o_ddr_wr_end, // Mark the second 64-byte word of the transfer -output [7:0] o_ddr_wr_mask, // 1 bit per byte -output [63:0] o_ddr_wr_data, // 8 bytes write data - -input [63:0] i_ddr_rd_data, // 8 bytes of read data -input i_ddr_rd_valid // low when read data is valid - -); - -wire start_write; -wire start_read; -wire busy; -reg read_busy = 1'd0; - -wire cmd_en; -wire [2:0] cmd_instr; -wire [26:0] cmd_addr; -wire cmd_full; -wire wr_full; -wire rd_valid; -wire [26:0] ddr_cmd_byte_addr; -wire [WB_DWIDTH-1:0] ddr_wr_data; -wire [WB_DWIDTH-1:0] ddr_rd_data; -wire [WB_SWIDTH-1:0] ddr_wr_mask; -wire [7:0] wr_mask64; -wire [1:0] ddr_wr_addr_32; -wire ddr_addr2; -reg ddr_addr2_r = 1'd0; -wire ddr_addr4; -reg ddr_addr4_r = 1'd0; -wire ddr_wr_en; -reg ddr_wr_en_r = 1'd0; -wire ddr_rd_valid; -reg ddr_rd_valid_r = 1'd0; -reg ddr_rd_valid_r2 = 1'd0; - -reg cmd_en_r = 'd0; -reg [2:0] cmd_instr_r = 'd0; -reg [26:0] cmd_addr_r = 'd0; -reg [11:0] phy_init_count = 'd0; -reg [63:0] ddr_rd_data_r = 'd0; - - -assign o_wb_err = 'd0; -assign o_wb_ack = i_wb_stb && ( start_write || rd_valid ); -assign o_ddr_cmd_byte_addr = {ddr_cmd_byte_addr[26:3], 3'd0}; -assign ddr_addr2 = ddr_cmd_byte_addr[2]; -assign ddr_addr4 = ddr_cmd_byte_addr[4]; - -assign o_ddr_wr_en = ddr_wr_en | ddr_wr_en_r; -assign o_ddr_wr_end = ddr_wr_en_r; - -generate -if (WB_DWIDTH == 128) begin : wb128 - reg [63:0] ddr_wr_data_r = 'd0; - reg [7:0] ddr_wr_mask_r = 'd0; - - always @(posedge i_ddr_clk) - begin - ddr_wr_data_r <= ddr_wr_data[127:64]; - ddr_wr_mask_r <= ddr_wr_mask[15:8]; - end - - assign o_ddr_wr_data = ddr_wr_en_r ? ddr_wr_data_r : ddr_wr_data[63:00]; - assign o_ddr_wr_mask = ddr_wr_en_r ? ddr_wr_mask_r : ddr_wr_mask[7:0] ; - assign ddr_rd_valid = ddr_rd_valid_r && !ddr_rd_valid_r2; - assign ddr_rd_data = {i_ddr_rd_data, ddr_rd_data_r} ; -end -else begin : wb32 - assign o_ddr_wr_data = ddr_wr_en_r ? 64'h0 : {2{ddr_wr_data}}; - assign o_ddr_wr_mask = ddr_wr_en_r ? 8'hff : wr_mask64; - assign wr_mask64 = ddr_wr_addr_32[0] ? {ddr_wr_mask, 4'hf} : {4'hf, ddr_wr_mask} ; - assign ddr_rd_valid = i_ddr_rd_valid && !ddr_rd_valid_r; - assign ddr_rd_data = ddr_addr2_r ? i_ddr_rd_data[63:32] : i_ddr_rd_data[31:00]; -end -endgenerate - -assign start_write = i_wb_stb && i_wb_we && !busy; -assign start_read = i_wb_stb && !i_wb_we && !busy; -assign busy = cmd_full | wr_full | read_busy; - -assign cmd_en = start_write || start_read; -assign cmd_instr = start_write ? 3'd0 : 3'd1; -assign cmd_addr = i_mem_ctrl ? {2'd0, i_wb_adr[24:0]} : i_wb_adr[26:0]; - - - -always @( posedge i_ddr_clk ) - ddr_rd_data_r <= i_ddr_rd_data; - - -// Delay the phy_init_done signal. -// The memory model issues an error if -// it is accesses striaght away after -// phy_init_done done go9es high. May be a -// configuration issue, but this is a simple work -// around -always @( posedge i_sys_clk ) - if ( i_phy_init_done && !o_phy_init_done ) - phy_init_count <= phy_init_count + 1'd1; - -assign o_phy_init_done = phy_init_count == 12'hfff; - - -// Use the read_busy reg to gate start_read -// so that it only pulses high for 1 tick at the -// start of a read sequence -always @( posedge i_sys_clk ) - if ( rd_valid ) - read_busy <= 1'd0; - else if ( start_read ) - read_busy <= 1'd1; - - -always @( posedge i_sys_clk ) - if ( !cmd_full ) - begin - cmd_en_r <= cmd_en; - cmd_instr_r <= cmd_instr; - cmd_addr_r <= cmd_addr; - end - - -always @( posedge i_ddr_clk ) - begin - ddr_wr_en_r <= ddr_wr_en; - ddr_rd_valid_r <= i_ddr_rd_valid; - ddr_rd_valid_r2 <= ddr_rd_valid_r; - if ( o_ddr_cmd_en ) - begin - ddr_addr2_r <= ddr_addr2; - ddr_addr4_r <= ddr_addr4; - end - end - - -ddr3_afifo#( - .ADDR_WIDTH ( 27 ), - .DATA_WIDTH ( WB_DWIDTH ) - ) - u_ddr3_afifo ( - .i_sys_clk ( i_sys_clk ), - .i_ddr_clk ( i_ddr_clk ), - - // Wishbone Side - .i_cmd_en ( cmd_en_r ), - .i_cmd_instr ( cmd_instr_r ), - .i_cmd_byte_addr ( cmd_addr_r ), - .o_cmd_full ( cmd_full ), - - .o_wr_full ( wr_full ), - .i_wr_en ( start_write ), - .i_wr_mask ( ~i_wb_sel ), - .i_wr_data ( i_wb_dat ), - .i_wr_addr_32 ( i_wb_adr[3:2] ), - - .o_rd_data ( o_wb_dat ), - .o_rd_valid ( rd_valid ), - - // DDR3 Side - .o_ddr_cmd_en ( o_ddr_cmd_en ), - .o_ddr_cmd_instr ( o_ddr_cmd_instr ), - .o_ddr_cmd_byte_addr ( ddr_cmd_byte_addr ), - .i_ddr_cmd_full ( i_ddr_cmd_full ), - - .i_ddr_wr_full ( i_ddr_wr_full ), - .o_ddr_wr_en ( ddr_wr_en ), - .o_ddr_wr_mask ( ddr_wr_mask ), - .o_ddr_wr_data ( ddr_wr_data ), - .o_ddr_wr_addr_32 ( ddr_wr_addr_32 ), - - .i_ddr_rd_data ( ddr_rd_data ), - .i_ddr_rd_valid ( ddr_rd_valid ) - ); - - -// ======================================================================================= -// ======================================================================================= -// ======================================================================================= -// Non-synthesizable debug code -// ======================================================================================= - - -//synopsys translate_off -reg [7:0] cmd_full_count = 8'hff; - -always @( posedge i_ddr_clk ) - begin - if ( o_ddr_cmd_en && !i_ddr_cmd_full ) - cmd_full_count <= 'd0; - else if ( cmd_full_count != 8'hff ) - begin - if ( i_ddr_cmd_full ) - begin - if ( cmd_full_count != 8'hfe ) - cmd_full_count <= cmd_full_count + 1'd1; - else - cmd_full_count <= 'd0; - end - else - cmd_full_count <= 'd0; - end - - if ( cmd_full_count == 8'hfe ) - begin - `TB_ERROR_MESSAGE - $display("Virtex-6 DDR3 Command I/F stuck full"); - end - end - - -//synopsys translate_on - -endmodule - - Index: hw/vlog/system/uart.v =================================================================== --- hw/vlog/system/uart.v (revision 62) +++ hw/vlog/system/uart.v (revision 63) @@ -52,6 +52,7 @@ ////////////////////////////////////////////////////////////////// `include "system_config_defines.v" +`include "global_defines.v" // Normally AMBER_UART_BAUD is defined in the system_config_defines.v file. `ifndef AMBER_UART_BAUD
/hw/vlog/system/timer_module.v
38,8 → 38,8
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
 
 
module timer_module #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4
/hw/vlog/system/wb_xs6_ddr3_bridge.v
41,8 → 41,8
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
 
 
module wb_xs6_ddr3_bridge #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4
/hw/vlog/system/clocks_resets.v
38,6 → 38,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "system_config_defines.v"
 
 
//
/hw/vlog/tb/tb_uart.v
39,7 → 39,10
//////////////////////////////////////////////////////////////////
 
`timescale 1 ps / 1 ps
`include "system_config_defines.v"
`include "global_defines.v"
 
 
module tb_uart (
input i_uart_cts_n, // Clear To Send
output reg o_uart_txd,
/hw/vlog/amber23/a23_functions.v
163,11 → 163,12
function [31:0] log2;
input [31:0] num;
integer i;
 
integer out;
begin
log2 = 32'd0;
out = 32'd0;
for (i=0; i<30; i=i+1)
if ((2**i > num) && (log2 == 0))
log2 = i-1;
if ((2**i > num) && (out == 0))
out = i-1;
log2 = out;
end
endfunction
/hw/vlog/amber23/a23_decompile.v
39,7 → 39,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
`include "global_defines.v"
`include "a23_config_defines.v"
 
module a23_decompile
/hw/vlog/amber23/a23_cache.v
42,7 → 42,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
`include "global_defines.v"
`include "a23_config_defines.v"
 
module a23_cache
/hw/vlog/amber23/a23_decode.v
39,8 → 39,8
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
 
 
module a23_decode
(
input i_clk,
/hw/vlog/amber25/a25_dcache.v
42,7 → 42,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
`include "global_defines.v"
`include "a25_config_defines.v"
 
module a25_dcache
/hw/vlog/amber25/a25_icache.v
40,7 → 40,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
`include "global_defines.v"
`include "a25_config_defines.v"
 
module a25_icache
/hw/vlog/amber25/a25_decode.v
39,8 → 39,8
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
 
 
module a25_decode
(
input i_clk,
/hw/vlog/amber25/a25_decompile.v
39,7 → 39,7
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
 
`include "global_defines.v"
`include "a25_config_defines.v"
 
module a25_decompile
/hw/fpga/bin/xv6_source_files.prj File deleted
/hw/fpga/bin/xv6_constraints.ucf File deleted
/hw/fpga/bin/xs6_source_files.prj
47,7 → 47,6
verilog work ../../vlog/system/timer_module.v
verilog work ../../vlog/system/uart.v
verilog work ../../vlog/system/wb_xs6_ddr3_bridge.v
verilog work ../../vlog/system/wb_xv6_ddr3_bridge.v
verilog work ../../vlog/system/wishbone_arbiter.v
verilog work ../../vlog/system/afifo.v
verilog work ../../vlog/system/ddr3_afifo.v
/hw/fpga/bin/Makefile
90,26 → 90,17
endif
 
 
## FPGA type
ifdef VIRTEX6
# Virtex-6 device
XILINX_FPGA = xc6vlx75tff784-3
XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=15 $(BOOT_LOADER_DEF)
# Xilinx placement and timing constraints
XST_CONST_FILE = xv6_constraints.ucf
# List of verilog source files for Xilinx Virtex-6 device
XST_PROJ_FILE = xv6_source_files.prj
else
# The spartan6 device used on SP605 Development board
XILINX_FPGA = xc6slx45tfgg484-3
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20 $(BOOT_LOADER_DEF)
# Xilinx placement and timing constraints
XST_CONST_FILE = xs6_constraints.ucf
# List of verilog source files for Xilinx Spartan-6 device
XST_PROJ_FILE = xs6_source_files.prj
endif
 
# The spartan6 device used on SP605 Development board
XILINX_FPGA = xc6slx45tfgg484-3
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20 $(BOOT_LOADER_DEF)
# Xilinx placement and timing constraints
XST_CONST_FILE = xs6_constraints.ucf
# List of verilog source files for Xilinx Spartan-6 device
XST_PROJ_FILE = xs6_source_files.prj
 
 
 
# ----------------------------------------------------
# Focus on speed or area
# ----------------------------------------------------
189,8 → 180,8
@echo " trce Running timing analysis. Don't run buitgen"
@echo " help Print this message"
@echo ""
@echo "Optional switches: VIRTEX6=1 A25=1 WORK=<work directory name>"
@echo "e.g. > make VIRTEX6=1 WORK=work1 map"
@echo "Optional switches: A25=1 WORK=<work directory name>"
@echo "e.g. > make A25=1 WORK=work1 map"
 
clean :
rm -Rf $(WORK_FOLDER)/*

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