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https://opencores.org/ocsvn/amber/amber/trunk
Subversion Repositories amber
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- This comparison shows the changes necessary to convert path
/amber
- from Rev 22 to Rev 23
- ↔ Reverse comparison
Rev 22 → Rev 23
/trunk/hw/fpga/bin/source_files.prj
File deleted
/trunk/hw/fpga/bin/xv6_source_files.prj
0,0 → 1,169
# ---------------------------------------------------------------- |
# // |
# Xilinx Virtex-6 FPGA synthesis Verilog source file list // |
# // |
# This file is part of the Amber project // |
# http://www.opencores.org/project,amber // |
# // |
# Description // |
# // |
# Author(s): // |
# - Conor Santifort, csantifort.amber@gmail.com // |
# // |
#/ /////////////////////////////////////////////////////////////// |
# // |
# Copyright (C) 2010 Authors and OPENCORES.ORG // |
# // |
# This source file may be used and distributed without // |
# restriction provided that this copyright statement is not // |
# removed from the file and that any derivative work contains // |
# the original copyright notice and the associated disclaimer. // |
# // |
# This source file is free software; you can redistribute it // |
# and/or modify it under the terms of the GNU Lesser General // |
# Public License as published by the Free Software Foundation; // |
# either version 2.1 of the License, or (at your option) any // |
# later version. // |
# // |
# This source is distributed in the hope that it will be // |
# useful, but WITHOUT ANY WARRANTY; without even the implied // |
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
# PURPOSE. See the GNU Lesser General Public License for more // |
# details. // |
# // |
# You should have received a copy of the GNU Lesser General // |
# Public License along with this source; if not, download it // |
# from http://www.opencores.org/lgpl.shtml // |
# // |
# ---------------------------------------------------------------- |
|
# System |
verilog work ../../vlog/system/boot_mem.v |
verilog work ../../vlog/system/clocks_resets.v |
verilog work ../../vlog/system/interrupt_controller.v |
verilog work ../../vlog/system/system.v |
verilog work ../../vlog/system/test_module.v |
verilog work ../../vlog/system/timer_module.v |
verilog work ../../vlog/system/uart.v |
verilog work ../../vlog/system/wb_xs6_ddr3_bridge.v |
verilog work ../../vlog/system/wb_xv6_ddr3_bridge.v |
verilog work ../../vlog/system/wishbone_arbiter.v |
verilog work ../../vlog/system/afifo.v |
verilog work ../../vlog/system/ddr3_afifo.v |
|
# EthMac |
verilog work ../../vlog/ethmac/eth_clockgen.v |
verilog work ../../vlog/ethmac/eth_crc.v |
verilog work ../../vlog/ethmac/eth_fifo.v |
verilog work ../../vlog/ethmac/eth_maccontrol.v |
verilog work ../../vlog/ethmac/eth_macstatus.v |
verilog work ../../vlog/ethmac/eth_miim.v |
verilog work ../../vlog/ethmac/eth_outputcontrol.v |
verilog work ../../vlog/ethmac/eth_random.v |
verilog work ../../vlog/ethmac/eth_receivecontrol.v |
verilog work ../../vlog/ethmac/eth_registers.v |
verilog work ../../vlog/ethmac/eth_register.v |
verilog work ../../vlog/ethmac/eth_rxaddrcheck.v |
verilog work ../../vlog/ethmac/eth_rxcounters.v |
verilog work ../../vlog/ethmac/eth_rxethmac.v |
verilog work ../../vlog/ethmac/eth_rxstatem.v |
verilog work ../../vlog/ethmac/eth_shiftreg.v |
verilog work ../../vlog/ethmac/eth_spram_256x32.v |
verilog work ../../vlog/ethmac/eth_top.v |
verilog work ../../vlog/ethmac/eth_transmitcontrol.v |
verilog work ../../vlog/ethmac/eth_txcounters.v |
verilog work ../../vlog/ethmac/eth_txethmac.v |
verilog work ../../vlog/ethmac/eth_txstatem.v |
verilog work ../../vlog/ethmac/eth_wishbone.v |
verilog work ../../vlog/ethmac/xilinx_dist_ram_16x32.v |
|
# Amber 23 |
verilog work ../../vlog/amber23/a23_alu.v |
verilog work ../../vlog/amber23/a23_barrel_shift.v |
verilog work ../../vlog/amber23/a23_cache.v |
verilog work ../../vlog/amber23/a23_coprocessor.v |
verilog work ../../vlog/amber23/a23_core.v |
verilog work ../../vlog/amber23/a23_decode.v |
verilog work ../../vlog/amber23/a23_execute.v |
verilog work ../../vlog/amber23/a23_fetch.v |
verilog work ../../vlog/amber23/a23_multiply.v |
verilog work ../../vlog/amber23/a23_register_bank.v |
verilog work ../../vlog/amber23/a23_wishbone.v |
|
# Amber 25 |
verilog work ../../vlog/amber25/a25_alu.v |
verilog work ../../vlog/amber25/a25_barrel_shift.v |
verilog work ../../vlog/amber25/a25_coprocessor.v |
verilog work ../../vlog/amber25/a25_core.v |
verilog work ../../vlog/amber25/a25_dcache.v |
verilog work ../../vlog/amber25/a25_decode.v |
verilog work ../../vlog/amber25/a25_execute.v |
verilog work ../../vlog/amber25/a25_fetch.v |
verilog work ../../vlog/amber25/a25_icache.v |
verilog work ../../vlog/amber25/a25_mem.v |
verilog work ../../vlog/amber25/a25_multiply.v |
verilog work ../../vlog/amber25/a25_register_bank.v |
verilog work ../../vlog/amber25/a25_wishbone.v |
verilog work ../../vlog/amber25/a25_write_back.v |
|
# Xilinx Virtex-6 FPGA Hardware wrappers |
verilog work ../../vlog/lib/xv6_addsub_n.v |
verilog work ../../vlog/lib/xv6_sram_2048x32_byte_en.v |
verilog work ../../vlog/lib/xv6_sram_256x128_byte_en.v |
verilog work ../../vlog/lib/xv6_sram_256x21_line_en.v |
verilog work ../../vlog/lib/xv6_sram_256x32_byte_en.v |
|
# Xilinx Virtex-6 DDR3 I/F |
verilog work ../../vlog/xv6_ddr3/ui_cmd.v |
verilog work ../../vlog/xv6_ddr3/phy_data_io.v |
verilog work ../../vlog/xv6_ddr3/phy_control_io.v |
verilog work ../../vlog/xv6_ddr3/round_robin_arb.v |
verilog work ../../vlog/xv6_ddr3/phy_write.v |
verilog work ../../vlog/xv6_ddr3/phy_pd_top.v |
verilog work ../../vlog/xv6_ddr3/ddr2_ddr3_chipscope.v |
verilog work ../../vlog/xv6_ddr3/phy_dq_iob.v |
verilog work ../../vlog/xv6_ddr3/phy_wrlvl.v |
verilog work ../../vlog/xv6_ddr3/bank_mach.v |
verilog work ../../vlog/xv6_ddr3/ecc_buf.v |
verilog work ../../vlog/xv6_ddr3/ui_rd_data.v |
verilog work ../../vlog/xv6_ddr3/infrastructure.v |
verilog work ../../vlog/xv6_ddr3/phy_dly_ctrl.v |
verilog work ../../vlog/xv6_ddr3/phy_dqs_iob.v |
verilog work ../../vlog/xv6_ddr3/rank_mach.v |
verilog work ../../vlog/xv6_ddr3/phy_dm_iob.v |
verilog work ../../vlog/xv6_ddr3/bank_queue.v |
verilog work ../../vlog/xv6_ddr3/phy_rdclk_gen.v |
verilog work ../../vlog/xv6_ddr3/mem_intfc.v |
verilog work ../../vlog/xv6_ddr3/bank_state.v |
verilog work ../../vlog/xv6_ddr3/arb_row_col.v |
verilog work ../../vlog/xv6_ddr3/iodelay_ctrl.v |
verilog work ../../vlog/xv6_ddr3/rd_bitslip.v |
verilog work ../../vlog/xv6_ddr3/phy_rdlvl.v |
verilog work ../../vlog/xv6_ddr3/memc_ui_top.v |
verilog work ../../vlog/xv6_ddr3/mc.v |
verilog work ../../vlog/xv6_ddr3/bank_compare.v |
verilog work ../../vlog/xv6_ddr3/phy_rdctrl_sync.v |
verilog work ../../vlog/xv6_ddr3/clk_ibuf.v |
verilog work ../../vlog/xv6_ddr3/xv6_ddr3.v |
verilog work ../../vlog/xv6_ddr3/phy_ck_iob.v |
verilog work ../../vlog/xv6_ddr3/bank_cntrl.v |
verilog work ../../vlog/xv6_ddr3/phy_ocb_mon.v |
verilog work ../../vlog/xv6_ddr3/ui_top.v |
verilog work ../../vlog/xv6_ddr3/ecc_gen.v |
verilog work ../../vlog/xv6_ddr3/arb_select.v |
verilog work ../../vlog/xv6_ddr3/col_mach.v |
verilog work ../../vlog/xv6_ddr3/phy_pd.v |
verilog work ../../vlog/xv6_ddr3/rank_cntrl.v |
verilog work ../../vlog/xv6_ddr3/phy_top.v |
verilog work ../../vlog/xv6_ddr3/phy_clock_io.v |
verilog work ../../vlog/xv6_ddr3/circ_buffer.v |
verilog work ../../vlog/xv6_ddr3/phy_init.v |
verilog work ../../vlog/xv6_ddr3/ecc_dec_fix.v |
verilog work ../../vlog/xv6_ddr3/arb_mux.v |
verilog work ../../vlog/xv6_ddr3/ui_wr_data.v |
verilog work ../../vlog/xv6_ddr3/phy_read.v |
verilog work ../../vlog/xv6_ddr3/bank_common.v |
verilog work ../../vlog/xv6_ddr3/phy_ocb_mon_top.v |
verilog work ../../vlog/xv6_ddr3/phy_rddata_sync.v |
verilog work ../../vlog/xv6_ddr3/ecc_merge_enc.v |
verilog work ../../vlog/xv6_ddr3/rank_common.v |
/trunk/hw/fpga/bin/xs6_source_files.prj
0,0 → 1,124
# ---------------------------------------------------------------- |
# // |
# Xilinx Spartan-6 FPGA synthesis Verilog source file list // |
# // |
# This file is part of the Amber project // |
# http://www.opencores.org/project,amber // |
# // |
# Description // |
# // |
# Author(s): // |
# - Conor Santifort, csantifort.amber@gmail.com // |
# // |
#/ /////////////////////////////////////////////////////////////// |
# // |
# Copyright (C) 2010 Authors and OPENCORES.ORG // |
# // |
# This source file may be used and distributed without // |
# restriction provided that this copyright statement is not // |
# removed from the file and that any derivative work contains // |
# the original copyright notice and the associated disclaimer. // |
# // |
# This source file is free software; you can redistribute it // |
# and/or modify it under the terms of the GNU Lesser General // |
# Public License as published by the Free Software Foundation; // |
# either version 2.1 of the License, or (at your option) any // |
# later version. // |
# // |
# This source is distributed in the hope that it will be // |
# useful, but WITHOUT ANY WARRANTY; without even the implied // |
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // |
# PURPOSE. See the GNU Lesser General Public License for more // |
# details. // |
# // |
# You should have received a copy of the GNU Lesser General // |
# Public License along with this source; if not, download it // |
# from http://www.opencores.org/lgpl.shtml // |
# // |
# ---------------------------------------------------------------- |
|
# System |
verilog work ../../vlog/system/boot_mem.v |
verilog work ../../vlog/system/clocks_resets.v |
verilog work ../../vlog/system/interrupt_controller.v |
verilog work ../../vlog/system/system.v |
verilog work ../../vlog/system/test_module.v |
verilog work ../../vlog/system/timer_module.v |
verilog work ../../vlog/system/uart.v |
verilog work ../../vlog/system/wb_xs6_ddr3_bridge.v |
verilog work ../../vlog/system/wb_xv6_ddr3_bridge.v |
verilog work ../../vlog/system/wishbone_arbiter.v |
verilog work ../../vlog/system/afifo.v |
verilog work ../../vlog/system/ddr3_afifo.v |
|
# EthMac |
verilog work ../../vlog/ethmac/eth_clockgen.v |
verilog work ../../vlog/ethmac/eth_crc.v |
verilog work ../../vlog/ethmac/eth_fifo.v |
verilog work ../../vlog/ethmac/eth_maccontrol.v |
verilog work ../../vlog/ethmac/eth_macstatus.v |
verilog work ../../vlog/ethmac/eth_miim.v |
verilog work ../../vlog/ethmac/eth_outputcontrol.v |
verilog work ../../vlog/ethmac/eth_random.v |
verilog work ../../vlog/ethmac/eth_receivecontrol.v |
verilog work ../../vlog/ethmac/eth_registers.v |
verilog work ../../vlog/ethmac/eth_register.v |
verilog work ../../vlog/ethmac/eth_rxaddrcheck.v |
verilog work ../../vlog/ethmac/eth_rxcounters.v |
verilog work ../../vlog/ethmac/eth_rxethmac.v |
verilog work ../../vlog/ethmac/eth_rxstatem.v |
verilog work ../../vlog/ethmac/eth_shiftreg.v |
verilog work ../../vlog/ethmac/eth_spram_256x32.v |
verilog work ../../vlog/ethmac/eth_top.v |
verilog work ../../vlog/ethmac/eth_transmitcontrol.v |
verilog work ../../vlog/ethmac/eth_txcounters.v |
verilog work ../../vlog/ethmac/eth_txethmac.v |
verilog work ../../vlog/ethmac/eth_txstatem.v |
verilog work ../../vlog/ethmac/eth_wishbone.v |
verilog work ../../vlog/ethmac/xilinx_dist_ram_16x32.v |
|
# Amber 23 |
verilog work ../../vlog/amber23/a23_alu.v |
verilog work ../../vlog/amber23/a23_barrel_shift.v |
verilog work ../../vlog/amber23/a23_cache.v |
verilog work ../../vlog/amber23/a23_coprocessor.v |
verilog work ../../vlog/amber23/a23_core.v |
verilog work ../../vlog/amber23/a23_decode.v |
verilog work ../../vlog/amber23/a23_execute.v |
verilog work ../../vlog/amber23/a23_fetch.v |
verilog work ../../vlog/amber23/a23_multiply.v |
verilog work ../../vlog/amber23/a23_register_bank.v |
verilog work ../../vlog/amber23/a23_wishbone.v |
|
# Amber 25 |
verilog work ../../vlog/amber25/a25_alu.v |
verilog work ../../vlog/amber25/a25_barrel_shift.v |
verilog work ../../vlog/amber25/a25_coprocessor.v |
verilog work ../../vlog/amber25/a25_core.v |
verilog work ../../vlog/amber25/a25_dcache.v |
verilog work ../../vlog/amber25/a25_decode.v |
verilog work ../../vlog/amber25/a25_execute.v |
verilog work ../../vlog/amber25/a25_fetch.v |
verilog work ../../vlog/amber25/a25_icache.v |
verilog work ../../vlog/amber25/a25_mem.v |
verilog work ../../vlog/amber25/a25_multiply.v |
verilog work ../../vlog/amber25/a25_register_bank.v |
verilog work ../../vlog/amber25/a25_wishbone.v |
verilog work ../../vlog/amber25/a25_write_back.v |
|
# Xilinx Spartan-6 FPGA Hardware wrappers |
verilog work ../../vlog/lib/xs6_addsub_n.v |
verilog work ../../vlog/lib/xs6_sram_2048x32_byte_en.v |
verilog work ../../vlog/lib/xs6_sram_256x128_byte_en.v |
verilog work ../../vlog/lib/xs6_sram_256x21_line_en.v |
verilog work ../../vlog/lib/xs6_sram_256x32_byte_en.v |
|
# Xilinx Spartan-6 DDR3 I/F |
verilog work ../../vlog/xs6_ddr3/mcb_ddr3.v |
verilog work ../../vlog/xs6_ddr3/iodrp_controller.v |
verilog work ../../vlog/xs6_ddr3/iodrp_mcb_controller.v |
verilog work ../../vlog/xs6_ddr3/mcb_raw_wrapper.v |
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration_top.v |
verilog work ../../vlog/xs6_ddr3/mcb_soft_calibration.v |
verilog work ../../vlog/xs6_ddr3/memc3_infrastructure.v |
verilog work ../../vlog/xs6_ddr3/memc3_wrapper.v |
/trunk/hw/fpga/bin/Makefile
60,8 → 60,6
# Name of top level verilog file (must be the same as its module name) |
RTL_TOP = system |
|
# List of verilog source files |
XST_PROJ_FILE = source_files.prj |
|
|
# ---------------------------------------------------- |
90,6 → 88,8
XST_DEFINES = XILINX_FPGA XILINX_VIRTEX6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=12 |
# Xilinx placement and timing constraints |
XST_CONST_FILE = xv6_constraints.ucf |
# List of verilog source files for Xilinx Virtex-6 device |
XST_PROJ_FILE = xv6_source_files.prj |
else |
# The spartan6 device used on SP605 Development board |
XILINX_FPGA = xc6slx45tfgg484-3 |
96,6 → 96,8
XST_DEFINES = XILINX_FPGA XILINX_SPARTAN6_FPGA $(AMBER_CORE) AMBER_CLK_DIVIDER=20 |
# Xilinx placement and timing constraints |
XST_CONST_FILE = xs6_constraints.ucf |
# List of verilog source files for Xilinx Spartan-6 device |
XST_PROJ_FILE = xs6_source_files.prj |
endif |
|
|