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    from Rev 138 to Rev 137
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Rev 138 → Rev 137

/trunk/rtl/verilog/can_top.v
17,7 → 17,7
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// Copyright (C) 2002, 2003 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
50,9 → 50,6
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.46 2003/10/17 05:55:20 markom
// mbist signals updated according to newest convention
//
// Revision 1.45 2003/09/30 00:55:13 mohor
// Error counters fixed to be compatible with Bosch VHDL reference model.
// Small synchronization changes.
231,7 → 228,7
clk_i,
rx_i,
tx_o,
bus_off_on,
tx_oen_o,
irq_on,
clkout_o
 
286,7 → 283,7
input clk_i;
input rx_i;
output tx_o;
output bus_off_on;
output tx_oen_o;
output irq_on;
output clkout_o;
 
429,6 → 426,8
wire go_tx;
wire send_ack;
 
 
 
wire rst;
wire we;
wire [7:0] addr;
720,7 → 719,7
/* Tx signal */
.tx(tx_o),
.tx_next(tx_next),
.bus_off_on(bus_off_on),
.tx_oen(tx_oen_o),
 
.go_overload_frame(go_overload_frame),
.go_error_frame(go_error_frame),
833,7 → 832,7
`else
 
// Latching address
always @ (posedge clk_i or posedge rst)
always @ (negedge clk_i or posedge rst)
begin
if (rst)
addr_latched <= 8'h0;

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