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  • This comparison shows the changes necessary to convert path
    /claw/trunk/or1200_cpu/work/or1200_ic_tag
    from Rev 2 to Rev 4
    Reverse comparison

Rev 2 → Rev 4

/_primary.vhd
0,0 → 1,18
library verilog;
use verilog.vl_types.all;
entity or1200_ic_tag is
generic(
dw : integer := 21;
aw : integer := 8
);
port(
clk : in vl_logic;
rst : in vl_logic;
addr : in vl_logic_vector;
en : in vl_logic;
we : in vl_logic;
datain : in vl_logic_vector;
tag_v : out vl_logic;
tag : out vl_logic_vector
);
end or1200_ic_tag;
_primary.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: verilog.asm =================================================================== --- verilog.asm (nonexistent) +++ verilog.asm (revision 4) @@ -0,0 +1,214 @@ +4A7 +џџk41 Tќ +џџ  +џџЙ +џџ”ц +џџ<§џ§џ0§џ` +џџџџ +§џp§џ0§џˆ +џџџџ  +§џ˜§џИ +џџГџџP +3У 0П0К4 + +џџќџџ§џ + +џџџџ + +џџќџџ §џ  + +џџџџ +   +џџ  + §џ0 +џџ8 +џџ + +§џ0 +џџ +џџ8 џџ +  +џџ +џџ2  +џџ +џџ2 +  +џџ   + +џџ +  +џџ  + +џџT +џџ +џџ2 +џџ§џ8§џ0 +џџT  +џџ, + + + + +џџ џџ  +  +џџ§џ@§џ0 +џџK +џџD +џџќџџ §џP +џџ +џџџџ$ + +џџќџџ(§џh + +џџџџ, + +џџќџџ0 §џ€ + +џџџџ4 +  +џџ +§џ0 +џџ8џџH +§џ0 +џџH +џџ8џџL + +џџL +џџ2 +џџH +џџ2  +џџ  +џџH +  +џџ + +џџT +џџH +џџ2 +џџH§џ8§џ0 +џџT   +џџL, +  + + +џџ џџ`  + +џџL§џ@§џ0 +џџK +џџŒ +џџќ!џџ8!§џ  +!џџ` +џџ"џџ< +" +џџќ#џџ@# §џР +# +џџ$џџD +$ +џџL +џџ2% +џџH +џџ2& ' +џџ & +џџH +' ( +џџ +( +џџT +џџH +џџ2)) +џџH§џи§џ0 +џџT% * +џџL, +* +& +) +џџ џџ   +% +џџL§џ@§џ0 +џџK +џџЬ +џџќ+џџH+ +§џш ++џџ  +џџ,џџL +,3Є +џџ|§џ +џџ§џа +џџj§џ +џџ§џа +џџj§џ0 +џџ$џџ +џџj§џH +џџ,§џа +џџj§џ` +џџ4§џа +џџj§џx +џџ<џџ` +џџj§џ +џџD§џа +џџj§џЈ +џџLџџ  +џџjџџџџ +џџ~џџа§џРџџ  +џџN +џџH +џџZ-џџ˜ +- +џџH +џџZ.џџ” +. +џџL +џџZ/џџ +/ +џџH +џџZ0џџX +0 +џџH +џџZ1џџT +1 +џџL +џџZ2џџP +2 +џџ +џџZ3џџ +3 +џџ +џџZ4џџ +4 +џџ +џџZ5џџ  +5 +џџќ6џџ6§џ +6 +џџ7џџ +7 +џџ§џ8§џ +џџ)8 +8Ї +џџд +џџ§џ +џџ +џџ§џ +џџ +џџ,§џ' +џџ +џџ4§џ| +џџ +џџ§џ* +џџ +џџ$§џH +џџ +џџ<§џ- +џџ§џ0џџа +џџz +џџ@§џа +џџ{ +џџHџџ  +џџ{ +џџP§џИ +џџ9 7J    +9  7§џ3 +џџc +9979EEEEdwaEEмEEdE§џEEEE +EџџџџEEEEEEEEEEE EEEawaEEмEEeE§џhEEEEEEic_tEag0EтEEЋE§џEEEEEor12E00_sEpramE_256Ex21EE EEEEEEEEEEEEEclkEEEEnE§џEEEEErstEEEoE§џEEEEEEEEEEaddrEddrEEEE}E§џHEEEEEenrEEEE~E§џdEEEEEwerEEEEE§џ|EEEEEdataEinaEEEE€E§џ”EEEEEtag_Evg_EEEEE§џДEEEEEEEEtagEEEE‚E§џрEEEEEE#њEEWE§џEE’E#њEEWE§џEE’E#EEWE§џHEE’E#њEEWE§џdEE’E#њEEWE§џ|EE’E#EEWE§џ”EE’E#њEEWE§џДEE”E#EEWE§џрEE”E +EEEEEEEEEEEEE#impEliciEt-wiEre#0Ee#0EEEEЇE§џ№EEEEE#w#(E1)#1E671Ece1Eoe1Edi1Edo1Eor12E00_iEc_taEgtaZ333 14 { 31c 5de { {} { 2f0}}}x \ No newline at end of file
verilog.asm Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: _primary.dat =================================================================== --- _primary.dat (nonexistent) +++ _primary.dat (revision 4) @@ -0,0 +1,12 @@ +pЪjє~є— vŸiџДДо‰cшВчъЌh—_Шрыг,фLЇЅmгћ]@&9ИCkгar0ЕPILзУ64[*)эЖPf?|Ј˜Х7}шО„|лж† +ТMД‰ “шв8™цoКпЈW[ˆ‘ог@4Љкјž%ћ=6w~ЧЯњžљ/єdЏа•ГTp YЧтIю ЊP~’ˆ,сP“j7ў]ŠЊ>f +н >‰ + +>5 +{ Щ +†Z љєЯЃ8Зc Uєшщфа…­[NGŽ +Е/(^ rП–ќ}№ОЧЛљЗсS№ыь—Ья‹у$‹AЭиWš67ƒ +-Ь(™e1cPФE™З# ЯЃ: yWчoму‹‹W"6GƒŸ - (e1cPФE™ З# о +:OyЮч7Ь‰ ) AuЁХ З# ЈRDŒ6<у`|бж‘ж2ƒVQ­жV‚ЙtbЦїіўУЮбж7‚{tцЦџіюУюбнжЗ‚{tцЦџіюУюбнжЗ‚{tцЦџёўщџйэ’шsб’Ў +Idƒц5ЖzCЦбŒж‚?tnЦяіЮ УЎб]жЗ‚{tцЦџџ‘ю юfЭ +ЗЉРSћЋпCў‡БПЛRє/* \ No newline at end of file
_primary.dat Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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