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URL https://opencores.org/ocsvn/core1990_interlaken/core1990_interlaken/trunk

Subversion Repositories core1990_interlaken

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Rev 5 → Rev 6

/core1990_interlaken/trunk/gateware/constraints/Core1990_Constraints.xdc
0,0 → 1,43
###############################################################################
## This the constraints file for the Core1990 Interlaken project
##
## Family - virtex7
## Part - xc7vx485t
## Package - ffg1761
## Speed grade - -2
## Transceiver - X1Y2 (GTX)
##
###############################################################################
## Physical Constraints (geographical constraints)
###############################################################################
 
## Pin locations of the transceiver and system clock
set_property PACKAGE_PIN AH8 [get_ports GTREFCLK_IN_P]
set_property PACKAGE_PIN E19 [get_ports System_Clock_In_P]
set_property IOSTANDARD LVDS [get_ports System_Clock_In_P]
 
set_property PACKAGE_PIN AL6 [get_ports RX_In_P]
set_property PACKAGE_PIN AM4 [get_ports TX_Out_P]
 
## Pin locations and configuration of the status leds
set_property PACKAGE_PIN AM39 [get_ports Valid_out]
set_property IOSTANDARD LVCMOS18 [get_ports Valid_out]
 
###############################################################################
## Timing constraints
###############################################################################
 
## Clocks and their speed
create_clock -period 8.000 -name tc_GTREFCLK_IN_P [get_ports GTREFCLK_IN_P]
 
## Clock relations
set_max_delay -datapath_only -from [get_clocks clkout0] -to [get_clocks clk_out1_clk_40MHz*] 25.000
set_max_delay -datapath_only -from [get_clocks clk_out1_clk_40MHz*] -to [get_clocks clkout0] 25.000
 
###############################################################################
## Resets and False paths
###############################################################################
 
set_false_path -valid_path -from [get_ports Valid_out]
 
###############################################################################
/core1990_interlaken/trunk/gateware/scripts/implementation.tcl
0,0 → 1,86
set IMPL_RUN [get_runs impl*]
set SYNTH_RUN [get_runs synth*]
set PROJECT_NAME "pcie_dma_top_VC709"
set scriptdir [pwd]
set HDLDIR $scriptdir/../../
 
set_property part xc7vx690tffg1761-2 [current_project]
 
foreach design [get_designs] {
puts "Closing design: $design"
current_design $design
close_design
}
 
reset_run $SYNTH_RUN
 
set svn_hash [exec svn info]
set svn_hash_lines [split $svn_hash "\n"]
set svn_version "0"
cd $HDLDIR
foreach line $svn_hash_lines {
if [regexp {Last Changed Rev: } $line ] {
set svn_version [ lindex [split $line] 3 ]
}
}
cd $scriptdir
 
puts "SVN_VERSION = $svn_version"
 
 
set systemTime [clock seconds]
set build_date "40'h[clock format $systemTime -format %y%m%d%H%M]"
puts "BUILD_DATE = $build_date"
 
 
set_property is_enabled false [get_files $HDLDIR/constraints/pcie_dma_top_HTG710.xdc]
#set_property is_enabled false [get_files $HDLDIR/constraints/pcie_dma_top_kcu105.xdc]
set_property is_enabled true [get_files $HDLDIR/constraints/pcie_dma_top_VC709.xdc]
 
#set to true in order to generate the GBT links
set NUMBER_OF_INTERRUPTS 8
set NUMBER_OF_DESCRIPTORS 8
 
set CARD_TYPE 709
 
#compiled LM32 software
set g_dpram_initf ${HDLDIR}../../wrpc-sw/wrc.bram
 
 
set_property generic "\
BUILD_DATETIME=$build_date \
SVN_VERSION=$svn_version \
NUMBER_OF_INTERRUPTS=$NUMBER_OF_INTERRUPTS \
NUMBER_OF_DESCRIPTORS=$NUMBER_OF_DESCRIPTORS \
CARD_TYPE=$CARD_TYPE \
g_dpram_initf=$g_dpram_initf \
" [get_filesets {sim_1 sources_1}]
set_property strategy Performance_ExplorePostRoutePhysOpt $IMPL_RUN
launch_runs $SYNTH_RUN
#return
launch_runs $IMPL_RUN
#launch_runs $IMPL_RUN -to_step write_bitstream
#cd $HDLDIR/Synt/
wait_on_run $IMPL_RUN
set TIMESTAMP [clock format $systemTime -format {%y%m%d_%H_%M}]
 
 
 
open_run $IMPL_RUN
current_run $IMPL_RUN
 
write_bitstream $HDLDIR/output/${PROJECT_NAME}_${TIMESTAMP}.bit -force
 
cd $HDLDIR/output/
 
 
set BitFile ${PROJECT_NAME}_$TIMESTAMP.bit
set IMPL_DIR [get_property DIRECTORY [current_run]]
 
write_cfgmem -force -format MCS -size 128 -interface BPIx16 -loadbit "up 0x00000000 $BitFile" ${PROJECT_NAME}_$TIMESTAMP.mcs
if {[file exists $IMPL_DIR/debug_nets.ltx] == 1} {
file copy $IMPL_DIR/debug_nets.ltx ${PROJECT_NAME}_debug_nets_$TIMESTAMP.ltx
}
 
 
cd $scriptdir
/core1990_interlaken/trunk/gateware/simulation/Core1990_Test_tb.vhd
0,0 → 1,67
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_Interface_Test is
end entity testbench_Interface_Test;
 
architecture tb_interlaken_interface of testbench_Interface_Test is
constant TX_REFCLK_PERIOD : time := 8.0 ns;
constant RX_REFCLK_PERIOD : time := 8.0 ns;
constant SYSCLK_PERIOD : time := 25.0 ns;
constant DCLK_PERIOD : time := 5.0 ns;
 
signal System_Clock_In_P : std_logic;
signal System_Clock_In_N : std_logic;
signal GTREFCLK_IN_P : std_logic;
signal GTREFCLK_IN_N : std_logic;
 
signal TX_Out_P : std_logic;
signal TX_Out_N : std_logic;
signal RX_In_P : std_logic;
signal RX_In_N : std_logic;
signal valid_out : std_logic;
begin
RX_In_N <= TX_Out_N;
RX_In_P <= TX_Out_P;
uut : entity work.Interface_Test
port map (
System_Clock_In_P => System_Clock_In_P,
System_Clock_In_N => System_Clock_In_N,
GTREFCLK_IN_P => GTREFCLK_IN_P,
GTREFCLK_IN_N => GTREFCLK_IN_N,
RX_In_N => RX_In_N,
RX_In_P => RX_In_P,
TX_Out_N => TX_Out_N,
TX_Out_P => TX_Out_P,
valid_out => valid_out
);
process
begin
GTREFCLK_IN_N <= '1';
wait for TX_REFCLK_PERIOD/2;
GTREFCLK_IN_N <= '0';
wait for TX_REFCLK_PERIOD/2;
end process;
 
GTREFCLK_IN_P <= not GTREFCLK_IN_N;
 
process
begin
System_Clock_In_N <= '1';
wait for DCLK_PERIOD/2;
System_Clock_In_N <= '0';
wait for DCLK_PERIOD/2;
end process;
System_Clock_In_P <= not System_Clock_In_N;
 
end architecture tb_interlaken_interface;
/core1990_interlaken/trunk/gateware/simulation/crc-32_tb.vhd
0,0 → 1,80
library ieee;
use ieee.std_logic_1164.all;
 
entity testbenchcrc_32 is
end entity testbenchcrc_32;
 
architecture tb_CRC_32 of testbenchcrc_32 is
 
 
--for uut : CRC use entity work.CRC(error_check);
constant Nbits : positive := 64;
constant CRC_Width : positive := 32;
constant G_Poly: Std_Logic_Vector :=x"1EDC_6F41"; --c1acf
constant G_InitVal: std_logic_vector:=x"ffff_ffff";
 
signal CRC : std_logic_vector(CRC_Width-1 downto 0);
signal Calc : std_logic := '0';
signal Clk : std_logic := '1';
signal Reset: std_logic := '1';
signal Din : std_logic_vector(Nbits-1 downto 0);
 
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.CRC_32
generic map(
Nbits => Nbits,
CRC_Width => CRC_Width,
G_Poly => G_Poly,
G_InitVal => G_InitVal
)
port map (
CRC => CRC,
Calc => Calc,
Reset => Reset,
Clk => Clk,
Din => Din
);
 
Clk_process :process
begin
Clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
Clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
Din <= (others=>'0');
wait for CLK_PERIOD*2;
Reset <= '0';
Calc <= '1';
Din <= X"5f5e5d5c5b5a5958";
--wait for CLK_PERIOD;
--Din <= X"5f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Din <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Din <= X"9f5e5d5c5b5a5958";
wait for CLK_PERIOD;
--Calc <= '0';
Reset <= '1';
--Din <= (others=>'0');
wait for CLK_PERIOD;
Reset <='0';
--Calc <= '1';
wait for CLK_PERIOD;
Din <= X"aaa5555555554000";
wait for CLK_PERIOD;
Din <= X"d721a28c5b5c5959";
wait for CLK_PERIOD;
Din <= X"60b35d5dc4a582a7";
wait;
end process;
end architecture tb_CRC_32;
 
/core1990_interlaken/trunk/gateware/simulation/decoder_tb.vhd
0,0 → 1,185
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_decoder is
end entity testbench_decoder;
 
architecture tb_decoder of testbench_decoder is
 
signal Clk : std_logic; -- Clock input
signal Reset : std_logic; -- Reset decoder
signal Data_In : std_logic_vector(66 downto 0); -- Data input
signal Decoder_En : std_logic; -- Enables the decoder
signal Data_Valid_In : std_logic;
signal Data_Valid_Out : std_logic;
signal Data_Out : std_logic_vector(63 downto 0);-- Decoded 64-bit output
signal Data_Control : std_logic; -- Indicates whether the word is data or control
signal Sync_Locked : std_logic;
signal Sync_Error : std_logic;
signal Bitslip : std_logic;
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.decoder
port map (
clk => clk,
reset => reset,
Decoder_En => Decoder_En,
Data_in => Data_in,
Data_out => Data_out,
Data_Valid_In => Data_Valid_In,
Data_Valid_Out => Data_Valid_Out,
Data_control => Data_control,
Sync_Locked => Sync_locked,
Sync_error => Sync_error,
Bitslip => Bitslip
 
);
 
Clk_process :process
begin
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
decoder_en <= '1';
reset <= '1';
data_in <= (others=>'0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
reset <= '0';
Data_in <= "101" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= "101" & X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= "101" & X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
data_in <= "101" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= "101" & X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
data_in <= "110" & X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= "101" & X"9486576758050505";
wait for CLK_PERIOD;
data_in <= "101" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
data_in <= "111" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= "101" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= "101" & X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= "101" & X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
data_in <= "101" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= "101" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= "101" & X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= "110" & X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= "101" & X"9486576758050505";
wait for CLK_PERIOD;
data_in <= "101" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD*60;
data_in <= "110" & X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= "101" & X"9486576758050505";
wait for CLK_PERIOD;
data_in <= "101" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
data_in <= "111" & X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= "101" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD*26;
data_in <= "111" & X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD*18;
data_in <= "101" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait;
end process;
end architecture tb_decoder;
 
/core1990_interlaken/trunk/gateware/simulation/deframing_burst_tb.vhd
0,0 → 1,261
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_deburster is
end entity testbench_deburster;
 
architecture tb_deburster of testbench_deburster is
 
signal Clk : std_logic; -- Clock input
signal Reset : std_logic; -- Reset decoder
signal Data_In : std_logic_vector(63 downto 0); -- Data input
signal Deburst_En : std_logic; -- Enables the decoder
signal Data_Out : std_logic_vector(65 downto 0); -- Decoded 64-bit output
signal Data_Control_In : std_logic; -- Indicates whether the word is data or control
signal Data_Control_Out : std_logic; -- Indicates whether the word is data or control
signal CRC24_Error : std_logic;
signal Data_Valid_In : std_logic;
signal Data_Valid_Out : std_logic;
signal FIFO_Full : std_logic;
signal FIFO_Data : std_logic_vector(4 downto 0);
signal FIFO_Write : std_logic;
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.Burst_Deframer
port map (
clk => clk,
reset => reset,
Deburst_En => Deburst_En,
Data_in => Data_in,
Data_out => Data_out,
Data_control_in => Data_control_in,
Data_control_out => Data_control_out,
CRC24_Error => CRC24_Error,
FIFO_Full => FIFO_Full,
FIFO_Data => FIFO_Data,
FIFO_Write => FIFO_Write,
Data_valid_in => Data_valid_in,
Data_valid_out => Data_valid_out
);
 
Clk_process :process
begin
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
Data_control_in <= '0';
deburst_en <= '1';
reset <= '1';
data_in <= (others=>'0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
reset <= '0';
Data_control_in <= '1';
Data_in <= X"E000_0001_0000_0000";
wait for CLK_PERIOD;
Data_control_in <= '0';
Data_in <= X"2800_0000_0000_0000";
wait for CLK_PERIOD;
data_in <= X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
Data_control_in <= '1';
data_in <= X"9000_0001_dd52_35a7";
wait for CLK_PERIOD;
Data_control_in <= '0';
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
Data_Control_In <= '1';
data_in <= X"E000_0001_0000_0000";
wait for CLK_PERIOD*3;
Data_Control_In <= '0';
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
Data_control_in <= '1';
data_in <= X"9000_0001_dd52_35a7";
wait for CLK_PERIOD;
Data_control_in <= '0';
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*5;
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD*3;
Data_Control_In <= '1';
Data_in <= X"6400_0000_6222_431a";
wait for clk_period;
Data_control_in <= '1';
Data_in <= X"78f6_78f6_78f6_78f6";
wait for CLK_PERIOD;
Data_in <= X"2800_0000_0000_0000";
wait for CLK_PERIOD;
data_in <= X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
Data_control_in <= '0';
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
Data_control_in <= '1';
Data_in <= X"E000_0001_0000_0000";
wait for CLK_PERIOD;
Data_control_in <= '0';
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
 
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_control_in <= '1';
data_in <= X"C000_0001_0000_0000";
wait for CLK_PERIOD;
Data_control_in <= '0';
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"78f6_78f6_78f6_78f6";
wait for CLK_PERIOD;
Data_control_in <= '1';
data_in <= X"9000_0001_dd52_35a7";
wait for CLK_PERIOD;
Data_control_in <= '0';
Data_in <= X"2800_0000_0000_0000";
wait for CLK_PERIOD;
data_in <= X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
Data_Control_In <= '1';
data_in <= X"645e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"78f6_78f6_78f6_78f6";
wait for CLK_PERIOD;
Data_in <= X"2800_0000_0000_0000";
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD*60;
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
data_in <= X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD*26;
data_in <= X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD*18;
data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait;
end process;
end architecture tb_deburster;
 
/core1990_interlaken/trunk/gateware/simulation/deframing_meta_tb.vhd
0,0 → 1,230
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_deframer is
end entity testbench_deframer;
 
architecture tb_deframer of testbench_deframer is
 
signal Clk : std_logic; -- Clock input
signal Reset : std_logic; -- Reset decoder
signal Data_In : std_logic_vector(63 downto 0); -- Data input
signal Deframer_En : std_logic; -- Enables the decoder
signal Data_Out : std_logic_vector(63 downto 0); -- Decoded 64-bit output
signal Data_Control_In : std_logic; -- Indicates whether the word is data or control
signal Data_Control_Out : std_logic; -- Indicates whether the word is data or control
signal Data_Valid_Out : std_logic;
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.Meta_Deframer
port map (
clk => clk,
reset => reset,
Deframer_En => Deframer_En,
Data_in => Data_in,
Data_out => Data_out,
Data_control_in => Data_control_in,
Data_control_out => Data_control_out,
Data_valid_out => Data_valid_out
);
 
Clk_process :process
begin
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
Data_control_in <= '0';
deframer_en <= '1';
reset <= '1';
data_in <= (others=>'0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
reset <= '0';
Data_control_in <= '1';
Data_in <= X"78f6_78f6_78f6_78f6";
wait for CLK_PERIOD;
Data_in <= X"2800_0000_0000_0000";
wait for CLK_PERIOD;
data_in <= X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
Data_control_in <= '0';
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
Data_Control_In <= '1';
data_in <= X"E000_0001_0000_0000";
wait for CLK_PERIOD*3;
Data_Control_In <= '0';
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*5;
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD*3;
Data_Control_In <= '1';
Data_in <= X"6400_0000_6222_431a";
wait for clk_period;
Data_control_in <= '1';
Data_in <= X"78f6_78f6_78f6_78f6";
wait for CLK_PERIOD;
Data_in <= X"2800_0000_0000_0000";
wait for CLK_PERIOD;
data_in <= X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
Data_control_in <= '0';
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
 
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"78f6_78f6_78f6_78f6";
wait for CLK_PERIOD;
Data_in <= X"2800_0000_0000_0000";
wait for CLK_PERIOD;
data_in <= X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
Data_Control_In <= '1';
data_in <= X"645e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"78f6_78f6_78f6_78f6";
wait for CLK_PERIOD;
Data_in <= X"2800_0000_0000_0000";
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD*60;
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
data_in <= X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD*26;
data_in <= X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD*18;
data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait;
end process;
end architecture tb_deframer;
 
/core1990_interlaken/trunk/gateware/simulation/descrambler_tb.vhd
0,0 → 1,217
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_descrambler is
end entity testbench_descrambler;
 
architecture tb_descrambler of testbench_descrambler is
 
signal Clk : std_logic; -- Clock input
signal Reset : std_logic; -- Reset decoder
signal Data_In : std_logic_vector(63 downto 0); -- Data input
signal Data_Out : std_logic_vector(63 downto 0); -- Decoded 64-bit output
signal Data_Control_In : std_logic; -- Indicates whether the word is data or control
signal Data_Control_Out : std_logic; -- Indicates whether the word is data or control
signal Lane_Number : std_logic_vector (3 downto 0);
signal Error_BadSync : std_logic;
signal Error_StateMismatch : std_logic;
signal Error_NoSync : std_logic;
signal Data_Valid_Out : std_logic;
 
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.Descrambler
port map (
clk => clk,
reset => reset,
Data_in => Data_in,
Data_out => Data_out,
Data_control_In => Data_control_In,
Data_control_Out => Data_control_Out,
Data_valid_out => Data_valid_out,
Lane_Number => Lane_Number,
Error_BadSync => Error_BadSync,
Error_StateMismatch => Error_StateMismatch,
Error_NoSync => Error_NoSync
);
 
Clk_process :process
begin
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
Data_Control_In <= '0';
reset <= '1';
Lane_Number <= "0001";
data_in <= (others=>'0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
reset <= '0';
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_Control_In <= '1';
Data_in <= X"78f6_78f6_78f6_78f6"; --1
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD*23;
Data_Control_In <= '1';
Data_in <= X"78f6_78f6_78f6_78f6";--2
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD*23;
Data_Control_In <= '1';
data_in <= X"78f6_78f6_78f6_78f6";--3
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*23;
Data_Control_In <= '1';
data_in <= X"78f6_78f6_78f6_78f6";--4 -> lock
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*21;
Data_Control_In <= '1';
data_in <= X"78f6_78f6_78f6_78f6"; --Sync &
wait for CLK_PERIOD;
Data_In <= X"2Bfe_d100_19e0_1dbd";
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_Control_In <= '1';
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"9486576758050505";
wait for CLK_PERIOD*19;
wait for CLK_PERIOD;
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD*60;
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
data_in <= X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD*26;
data_in <= X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD*18;
data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait;
end process;
end architecture tb_descrambler;
 
/core1990_interlaken/trunk/gateware/simulation/encoder_tb.vhd
0,0 → 1,110
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_encoder is
end entity testbench_encoder;
 
architecture tb_encoder of testbench_encoder is
component Encoder is
port (
data_in : in std_logic_vector(63 downto 0);
encoder_en : in std_logic;
Data_Control : in std_logic;
clk : in std_logic;
rst : in std_logic;
encoder_rst : in std_logic;
offset : out std_logic_vector(7 downto 0);
data_out : out std_logic_vector(66 downto 0)
);
end component Encoder;
 
for uut : line_encoder use entity work.line_encoder(encoder);
 
signal data_in : std_logic_vector(63 downto 0);
signal encoder_en : std_logic := '0';
signal Data_Control : std_logic := '0';
signal clk : std_logic;
signal rst : std_logic := '0';
signal encoder_rst : std_logic;
signal offset : std_logic_vector(7 downto 0);
signal data_out : std_logic_vector(66 downto 0);
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : Encoder
port map (
data_in => data_in,
encoder_en => encoder_en,
Data_Control => Data_Control,
clk => clk,
rst => rst,
encoder_rst => encoder_rst,
offset => offset,
data_out => data_out
);
 
Clk_process :process
begin
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
encoder_rst <= '1';
data_in <= (others=>'0');
wait for CLK_PERIOD;
 
wait for CLK_PERIOD;
encoder_rst <= '0';
encoder_en <= '1';
data_in <= X"5f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"9f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"bf21a2a3a4a5a6a7";
encoder_rst <= '1';
wait for CLK_PERIOD;
encoder_rst <= '0';
wait for CLK_PERIOD;
data_in <= X"2f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"00000FFF000000F0";
wait for CLK_PERIOD*3;
data_in <= X"5050505050050505";
wait for CLK_PERIOD;
 
data_in <= X"5486576758050505";
wait for CLK_PERIOD;
Data_Control <= '1';
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait;
end process;
end architecture tb_line_encoder;
 
/core1990_interlaken/trunk/gateware/simulation/framing_burst_tb.vhd
0,0 → 1,160
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_burst is
end entity testbench_burst;
 
architecture tb_burst of testbench_burst is
 
 
--for uut : CRC use entity work.CRC(error_check);
constant BurstMax : positive := 64; --256
constant BurstShort : positive := 32; --512 - 256 - 128 - 64 - 32
 
signal clk : std_logic; -- System clock
signal reset : std_logic; -- Reset, use for initialization.
 
signal TX_Enable : std_logic := '0'; -- Enable the TX
signal TX_SOP : std_logic := '0'; -- Start of Packet
signal TX_ValidBytes : std_logic_vector(2 downto 0) := "000"; -- Valid bytes packet contains
signal TX_EOP : std_logic := '0'; -- End of Packet
signal TX_FlowControl : std_logic_vector(15 downto 0) := (others => '0'); -- Flow control data (yet unutilized)
signal TX_Channel : std_logic_vector(7 downto 0);
 
signal Data_in : std_logic_vector(63 downto 0); -- Input data
signal Data_out : std_logic_vector(63 downto 0); -- To scrambling/framing
signal Data_valid_out : std_logic; -- Indicate data transmitted is valid
signal Data_control_out : std_logic; -- Control word indication
 
--signal CRC24_TX : std_logic_vector(63 downto 0); -- Data to CRC-24
--signal CRC24_Cal : std_logic_vector(63 downto 0); -- Calculated CRC-24
--signal CRC24_En : std_logic; -- Indicate the CRC-24 the data is valid
 
signal FIFO_meta : std_logic;
signal FIFO_read : std_logic; -- Request data from the FIFO
signal FIFO_data : std_logic_vector(9 downto 0); -- Determines how many bytes have to be transmitted
 
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.burst
generic map(
BurstShort => BurstShort,
BurstMax => BurstMax
)
port map (
clk => clk,
reset => reset,
TX_Enable => TX_Enable,
TX_SOP => TX_SOP,
TX_ValidBytes => TX_ValidBytes,
TX_EOP => TX_EOP,
TX_FlowControl => TX_FlowControl,
TX_Channel => TX_Channel,
Data_in => Data_in,
Data_out => Data_out,
Data_valid_out => Data_valid_out,
Data_control_out => Data_control_out,
--CRC24_TX => CRC24_TX,
--CRC24_Cal => CRC24_Cal,
--CRC24_En => CRC24_En,
FIFO_read => FIFO_read,
FIFO_meta => FIFO_meta,
FIFO_data => FIFO_data
);
 
Clk_process :process
begin
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
TX_SOP <= '0';
reset <= '1';
data_in <= (others=>'0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
FIFO_meta <= '1';
reset <= '0';
TX_Enable <= '1';
TX_ValidBytes <= "111";
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_SOP <= '1';
TX_EOP <= '1';
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_SOP <= '1';
TX_EOP <= '0';
data_in <= X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_EOP <= '0';
--reset <= '1';
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
--reset <= '0';
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
--TX_EOP <= '1';
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
--TX_EOP <= '0';
--TX_SOP <= '1';
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
TX_SOP <= '1';
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '1';
wait for CLK_PERIOD;
TX_EOP <= '0';
--TX_SOP <= '0';
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
TX_EOP <= '1';
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
TX_EOP <= '0';
TX_SOP <= '1';
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*6;
FIFO_meta<= '0';
wait for CLK_PERIOD;
FIFO_meta<= '1';
wait for CLK_PERIOD*6;
TX_SOP <= '0';
TX_EOP <= '1';
wait for CLK_PERIOD;
FIFO_meta <= '0';
wait for CLK_PERIOD*4;
FIFO_meta <= '1';
wait;
end process;
end architecture tb_burst;
 
/core1990_interlaken/trunk/gateware/simulation/framing_meta_tb.vhd
0,0 → 1,150
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_meta is
end entity testbench_meta;
 
architecture tb_meta of testbench_meta is
 
signal clk : std_logic; -- System clock
signal reset : std_logic; -- Reset, use for initialization.
 
signal TX_Enable : std_logic;
signal HealthLane : std_logic := '0';
signal HealthInterface : std_logic := '0';
 
signal Data_in : std_logic_vector(63 downto 0); -- Input data
signal Data_out : std_logic_vector(63 downto 0); -- To scrambling/framing
signal Data_valid_in : std_logic; -- Indicate data transmitted is valid
signal Data_valid_out : std_logic; -- Indicate data transmitted is valid
signal Data_Control_In : std_logic;
signal Data_control_out : std_logic; -- Control word indication
 
signal Gearboxready : std_logic;
 
signal FIFO_read : std_logic; -- Request data from the FIFO
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.metaframing
port map (
clk => clk,
reset => reset,
TX_Enable => TX_Enable,
HealthLane => HealthLane,
HealthInterface => HealthInterface,
Data_in => Data_in,
Data_out => Data_out,
Data_valid_in => Data_valid_in,
Data_valid_out => Data_valid_out,
Data_control_in => Data_control_in,
Data_control_out => Data_control_out,
Gearboxready => Gearboxready,
FIFO_read => FIFO_read
);
 
Clk_process :process
begin
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
reset <= '1';
data_in <= (others=>'0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
Gearboxready <= '1';
reset <= '0';
TX_Enable <= '1';
Data_valid_in <= '1';
Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
 
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
 
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
 
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Gearboxready <= '0';
data_in <= X"8050505050050505";
wait for CLK_PERIOD*2;
Gearboxready <= '1';
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
 
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
 
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"8050505050050505";
wait for CLK_PERIOD*3;
data_in <= X"9486576758050505";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"8050505050050505";
wait;
end process;
end architecture tb_meta;
 
/core1990_interlaken/trunk/gateware/simulation/interlaken_interface_tb.vhd
0,0 → 1,261
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_interlaken_interface is
end entity testbench_interlaken_interface;
 
architecture tb_interlaken_interface of testbench_interlaken_interface is
constant TX_REFCLK_PERIOD : time := 8.0 ns;
constant RX_REFCLK_PERIOD : time := 8.0 ns;
constant SYSCLK_PERIOD : time := 25.0 ns;
constant DCLK_PERIOD : time := 5.0 ns;
-- constant BurstMax
-- constant BurstShort
-- constant PacketLength
signal System_Clock_In_P : std_logic;
signal System_Clock_In_N : std_logic;
signal GTREFCLK_IN_P : std_logic;
signal GTREFCLK_IN_N : std_logic;
 
signal Reset : std_logic;
signal TX_Data : std_logic_vector(63 downto 0); -- Data transmitted
signal RX_Data : std_logic_vector (63 downto 0); -- Data received
signal TX_Out_P : std_logic;
signal TX_Out_N : std_logic;
signal RX_In_P : std_logic;
signal RX_In_N : std_logic;
signal TX_Link_Up : std_logic; -- In case signal is high transmission may start
signal TX_SOP : std_logic;
signal TX_EOP : std_logic;
signal TX_EOP_Valid : std_logic_vector(2 downto 0);
signal TX_FlowControl : std_logic_vector(15 downto 0);
signal TX_Channel : std_logic_vector(7 downto 0);
signal RX_SOP : std_logic; -- Start of Packet
signal RX_EOP : std_logic; -- End of Packet
signal RX_EOP_Valid : std_logic_vector(2 downto 0); -- Valid bytes packet contains
signal RX_FlowControl : std_logic_vector(15 downto 0); -- Flow control data (yet unutilized)
signal RX_Channel : std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)
signal RX_Link_Up : std_logic;
signal TX_Overflow : std_logic;
signal TX_Underflow : std_logic;
signal RX_FIFO_Full : std_logic;
signal RX_FIFO_Empty : std_logic;
signal Decoder_lock : std_logic;
signal Descrambler_lock : std_logic;
signal CRC24_Error : std_logic;
signal CRC32_Error : std_logic;
begin
RX_In_N <= TX_Out_N;
RX_In_P <= TX_Out_P;
uut : entity work.interlaken_interface
port map (
System_Clock_In_P => System_Clock_In_P,
System_Clock_In_N => System_Clock_In_N,
GTREFCLK_IN_P => GTREFCLK_IN_P,
GTREFCLK_IN_N => GTREFCLK_IN_N,
reset => reset,
TX_Data => TX_Data,
RX_Data => RX_Data,
RX_In_N => RX_In_N,
RX_In_P => RX_In_P,
TX_Out_N => TX_Out_N,
TX_Out_P => TX_Out_P,
TX_Link_Up => TX_Link_Up,
TX_SOP => TX_SOP,
TX_EOP => TX_EOP,
TX_EOP_Valid => TX_EOP_Valid,
TX_FlowControl => TX_FlowControl,
TX_Channel => TX_Channel,
RX_SOP => RX_SOP,
RX_EOP => RX_EOP,
RX_EOP_Valid => RX_EOP_Valid,
RX_FlowControl => RX_FlowControl,
RX_Channel => RX_Channel,
RX_Link_Up => RX_Link_Up,
TX_Overflow => TX_Overflow,
TX_Underflow => TX_Underflow,
RX_FIFO_Full => RX_FIFO_Full,
RX_FIFO_Empty => RX_FIFO_Empty,
Decoder_lock => Decoder_lock,
Descrambler_lock => Descrambler_lock,
CRC24_Error => CRC24_Error,
CRC32_Error => CRC32_Error
);
process
begin
GTREFCLK_IN_N <= '1';
wait for TX_REFCLK_PERIOD/2;
GTREFCLK_IN_N <= '0';
wait for TX_REFCLK_PERIOD/2;
end process;
 
GTREFCLK_IN_P <= not GTREFCLK_IN_N;
process
begin
rx_refclk_n_r <= '1';
wait for RX_REFCLK_PERIOD/2;
rx_refclk_n_r <= '0';
wait for RX_REFCLK_PERIOD/2;
end process;
 
rx_refclk_p_r <= not rx_refclk_n_r;
process
begin
System_Clock_In_N <= '1';
wait for DCLK_PERIOD/2;
System_Clock_In_N <= '0';
wait for DCLK_PERIOD/2;
end process;
System_Clock_In_P <= not System_Clock_In_N;
 
simulation : process
begin
wait for 1 ps;
--TX_Enable <= '0';
TX_EOP <= '0';
TX_SOP <= '0';
TX_Channel <= X"01";
TX_EOP_Valid <= "111";
TX_Data <= (others=>'0');
reset <= '1';
TX_FlowControl <= (others => '0');
wait for 20*SYSCLK_PERIOD;
wait for SYSCLK_PERIOD;
reset <= '0';
--TX_SOP <= '1';
--TX_Enable <= '1';
TX_Data <= X"1f5e5d5c5b5a5958";
wait for SYSCLK_PERIOD;
--TX_EOP <= '1';
wait until (TX_Link_Up = '1');
wait for SYSCLK_PERIOD*10;
TX_FlowControl(0) <= '1';
TX_SOP <= '1';
TX_EOP <= '1';
TX_Data <= X"2f5e5d5c5b5a5958";
wait for SYSCLK_PERIOD;
TX_EOP <= '0';
TX_Data <= X"3f5e5d5c5b5a5958";
wait for SYSCLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '0';
TX_EOP <= '0';
--reset <= '1';
TX_Data <= X"4f21a2a3a4a5a6a7";
wait for SYSCLK_PERIOD;
-- TX_FlowControl(0) <= '1';
TX_SOP <= '1';
TX_Data <= X"5f5e5a5c5b60f2a0";
wait for SYSCLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '1';
TX_Data <= X"635e22a3a4a5a7a7";
wait for SYSCLK_PERIOD;
TX_EOP <= '0';
--TX_SOP <= '1';
TX_Data <= X"70000FFF000000F0";
wait for SYSCLK_PERIOD*2;
TX_SOP <= '1';
TX_Data <= X"2f5e5d5c5b5a5958";
wait for SYSCLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '1';
wait for SYSCLK_PERIOD;
TX_EOP <= '0';
--TX_SOP <= '0';
TX_Data <= X"8050505050050505";
--wait for SYSCLK_PERIOD*3;
wait for SYSCLK_PERIOD;
TX_Data <= X"9486576758050505";
wait for SYSCLK_PERIOD;
TX_EOP <= '1';
TX_Data <= X"60b35d5dc4a582a7";
wait for SYSCLK_PERIOD; --Test influencing pause state position
TX_EOP <= '0';
wait for SYSCLK_PERIOD*16;
TX_SOP <= '1';
TX_Data <= X"4f21a2a3a4a5a6a7";
wait for SYSCLK_PERIOD;
TX_Data <= X"995e5a5c5b60f2a0";
wait for SYSCLK_PERIOD;
TX_Data <= X"635e22a3a4a5a7a7";
wait for SYSCLK_PERIOD;
TX_Data <= X"70000FFF000000F0";
wait for SYSCLK_PERIOD*2;
TX_Data <= X"2f5e5d5c5b5a5958";
wait for SYSCLK_PERIOD;
TX_Data <= X"4f21a2a3a4a5a6a7";
wait for SYSCLK_PERIOD;
TX_Data <= X"5f5e5a5c5b60f2a0";
wait for SYSCLK_PERIOD;
TX_Data <= X"635e22a3a4a5a7a7";
wait for SYSCLK_PERIOD;
TX_Data <= X"70000FFF000000F0";
wait for SYSCLK_PERIOD*2;
TX_Data <= X"2f5e5d5c5b5a5958";
wait for SYSCLK_PERIOD*12;
TX_Data <= X"4f5e5d5c5b5a5958";
wait for SYSCLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '1';
wait for SYSCLK_PERIOD;
wait for SYSCLK_PERIOD*4;
wait;
end process;
 
end architecture tb_interlaken_interface;
 
 
/core1990_interlaken/trunk/gateware/simulation/interlaken_receiver_tb.vhd
0,0 → 1,386
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_interlaken_receiver is
end entity testbench_interlaken_receiver;
 
architecture tb_interlaken_receiver of testbench_interlaken_receiver is
 
signal write_clk : std_logic;
signal clk : std_logic;
signal reset : std_logic;
signal RX_Data_In : std_logic_vector(66 downto 0);
signal RX_Data_Out : std_logic_vector (63 downto 0); -- later 66 downto 0
signal RX_Enable : std_logic; -- Enable the TX
signal RX_SOP : std_logic; -- Start of Packet
signal RX_ValidBytes : std_logic_vector(2 downto 0); -- Valid bytes packet contains
signal RX_EOP : std_logic; -- End of Packet
signal RX_FlowControl : std_logic_vector(15 downto 0); -- Flow control data (yet unutilized)
signal RX_Channel : std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)
signal RX_Link_Up : std_logic;
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.interlaken_receiver
port map (
write_clk => write_clk,
clk => clk,
reset => reset,
RX_Data_In => RX_Data_In,
RX_Data_Out => RX_Data_Out,
RX_Enable => RX_Enable,
RX_SOP => RX_SOP,
RX_ValidBytes => RX_ValidBytes,
RX_EOP => RX_EOP,
RX_FlowControl => RX_FlowControl,
RX_Channel => RX_Channel,
RX_Link_Up => RX_Link_Up
);
 
Clk_process :process
begin
write_clk <= '1';
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
write_clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
RX_Data_In <= (others=>'0');
reset <= '1';
wait for CLK_PERIOD;
wait for CLK_PERIOD;
--FIFO_meta <= '1';
reset <= '0';
reset <= '0';
RX_Data_in <= "101" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"70000FFF000000F0";
wait for CLK_PERIOD*2;
RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait for CLK_PERIOD;
RX_Data_In <= "110" & X"8050505050050505";
wait for CLK_PERIOD*3;
RX_Data_In <= "101" & X"9486576758050505";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
RX_Data_In <= "111" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"70000FFF000000F0";
wait for CLK_PERIOD*21;
RX_Data_In <= "001" & X"78f6_78f6_78f6_78f6"; --Sync &
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"70000FFF000000F0";
wait for CLK_PERIOD*2;
RX_Data_In <= "001" & X"2Bfe_d100_19e0_1dbd";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"70000FFF000000F0";
wait for CLK_PERIOD*2;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD*10;
 
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"8050505050050505";
wait for CLK_PERIOD*3;
RX_Data_In <= "001" & X"9486576758050505";
wait for CLK_PERIOD;
 
RX_Data_In <= "101" & X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD*20;
RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD*10;
RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"70000FFF000000F0";
wait for CLK_PERIOD*6;
RX_Data_In <= "001" & X"8050505050050505";
wait for CLK_PERIOD*9;
RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "110" & X"8050505050050505";
wait for CLK_PERIOD*3;
RX_Data_In <= "101" & X"9486576758050505";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6"; --1
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD*23;
RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6";--2
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD*23;
RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6";--3
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"70000FFF000000F0";
wait for CLK_PERIOD*23;
RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6";--4 -> lock
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"70000FFF000000F0";
wait for CLK_PERIOD*21;
RX_Data_In <= "010" & X"78f6_78f6_78f6_78f6"; --Sync &
wait for CLK_PERIOD;
RX_Data_In <= "010" & X"2Bfe_d100_19e0_1dbd";
wait for CLK_PERIOD;
RX_Data_In <= "010" & X"1e1e_1e1e_1e1e_1e1e";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"70000FFF000000F0";
wait for CLK_PERIOD*2;
RX_Data_In <= "010" & X"E000_0001_0000_0000";
wait for CLK_PERIOD*3;
RX_Data_In <= "001" & X"9486576758050505";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*5;
RX_Data_In <= "001" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD*3;
RX_Data_In <= "010" & X"6400_0000_6222_431a";
wait for clk_period;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"9486576758050505";
wait for CLK_PERIOD*19;
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"8050505050050505";
wait for CLK_PERIOD*3;
RX_Data_In <= "001" & X"9486576758050505";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"70000FFF000000F0";
wait for CLK_PERIOD*2;
RX_Data_In <= "001" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"8050505050050505";
wait for CLK_PERIOD*3;
RX_Data_In <= "001" & X"9486576758050505";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD*60;
RX_Data_In <= "001" & X"8050505050050505";
wait for CLK_PERIOD*3;
RX_Data_In <= "001" & X"9486576758050505";
wait for CLK_PERIOD;
RX_Data_In <= "001" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD*60;
RX_Data_In <= "110" & X"8050505050050505";
wait for CLK_PERIOD*3;
RX_Data_In <= "101" & X"9486576758050505";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
RX_Data_In <= "111" & X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD;
RX_Data_In <= "101" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD*26;
RX_Data_In <= "111" & X"2c8e5d5c5b5a5958";
wait for CLK_PERIOD*18;
RX_Data_In <= "101" & X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait;
--FIFO_meta <= '0';
wait for CLK_PERIOD*4;
--FIFO_meta <= '1';
wait;
end process;
 
end architecture tb_interlaken_receiver;
 
 
/core1990_interlaken/trunk/gateware/simulation/interlaken_transmitter_tb.vhd
0,0 → 1,184
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_interlaken_transmitter is
end entity testbench_interlaken_transmitter;
 
architecture tb_interlaken_transmitter of testbench_interlaken_transmitter is
 
signal write_clk : std_logic;
signal clk : std_logic;
signal reset : std_logic;
signal TX_Data_In : std_logic_vector(63 downto 0);
signal TX_Data_Out : std_logic_vector (66 downto 0); -- later 66 downto 0
signal TX_Enable : std_logic; -- Enable the TX
signal TX_SOP : std_logic; -- Start of Packet
signal TX_ValidBytes : std_logic_vector(2 downto 0); -- Valid bytes packet contains
signal TX_EOP : std_logic; -- End of Packet
signal TX_FlowControl : std_logic_vector(15 downto 0); -- Flow control data (yet unutilized)
signal TX_Channel : std_logic_vector(7 downto 0); -- Select transmit channel (yet unutilized)
signal TX_Link_Up : std_logic;
signal TX_Valid_Out : std_logic;
signal TX_Control_Out : std_logic;
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : entity work.interlaken_transmitter
port map (
write_clk => write_clk,
clk => clk,
reset => reset,
TX_Data_In => TX_Data_In,
TX_Data_Out => TX_Data_Out,
TX_Enable => TX_Enable,
TX_SOP => TX_SOP,
TX_ValidBytes => TX_ValidBytes,
TX_EOP => TX_EOP,
TX_FlowControl => TX_FlowControl,
TX_Channel => TX_Channel,
TX_Link_Up => TX_Link_Up,
TX_Valid_Out => TX_Valid_Out,
TX_Control_Out => TX_Control_Out
);
 
Clk_process :process
begin
write_clk <= '1';
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
write_clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
TX_Enable <= '0';
TX_EOP <= '0';
TX_SOP <= '0';
TX_Channel <= X"01";
TX_ValidBytes <= "111";
TX_data_in <= (others=>'0');
reset <= '1';
TX_FlowControl <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
--FIFO_meta <= '1';
reset <= '0';
TX_Enable <= '1';
TX_Data_in <= X"1f5e5d5c5b5a5958";
wait for CLK_PERIOD;
wait for CLK_PERIOD*10;
TX_SOP <= '1';
TX_EOP <= '1';
TX_Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_EOP <= '0';
TX_data_in <= X"3f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '0';
TX_EOP <= '0';
--reset <= '1';
TX_Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
TX_FlowControl(0) <= '1';
TX_SOP <= '1';
TX_data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '1';
TX_data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
TX_EOP <= '0';
--TX_SOP <= '1';
TX_data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
TX_SOP <= '1';
TX_Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '1';
wait for CLK_PERIOD;
TX_EOP <= '0';
--TX_SOP <= '0';
TX_data_in <= X"8050505050050505";
--wait for CLK_PERIOD*3;
wait for CLK_PERIOD;
TX_data_in <= X"9486576758050505";
wait for CLK_PERIOD;
TX_EOP <= '1';
TX_data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD; --Test influencing pause state position
TX_EOP <= '0';
wait for CLK_period*16;
TX_SOP <= '1';
TX_Data_in <= X"4f21a2a3a4a5a6a7";
--wait for CLK_PERIOD;
TX_data_in <= X"995e5a5c5b60f2a0";
wait for CLK_PERIOD;
TX_data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
TX_data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
TX_Data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_Data_in <= X"4f21a2a3a4a5a6a7";
wait for CLK_PERIOD;
TX_data_in <= X"5f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
TX_data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
TX_data_in <= X"70000FFF000000F0";
wait for CLK_PERIOD*2;
TX_data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD*12;
TX_Data_in <= X"4f5e5d5c5b5a5958";
wait for CLK_PERIOD;
TX_SOP <= '0';
TX_EOP <= '1';
wait for CLK_PERIOD;
--FIFO_meta <= '0';
wait for CLK_PERIOD*4;
--FIFO_meta <= '1';
wait;
end process;
 
end architecture tb_interlaken_transmitter;
 
 
/core1990_interlaken/trunk/gateware/simulation/scrambler_tb.vhd
0,0 → 1,122
--
-- This file is an automatically generated VHDL testbench
-- by MakeTestBench (version 1.702)
--
-- Created on : 01 March 2018
--
-- Tested entity : interlaken_scrambler
-- Tested entity from : scrambler_interlaken.vhd
--
library ieee;
use ieee.std_logic_1164.all;
 
entity testbench_scrambler is
end entity testbench_scrambler;
 
architecture tb_interlaken_scrambler of testbench_scrambler is
component Scrambler is
port (
clk : in std_logic;
Scram_Rst : in std_logic;
lane_number : in std_logic_vector(3 downto 0);
Data_Control_In : in std_logic;
Data_Control_Out: out std_logic;
data_in : in std_logic_vector(63 downto 0);
scram_en : in std_logic;
data_out : out std_logic_vector(63 downto 0);
Data_Valid_Out : out std_logic
);
end component Scrambler;
 
for uut : Scrambler use entity work.Scrambler(behavior);
 
signal clk : std_logic := '1';
signal Scram_Rst : std_logic := '1';
signal lane_number : std_logic_vector(3 downto 0) := "0001";
signal Data_Control_In : std_logic;
signal Data_Control_Out : std_logic;
signal data_in : std_logic_vector(63 downto 0);
signal scram_en : std_logic := '0';
signal data_out : std_logic_vector(63 downto 0);
signal Data_Valid_Out : std_logic := '0';
 
constant CLK_PERIOD : time := 10 ns;
 
begin
uut : Scrambler port map (
clk => clk,
Scram_Rst => Scram_Rst,
lane_number => lane_number,
Data_Control_In => Data_Control_In,
Data_Control_Out => Data_Control_Out,
data_in => data_in,
scram_en => scram_en,
data_out => data_out,
Data_Valid_Out => Data_Valid_Out
);
 
Clk_process :process
begin
clk <= '1';
wait for CLK_PERIOD/2; --for half of clock period clk stays at '0'.
clk <= '0';
wait for CLK_PERIOD/2; --for next half of clock period clk stays at '1'.
end process;
simulation : process
begin
wait for 1 ps;
data_in <= (others=>'0');
wait for CLK_PERIOD;
 
wait for CLK_PERIOD;
Scram_Rst <= '0';
scram_en <= '1';
data_in <= X"5f5e5d5c5b5a5958";
wait for CLK_PERIOD;
Data_Control_In <= '1';
Data_In <= X"78f678f678f678f6";
wait for CLK_PERIOD;
Data_Control_In <= '0';
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
data_in <= X"9f5e5d5c5b5a5958";
wait for CLK_PERIOD*2;
data_in <= X"bf21a2a3a4a5a6a7";
Scram_Rst <= '1';
wait for CLK_PERIOD;
Scram_Rst <='0';
wait for CLK_PERIOD;
data_in <= X"2f5e5a5c5b60f2a0";
wait for CLK_PERIOD;
data_in <= X"635e22a3a4a5a7a7";
wait for CLK_PERIOD;
data_in <= X"60b35d5dc4a582a7";
wait for CLK_PERIOD;
data_in <= X"2f5e5d5c5b5a5958";
wait for CLK_PERIOD;
 
Data_Control_In <= '1';
Data_In <= X"78f678f678f678f6";
wait for CLK_PERIOD;
Data_Control_In <= '0';
wait for CLK_PERIOD;
 
wait for CLK_PERIOD;
 
wait;
end process;
end architecture tb_interlaken_scrambler;
 
/core1990_interlaken/trunk/gateware/simulation/testbench_interlaken_interface_behav.wcfg
0,0 → 1,1905
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="testbench_Interface_Test_behav.wdb" id="1">
<top_modules>
<top_module name="glbl" />
<top_module name="testbench_Interface_Test" />
</top_modules>
</db_ref>
</db_ref_list>
<zoom_setting>
<ZoomStartTime time="40729583333fs"></ZoomStartTime>
<ZoomEndTime time="40877083334fs"></ZoomEndTime>
<Cursor1Time time="40940883000fs"></Cursor1Time>
</zoom_setting>
<column_width_setting>
<NameColumnWidth column_width="237"></NameColumnWidth>
<ValueColumnWidth column_width="149"></ValueColumnWidth>
</column_width_setting>
<WVObjectSize size="12" />
<wvobject type="group" fp_name="group83">
<obj_property name="label">Interface</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/System_Clock_In_P">
<obj_property name="ElementShortName">System_Clock_In_P</obj_property>
<obj_property name="ObjectShortName">System_Clock_In_P</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/System_Clock_In_N">
<obj_property name="ElementShortName">System_Clock_In_N</obj_property>
<obj_property name="ObjectShortName">System_Clock_In_N</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/GTREFCLK_IN_P">
<obj_property name="ElementShortName">GTREFCLK_IN_P</obj_property>
<obj_property name="ObjectShortName">GTREFCLK_IN_P</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/GTREFCLK_IN_N">
<obj_property name="ElementShortName">GTREFCLK_IN_N</obj_property>
<obj_property name="ObjectShortName">GTREFCLK_IN_N</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/System_Clock_Gen">
<obj_property name="ElementShortName">System_Clock_Gen</obj_property>
<obj_property name="ObjectShortName">System_Clock_Gen</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/TX_Data">
<obj_property name="ElementShortName">TX_Data[63:0]</obj_property>
<obj_property name="ObjectShortName">TX_Data[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/RX_Data">
<obj_property name="ElementShortName">RX_Data[63:0]</obj_property>
<obj_property name="ObjectShortName">RX_Data[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_Out_P">
<obj_property name="ElementShortName">TX_Out_P</obj_property>
<obj_property name="ObjectShortName">TX_Out_P</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_Out_N">
<obj_property name="ElementShortName">TX_Out_N</obj_property>
<obj_property name="ObjectShortName">TX_Out_N</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_In_P">
<obj_property name="ElementShortName">RX_In_P</obj_property>
<obj_property name="ObjectShortName">RX_In_P</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_In_N">
<obj_property name="ElementShortName">RX_In_N</obj_property>
<obj_property name="ObjectShortName">RX_In_N</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_SOP">
<obj_property name="ElementShortName">TX_SOP</obj_property>
<obj_property name="ObjectShortName">TX_SOP</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_EOP">
<obj_property name="ElementShortName">TX_EOP</obj_property>
<obj_property name="ObjectShortName">TX_EOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/TX_EOP_Valid">
<obj_property name="ElementShortName">TX_EOP_Valid[2:0]</obj_property>
<obj_property name="ObjectShortName">TX_EOP_Valid[2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/TX_FlowControl">
<obj_property name="ElementShortName">TX_FlowControl[15:0]</obj_property>
<obj_property name="ObjectShortName">TX_FlowControl[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/TX_Channel">
<obj_property name="ElementShortName">TX_Channel[7:0]</obj_property>
<obj_property name="ObjectShortName">TX_Channel[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_SOP">
<obj_property name="ElementShortName">RX_SOP</obj_property>
<obj_property name="ObjectShortName">RX_SOP</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_EOP">
<obj_property name="ElementShortName">RX_EOP</obj_property>
<obj_property name="ObjectShortName">RX_EOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/RX_EOP_Valid">
<obj_property name="ElementShortName">RX_EOP_Valid[2:0]</obj_property>
<obj_property name="ObjectShortName">RX_EOP_Valid[2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/RX_FlowControl">
<obj_property name="ElementShortName">RX_FlowControl[15:0]</obj_property>
<obj_property name="ObjectShortName">RX_FlowControl[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/RX_Channel">
<obj_property name="ElementShortName">RX_Channel[7:0]</obj_property>
<obj_property name="ObjectShortName">RX_Channel[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_Link_Up">
<obj_property name="ElementShortName">TX_Link_Up</obj_property>
<obj_property name="ObjectShortName">TX_Link_Up</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_Link_Up">
<obj_property name="ElementShortName">RX_Link_Up</obj_property>
<obj_property name="ObjectShortName">RX_Link_Up</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_FIFO_Full">
<obj_property name="ElementShortName">TX_FIFO_Full</obj_property>
<obj_property name="ObjectShortName">TX_FIFO_Full</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_FIFO_Empty">
<obj_property name="ElementShortName">TX_FIFO_Empty</obj_property>
<obj_property name="ObjectShortName">TX_FIFO_Empty</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_FIFO_Full">
<obj_property name="ElementShortName">RX_FIFO_Full</obj_property>
<obj_property name="ObjectShortName">RX_FIFO_Full</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_FIFO_Empty">
<obj_property name="ElementShortName">RX_FIFO_Empty</obj_property>
<obj_property name="ObjectShortName">RX_FIFO_Empty</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Decoder_lock">
<obj_property name="ElementShortName">Decoder_lock</obj_property>
<obj_property name="ObjectShortName">Decoder_lock</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Descrambler_lock">
<obj_property name="ElementShortName">Descrambler_lock</obj_property>
<obj_property name="ObjectShortName">Descrambler_lock</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/CRC24_Error">
<obj_property name="ElementShortName">CRC24_Error</obj_property>
<obj_property name="ObjectShortName">CRC24_Error</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/CRC32_Error">
<obj_property name="ElementShortName">CRC32_Error</obj_property>
<obj_property name="ObjectShortName">CRC32_Error</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/System_Clock_40">
<obj_property name="ElementShortName">System_Clock_40</obj_property>
<obj_property name="ObjectShortName">System_Clock_40</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_User_Clock">
<obj_property name="ElementShortName">TX_User_Clock</obj_property>
<obj_property name="ObjectShortName">TX_User_Clock</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_User_Clock">
<obj_property name="ElementShortName">RX_User_Clock</obj_property>
<obj_property name="ObjectShortName">RX_User_Clock</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Data_Transferred">
<obj_property name="ElementShortName">Data_Transferred[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_Transferred[66:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/RX_prog_full">
<obj_property name="ElementShortName">RX_prog_full[15:0]</obj_property>
<obj_property name="ObjectShortName">RX_prog_full[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/FlowControl">
<obj_property name="ElementShortName">FlowControl[15:0]</obj_property>
<obj_property name="ObjectShortName">FlowControl[15:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_Datavalid_Out">
<obj_property name="ElementShortName">RX_Datavalid_Out</obj_property>
<obj_property name="ObjectShortName">RX_Datavalid_Out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/RX_Header_Out">
<obj_property name="ElementShortName">RX_Header_Out[2:0]</obj_property>
<obj_property name="ObjectShortName">RX_Header_Out[2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_Headervalid_Out">
<obj_property name="ElementShortName">RX_Headervalid_Out</obj_property>
<obj_property name="ObjectShortName">RX_Headervalid_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_Gearboxslip_In">
<obj_property name="ElementShortName">RX_Gearboxslip_In</obj_property>
<obj_property name="ObjectShortName">RX_Gearboxslip_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/RX_Resetdone_Out">
<obj_property name="ElementShortName">RX_Resetdone_Out</obj_property>
<obj_property name="ObjectShortName">RX_Resetdone_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_Gearboxready_Out">
<obj_property name="ElementShortName">TX_Gearboxready_Out</obj_property>
<obj_property name="ObjectShortName">TX_Gearboxready_Out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/TX_Header_In">
<obj_property name="ElementShortName">TX_Header_In[2:0]</obj_property>
<obj_property name="ObjectShortName">TX_Header_In[2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_Startseq_In">
<obj_property name="ElementShortName">TX_Startseq_In</obj_property>
<obj_property name="ObjectShortName">TX_Startseq_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/TX_Resetdone_Out">
<obj_property name="ElementShortName">TX_Resetdone_Out</obj_property>
<obj_property name="ObjectShortName">TX_Resetdone_Out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Data_Transceiver_In">
<obj_property name="ElementShortName">Data_Transceiver_In[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Transceiver_In[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Data_Transceiver_Out">
<obj_property name="ElementShortName">Data_Transceiver_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Transceiver_Out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/GT0_DATA_VALID_IN">
<obj_property name="ElementShortName">GT0_DATA_VALID_IN</obj_property>
<obj_property name="ObjectShortName">GT0_DATA_VALID_IN</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/GT0_TX_FSM_RESET_DONE_OUT">
<obj_property name="ElementShortName">GT0_TX_FSM_RESET_DONE_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_TX_FSM_RESET_DONE_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/locked">
<obj_property name="ElementShortName">locked</obj_property>
<obj_property name="ObjectShortName">locked</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/reset">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/BurstMax">
<obj_property name="ElementShortName">BurstMax</obj_property>
<obj_property name="ObjectShortName">BurstMax</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/BurstShort">
<obj_property name="ElementShortName">BurstShort</obj_property>
<obj_property name="ObjectShortName">BurstShort</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/PacketLength">
<obj_property name="ElementShortName">PacketLength</obj_property>
<obj_property name="ObjectShortName">PacketLength</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group173">
<obj_property name="label">InterlakenTX</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/write_clk">
<obj_property name="ElementShortName">write_clk</obj_property>
<obj_property name="ObjectShortName">write_clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/reset">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_Data_In">
<obj_property name="ElementShortName">TX_Data_In[63:0]</obj_property>
<obj_property name="ObjectShortName">TX_Data_In[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_Data_Out">
<obj_property name="ElementShortName">TX_Data_Out[66:0]</obj_property>
<obj_property name="ObjectShortName">TX_Data_Out[66:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_Enable">
<obj_property name="ElementShortName">TX_Enable</obj_property>
<obj_property name="ObjectShortName">TX_Enable</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_SOP">
<obj_property name="ElementShortName">TX_SOP</obj_property>
<obj_property name="ObjectShortName">TX_SOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_EOP_Valid">
<obj_property name="ElementShortName">TX_EOP_Valid[2:0]</obj_property>
<obj_property name="ObjectShortName">TX_EOP_Valid[2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_EOP">
<obj_property name="ElementShortName">TX_EOP</obj_property>
<obj_property name="ObjectShortName">TX_EOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_Channel">
<obj_property name="ElementShortName">TX_Channel[7:0]</obj_property>
<obj_property name="ObjectShortName">TX_Channel[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_Gearboxready">
<obj_property name="ElementShortName">TX_Gearboxready</obj_property>
<obj_property name="ObjectShortName">TX_Gearboxready</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_Startseq">
<obj_property name="ElementShortName">TX_Startseq</obj_property>
<obj_property name="ObjectShortName">TX_Startseq</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_FlowControl">
<obj_property name="ElementShortName">TX_FlowControl[15:0]</obj_property>
<obj_property name="ObjectShortName">TX_FlowControl[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/RX_prog_full">
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<obj_property name="ObjectShortName">RX_prog_full[15:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/TX_Link_Up">
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<obj_property name="ObjectShortName">TX_Link_Up</obj_property>
</wvobject>
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<obj_property name="ObjectShortName">pres_state</obj_property>
</wvobject>
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<obj_property name="ObjectShortName">next_state</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Input">
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<obj_property name="ObjectShortName">Data_Input[68:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_FIFO_In">
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<obj_property name="ObjectShortName">Data_FIFO_In[68:0]</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/FIFO_Full">
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<obj_property name="ObjectShortName">FIFO_Full</obj_property>
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</wvobject>
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<obj_property name="ElementShortName">FIFO_Empty</obj_property>
<obj_property name="ObjectShortName">FIFO_Empty</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/FIFO_prog_full">
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<obj_property name="ObjectShortName">FIFO_prog_full</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/FIFO_prog_empty">
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<obj_property name="ObjectShortName">FIFO_prog_empty</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/FIFO_Read_Data">
<obj_property name="ElementShortName">FIFO_Read_Data</obj_property>
<obj_property name="ObjectShortName">FIFO_Read_Data</obj_property>
<obj_property name="CustomSignalColor">#00FF7F</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/FIFO_Write_Data">
<obj_property name="ElementShortName">FIFO_Write_Data</obj_property>
<obj_property name="ObjectShortName">FIFO_Write_Data</obj_property>
<obj_property name="CustomSignalColor">#00FF7F</obj_property>
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</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/FIFO_Read_Count">
<obj_property name="ElementShortName">FIFO_Read_Count[4:0]</obj_property>
<obj_property name="ObjectShortName">FIFO_Read_Count[4:0]</obj_property>
<obj_property name="CustomSignalColor">#00FF7F</obj_property>
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</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/FIFO_Write_Count">
<obj_property name="ElementShortName">FIFO_Write_Count[4:0]</obj_property>
<obj_property name="ObjectShortName">FIFO_Write_Count[4:0]</obj_property>
<obj_property name="CustomSignalColor">#00FF7F</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Burst_In">
<obj_property name="ElementShortName">Data_Burst_In[68:0]</obj_property>
<obj_property name="ObjectShortName">Data_Burst_In[68:0]</obj_property>
<obj_property name="CustomSignalColor">#FF00FF</obj_property>
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</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Burst_Out">
<obj_property name="ElementShortName">Data_Burst_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Burst_Out[63:0]</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Valid_Burst_Out">
<obj_property name="ElementShortName">Data_Valid_Burst_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Burst_Out</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Control_Burst_Out">
<obj_property name="ElementShortName">Data_Control_Burst_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Burst_Out</obj_property>
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</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Meta_Out">
<obj_property name="ElementShortName">Data_Meta_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Meta_Out[63:0]</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Control_Meta_Out">
<obj_property name="ElementShortName">Data_Control_Meta_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Meta_Out</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Valid_Meta_Out">
<obj_property name="ElementShortName">Data_Valid_Meta_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Meta_Out</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/FIFO_Read_Meta">
<obj_property name="ElementShortName">FIFO_Read_Meta</obj_property>
<obj_property name="ObjectShortName">FIFO_Read_Meta</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Control_Scrambler_Out">
<obj_property name="ElementShortName">Data_Control_Scrambler_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Scrambler_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Valid_Scrambler_Out">
<obj_property name="ElementShortName">Data_Valid_Scrambler_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Scrambler_Out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Data_Scrambler_Out">
<obj_property name="ElementShortName">Data_Scrambler_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Scrambler_Out[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/HealthStatus">
<obj_property name="ElementShortName">HealthStatus[1:0]</obj_property>
<obj_property name="ObjectShortName">HealthStatus[1:0]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Gearbox_Count">
<obj_property name="ElementShortName">Gearbox_Count</obj_property>
<obj_property name="ObjectShortName">Gearbox_Count</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Gearbox_Pause">
<obj_property name="ElementShortName">Gearbox_Pause</obj_property>
<obj_property name="ObjectShortName">Gearbox_Pause</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/GearboxSignal">
<obj_property name="ElementShortName">GearboxSignal</obj_property>
<obj_property name="ObjectShortName">GearboxSignal</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/BurstMax">
<obj_property name="ElementShortName">BurstMax</obj_property>
<obj_property name="ObjectShortName">BurstMax</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/BurstShort">
<obj_property name="ElementShortName">BurstShort</obj_property>
<obj_property name="ObjectShortName">BurstShort</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/PacketLength">
<obj_property name="ElementShortName">PacketLength</obj_property>
<obj_property name="ObjectShortName">PacketLength</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group837">
<obj_property name="label">Burstframing</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/clk">
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<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/reset">
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<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/TX_Enable">
<obj_property name="ElementShortName">TX_Enable</obj_property>
<obj_property name="ObjectShortName">TX_Enable</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/TX_SOP">
<obj_property name="ElementShortName">TX_SOP</obj_property>
<obj_property name="ObjectShortName">TX_SOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/TX_ValidBytes">
<obj_property name="ElementShortName">TX_ValidBytes[2:0]</obj_property>
<obj_property name="ObjectShortName">TX_ValidBytes[2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/TX_EOP">
<obj_property name="ElementShortName">TX_EOP</obj_property>
<obj_property name="ObjectShortName">TX_EOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/TX_Channel">
<obj_property name="ElementShortName">TX_Channel[7:0]</obj_property>
<obj_property name="ObjectShortName">TX_Channel[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_in">
<obj_property name="ElementShortName">Data_in[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_in[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_in_valid">
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<obj_property name="ObjectShortName">Data_in_valid</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_out">
<obj_property name="ElementShortName">Data_out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_out[63:0]</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_valid_out">
<obj_property name="ElementShortName">Data_valid_out</obj_property>
<obj_property name="ObjectShortName">Data_valid_out</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_control_out">
<obj_property name="ElementShortName">Data_control_out</obj_property>
<obj_property name="ObjectShortName">Data_control_out</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/TX_FlowControl">
<obj_property name="ElementShortName">TX_FlowControl[15:0]</obj_property>
<obj_property name="ObjectShortName">TX_FlowControl[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/RX_prog_full">
<obj_property name="ElementShortName">RX_prog_full[15:0]</obj_property>
<obj_property name="ObjectShortName">RX_prog_full[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/FIFO_data">
<obj_property name="ElementShortName">FIFO_data[4:0]</obj_property>
<obj_property name="ObjectShortName">FIFO_data[4:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/FIFO_meta">
<obj_property name="ElementShortName">FIFO_meta</obj_property>
<obj_property name="ObjectShortName">FIFO_meta</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/FIFO_read">
<obj_property name="ElementShortName">FIFO_read</obj_property>
<obj_property name="ObjectShortName">FIFO_read</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Gearboxready">
<obj_property name="ElementShortName">Gearboxready</obj_property>
<obj_property name="ObjectShortName">Gearboxready</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/FIFO_Empty">
<obj_property name="ElementShortName">FIFO_Empty</obj_property>
<obj_property name="ObjectShortName">FIFO_Empty</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/FIFO_readreq">
<obj_property name="ElementShortName">FIFO_readreq</obj_property>
<obj_property name="ObjectShortName">FIFO_readreq</obj_property>
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<obj_property name="ElementShortName">pres_state</obj_property>
<obj_property name="ObjectShortName">pres_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/next_state">
<obj_property name="ElementShortName">next_state</obj_property>
<obj_property name="ObjectShortName">next_state</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_Temp">
<obj_property name="ElementShortName">Data_Temp[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Temp[63:0]</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
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</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_valid_temp">
<obj_property name="ElementShortName">Data_valid_temp</obj_property>
<obj_property name="ObjectShortName">Data_valid_temp</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/valid_temp">
<obj_property name="ElementShortName">valid_temp</obj_property>
<obj_property name="ObjectShortName">valid_temp</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Byte_Counter">
<obj_property name="ElementShortName">Byte_Counter</obj_property>
<obj_property name="ObjectShortName">Byte_Counter</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Word_Control_out">
<obj_property name="ElementShortName">Word_Control_out</obj_property>
<obj_property name="ObjectShortName">Word_Control_out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_P1">
<obj_property name="ElementShortName">Data_P1[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P1[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_P2">
<obj_property name="ElementShortName">Data_P2[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P2[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/ControlValid_P1">
<obj_property name="ElementShortName">ControlValid_P1[1:0]</obj_property>
<obj_property name="ObjectShortName">ControlValid_P1[1:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/ControlValid_P2">
<obj_property name="ElementShortName">ControlValid_P2[1:0]</obj_property>
<obj_property name="ObjectShortName">ControlValid_P2[1:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC24_TX">
<obj_property name="ElementShortName">CRC24_TX[63:0]</obj_property>
<obj_property name="ObjectShortName">CRC24_TX[63:0]</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_Valid">
<obj_property name="ElementShortName">Data_Valid</obj_property>
<obj_property name="ObjectShortName">Data_Valid</obj_property>
<obj_property name="CustomSignalColor">#E0FFFF</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Data_Control">
<obj_property name="ElementShortName">Data_Control</obj_property>
<obj_property name="ObjectShortName">Data_Control</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC24_Out">
<obj_property name="ElementShortName">CRC24_Out[31:0]</obj_property>
<obj_property name="ObjectShortName">CRC24_Out[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC24_En">
<obj_property name="ElementShortName">CRC24_En</obj_property>
<obj_property name="ObjectShortName">CRC24_En</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC24_RST">
<obj_property name="ElementShortName">CRC24_RST</obj_property>
<obj_property name="ObjectShortName">CRC24_RST</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC24_P1">
<obj_property name="ElementShortName">CRC24_P1</obj_property>
<obj_property name="ObjectShortName">CRC24_P1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC24_RST_P1">
<obj_property name="ElementShortName">CRC24_RST_P1</obj_property>
<obj_property name="ObjectShortName">CRC24_RST_P1</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC24_Stored">
<obj_property name="ElementShortName">CRC24_Stored[31:0]</obj_property>
<obj_property name="ObjectShortName">CRC24_Stored[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC24_Ready">
<obj_property name="ElementShortName">CRC24_Ready</obj_property>
<obj_property name="ObjectShortName">CRC24_Ready</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC_P1">
<obj_property name="ElementShortName">CRC_P1</obj_property>
<obj_property name="ObjectShortName">CRC_P1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CRC_P2">
<obj_property name="ElementShortName">CRC_P2</obj_property>
<obj_property name="ObjectShortName">CRC_P2</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/Gearboxready_P1">
<obj_property name="ElementShortName">Gearboxready_P1</obj_property>
<obj_property name="ObjectShortName">Gearboxready_P1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/CalcCrc">
<obj_property name="ElementShortName">CalcCrc</obj_property>
<obj_property name="ObjectShortName">CalcCrc</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/BurstMax">
<obj_property name="ElementShortName">BurstMax</obj_property>
<obj_property name="ObjectShortName">BurstMax</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Burst/BurstShort">
<obj_property name="ElementShortName">BurstShort</obj_property>
<obj_property name="ObjectShortName">BurstShort</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group363">
<obj_property name="label">Metaframing</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/reset">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/TX_Enable">
<obj_property name="ElementShortName">TX_Enable</obj_property>
<obj_property name="ObjectShortName">TX_Enable</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/HealthLane">
<obj_property name="ElementShortName">HealthLane</obj_property>
<obj_property name="ObjectShortName">HealthLane</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/HealthInterface">
<obj_property name="ElementShortName">HealthInterface</obj_property>
<obj_property name="ObjectShortName">HealthInterface</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_In">
<obj_property name="ElementShortName">Data_In[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_In[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Out">
<obj_property name="ElementShortName">Data_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Valid_In">
<obj_property name="ElementShortName">Data_Valid_In</obj_property>
<obj_property name="ObjectShortName">Data_Valid_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Valid_Out">
<obj_property name="ElementShortName">Data_Valid_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Control_In">
<obj_property name="ElementShortName">Data_Control_In</obj_property>
<obj_property name="ObjectShortName">Data_Control_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Control_Out">
<obj_property name="ElementShortName">Data_Control_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Gearboxready">
<obj_property name="ElementShortName">Gearboxready</obj_property>
<obj_property name="ObjectShortName">Gearboxready</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/FIFO_read">
<obj_property name="ElementShortName">FIFO_read</obj_property>
<obj_property name="ObjectShortName">FIFO_read</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/pres_state">
<obj_property name="ElementShortName">pres_state</obj_property>
<obj_property name="ObjectShortName">pres_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/next_state">
<obj_property name="ElementShortName">next_state</obj_property>
<obj_property name="ObjectShortName">next_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Packet_Counter">
<obj_property name="ElementShortName">Packet_Counter</obj_property>
<obj_property name="ObjectShortName">Packet_Counter</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Control">
<obj_property name="ElementShortName">Data_Control</obj_property>
<obj_property name="ObjectShortName">Data_Control</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Control_Meta">
<obj_property name="ElementShortName">Data_Control_Meta</obj_property>
<obj_property name="ObjectShortName">Data_Control_Meta</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Control_Burst">
<obj_property name="ElementShortName">Data_Control_Burst</obj_property>
<obj_property name="ObjectShortName">Data_Control_Burst</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Valid">
<obj_property name="ElementShortName">Data_Valid</obj_property>
<obj_property name="ObjectShortName">Data_Valid</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_P1">
<obj_property name="ElementShortName">Data_P1[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P1[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_P2">
<obj_property name="ElementShortName">Data_P2[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P2[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_P3">
<obj_property name="ElementShortName">Data_P3[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P3[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Control_P1">
<obj_property name="ElementShortName">Control_P1</obj_property>
<obj_property name="ObjectShortName">Control_P1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Control_P2">
<obj_property name="ElementShortName">Control_P2</obj_property>
<obj_property name="ObjectShortName">Control_P2</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Control_P3">
<obj_property name="ElementShortName">Control_P3</obj_property>
<obj_property name="ObjectShortName">Control_P3</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_valid_p1">
<obj_property name="ElementShortName">Data_valid_p1</obj_property>
<obj_property name="ObjectShortName">Data_valid_p1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_valid_p2">
<obj_property name="ElementShortName">Data_valid_p2</obj_property>
<obj_property name="ObjectShortName">Data_valid_p2</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_valid_p3">
<obj_property name="ElementShortName">Data_valid_p3</obj_property>
<obj_property name="ObjectShortName">Data_valid_p3</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_valid_framed">
<obj_property name="ElementShortName">Data_valid_framed</obj_property>
<obj_property name="ObjectShortName">Data_valid_framed</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_ControlValid_P1">
<obj_property name="ElementShortName">Data_ControlValid_P1[1:0]</obj_property>
<obj_property name="ObjectShortName">Data_ControlValid_P1[1:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_ControlValid_P2">
<obj_property name="ElementShortName">Data_ControlValid_P2[1:0]</obj_property>
<obj_property name="ObjectShortName">Data_ControlValid_P2[1:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Framed">
<obj_property name="ElementShortName">Data_Framed[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Framed[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Framed_P1">
<obj_property name="ElementShortName">Data_Framed_P1[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Framed_P1[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Data_Framed_P2">
<obj_property name="ElementShortName">Data_Framed_P2[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Framed_P2[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/CRC32_Out">
<obj_property name="ElementShortName">CRC32_Out[31:0]</obj_property>
<obj_property name="ObjectShortName">CRC32_Out[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/CRC32_En">
<obj_property name="ElementShortName">CRC32_En</obj_property>
<obj_property name="ObjectShortName">CRC32_En</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/CRC32_Rst">
<obj_property name="ElementShortName">CRC32_Rst</obj_property>
<obj_property name="ObjectShortName">CRC32_Rst</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/CalcCRC">
<obj_property name="ElementShortName">CalcCRC</obj_property>
<obj_property name="ObjectShortName">CalcCRC</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/CRC32_Ready">
<obj_property name="ElementShortName">CRC32_Ready</obj_property>
<obj_property name="ObjectShortName">CRC32_Ready</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/Gearboxready_P1">
<obj_property name="ElementShortName">Gearboxready_P1</obj_property>
<obj_property name="ObjectShortName">Gearboxready_P1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/CRC32_Rst_P1">
<obj_property name="ElementShortName">CRC32_Rst_P1</obj_property>
<obj_property name="ObjectShortName">CRC32_Rst_P1</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Framing_Meta/PacketLength">
<obj_property name="ElementShortName">PacketLength</obj_property>
<obj_property name="ObjectShortName">PacketLength</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group326">
<obj_property name="label">Scrambler</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Clk">
<obj_property name="ElementShortName">Clk</obj_property>
<obj_property name="ObjectShortName">Clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Scram_Rst">
<obj_property name="ElementShortName">Scram_Rst</obj_property>
<obj_property name="ObjectShortName">Scram_Rst</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Data_In">
<obj_property name="ElementShortName">Data_In[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_In[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Data_Out">
<obj_property name="ElementShortName">Data_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Out[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Lane_Number">
<obj_property name="ElementShortName">Lane_Number[3:0]</obj_property>
<obj_property name="ObjectShortName">Lane_Number[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Scrambler_En">
<obj_property name="ElementShortName">Scrambler_En</obj_property>
<obj_property name="ObjectShortName">Scrambler_En</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Data_Control_In">
<obj_property name="ElementShortName">Data_Control_In</obj_property>
<obj_property name="ObjectShortName">Data_Control_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Data_Control_Out">
<obj_property name="ElementShortName">Data_Control_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Data_Valid_In">
<obj_property name="ElementShortName">Data_Valid_In</obj_property>
<obj_property name="ObjectShortName">Data_Valid_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Data_Valid_Out">
<obj_property name="ElementShortName">Data_Valid_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Gearboxready">
<obj_property name="ElementShortName">Gearboxready</obj_property>
<obj_property name="ObjectShortName">Gearboxready</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Poly">
<obj_property name="ElementShortName">Poly[57:0]</obj_property>
<obj_property name="ObjectShortName">Poly[57:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Scrambling/Shiftreg">
<obj_property name="ElementShortName">Shiftreg[63:0]</obj_property>
<obj_property name="ObjectShortName">Shiftreg[63:0]</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group313">
<obj_property name="label">Encoder</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Clk">
<obj_property name="ElementShortName">Clk</obj_property>
<obj_property name="ObjectShortName">Clk</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Data_In">
<obj_property name="ElementShortName">Data_In[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_In[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Data_Out">
<obj_property name="ElementShortName">Data_Out[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_Out[66:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Data_Control">
<obj_property name="ElementShortName">Data_Control</obj_property>
<obj_property name="ObjectShortName">Data_Control</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Data_valid_in">
<obj_property name="ElementShortName">Data_valid_in</obj_property>
<obj_property name="ObjectShortName">Data_valid_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Data_valid_out">
<obj_property name="ElementShortName">Data_valid_out</obj_property>
<obj_property name="ObjectShortName">Data_valid_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Encoder_En">
<obj_property name="ElementShortName">Encoder_En</obj_property>
<obj_property name="ObjectShortName">Encoder_En</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Encoder_Rst">
<obj_property name="ElementShortName">Encoder_Rst</obj_property>
<obj_property name="ObjectShortName">Encoder_Rst</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Offset">
<obj_property name="ElementShortName">Offset[7:0]</obj_property>
<obj_property name="ObjectShortName">Offset[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_TX/Encoding/Gearboxready">
<obj_property name="ElementShortName">Gearboxready</obj_property>
<obj_property name="ObjectShortName">Gearboxready</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group509">
<obj_property name="label">Transceiver</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/SOFT_RESET_TX_IN">
<obj_property name="ElementShortName">SOFT_RESET_TX_IN</obj_property>
<obj_property name="ObjectShortName">SOFT_RESET_TX_IN</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/SOFT_RESET_RX_IN">
<obj_property name="ElementShortName">SOFT_RESET_RX_IN</obj_property>
<obj_property name="ObjectShortName">SOFT_RESET_RX_IN</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/DONT_RESET_ON_DATA_ERROR_IN">
<obj_property name="ElementShortName">DONT_RESET_ON_DATA_ERROR_IN</obj_property>
<obj_property name="ObjectShortName">DONT_RESET_ON_DATA_ERROR_IN</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/Q0_CLK0_GTREFCLK_PAD_N_IN">
<obj_property name="ElementShortName">Q0_CLK0_GTREFCLK_PAD_N_IN</obj_property>
<obj_property name="ObjectShortName">Q0_CLK0_GTREFCLK_PAD_N_IN</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/Q0_CLK0_GTREFCLK_PAD_P_IN">
<obj_property name="ElementShortName">Q0_CLK0_GTREFCLK_PAD_P_IN</obj_property>
<obj_property name="ObjectShortName">Q0_CLK0_GTREFCLK_PAD_P_IN</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_TX_FSM_RESET_DONE_OUT">
<obj_property name="ElementShortName">GT0_TX_FSM_RESET_DONE_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_TX_FSM_RESET_DONE_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_RX_FSM_RESET_DONE_OUT">
<obj_property name="ElementShortName">GT0_RX_FSM_RESET_DONE_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_RX_FSM_RESET_DONE_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_DATA_VALID_IN">
<obj_property name="ElementShortName">GT0_DATA_VALID_IN</obj_property>
<obj_property name="ObjectShortName">GT0_DATA_VALID_IN</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_TX_MMCM_LOCK_OUT">
<obj_property name="ElementShortName">GT0_TX_MMCM_LOCK_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_TX_MMCM_LOCK_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_RX_MMCM_LOCK_OUT">
<obj_property name="ElementShortName">GT0_RX_MMCM_LOCK_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_RX_MMCM_LOCK_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_TXUSRCLK_OUT">
<obj_property name="ElementShortName">GT0_TXUSRCLK_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_TXUSRCLK_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_TXUSRCLK2_OUT">
<obj_property name="ElementShortName">GT0_TXUSRCLK2_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_TXUSRCLK2_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_RXUSRCLK_OUT">
<obj_property name="ElementShortName">GT0_RXUSRCLK_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_RXUSRCLK_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_RXUSRCLK2_OUT">
<obj_property name="ElementShortName">GT0_RXUSRCLK2_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_RXUSRCLK2_OUT</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_drpaddr_in">
<obj_property name="ElementShortName">gt0_drpaddr_in[8:0]</obj_property>
<obj_property name="ObjectShortName">gt0_drpaddr_in[8:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_drpdi_in">
<obj_property name="ElementShortName">gt0_drpdi_in[15:0]</obj_property>
<obj_property name="ObjectShortName">gt0_drpdi_in[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_drpdo_out">
<obj_property name="ElementShortName">gt0_drpdo_out[15:0]</obj_property>
<obj_property name="ObjectShortName">gt0_drpdo_out[15:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_drpen_in">
<obj_property name="ElementShortName">gt0_drpen_in</obj_property>
<obj_property name="ObjectShortName">gt0_drpen_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_drprdy_out">
<obj_property name="ElementShortName">gt0_drprdy_out</obj_property>
<obj_property name="ObjectShortName">gt0_drprdy_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_drpwe_in">
<obj_property name="ElementShortName">gt0_drpwe_in</obj_property>
<obj_property name="ObjectShortName">gt0_drpwe_in</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_dmonitorout_out">
<obj_property name="ElementShortName">gt0_dmonitorout_out[7:0]</obj_property>
<obj_property name="ObjectShortName">gt0_dmonitorout_out[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_eyescanreset_in">
<obj_property name="ElementShortName">gt0_eyescanreset_in</obj_property>
<obj_property name="ObjectShortName">gt0_eyescanreset_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxuserrdy_in">
<obj_property name="ElementShortName">gt0_rxuserrdy_in</obj_property>
<obj_property name="ObjectShortName">gt0_rxuserrdy_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_eyescandataerror_out">
<obj_property name="ElementShortName">gt0_eyescandataerror_out</obj_property>
<obj_property name="ObjectShortName">gt0_eyescandataerror_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_eyescantrigger_in">
<obj_property name="ElementShortName">gt0_eyescantrigger_in</obj_property>
<obj_property name="ObjectShortName">gt0_eyescantrigger_in</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxdata_out">
<obj_property name="ElementShortName">gt0_rxdata_out[63:0]</obj_property>
<obj_property name="ObjectShortName">gt0_rxdata_out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_gtxrxp_in">
<obj_property name="ElementShortName">gt0_gtxrxp_in</obj_property>
<obj_property name="ObjectShortName">gt0_gtxrxp_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_gtxrxn_in">
<obj_property name="ElementShortName">gt0_gtxrxn_in</obj_property>
<obj_property name="ObjectShortName">gt0_gtxrxn_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxdfelpmreset_in">
<obj_property name="ElementShortName">gt0_rxdfelpmreset_in</obj_property>
<obj_property name="ObjectShortName">gt0_rxdfelpmreset_in</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxmonitorout_out">
<obj_property name="ElementShortName">gt0_rxmonitorout_out[6:0]</obj_property>
<obj_property name="ObjectShortName">gt0_rxmonitorout_out[6:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxmonitorsel_in">
<obj_property name="ElementShortName">gt0_rxmonitorsel_in[1:0]</obj_property>
<obj_property name="ObjectShortName">gt0_rxmonitorsel_in[1:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxoutclkfabric_out">
<obj_property name="ElementShortName">gt0_rxoutclkfabric_out</obj_property>
<obj_property name="ObjectShortName">gt0_rxoutclkfabric_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxdatavalid_out">
<obj_property name="ElementShortName">gt0_rxdatavalid_out</obj_property>
<obj_property name="ObjectShortName">gt0_rxdatavalid_out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxheader_out">
<obj_property name="ElementShortName">gt0_rxheader_out[2:0]</obj_property>
<obj_property name="ObjectShortName">gt0_rxheader_out[2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxheadervalid_out">
<obj_property name="ElementShortName">gt0_rxheadervalid_out</obj_property>
<obj_property name="ObjectShortName">gt0_rxheadervalid_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxgearboxslip_in">
<obj_property name="ElementShortName">gt0_rxgearboxslip_in</obj_property>
<obj_property name="ObjectShortName">gt0_rxgearboxslip_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_gtrxreset_in">
<obj_property name="ElementShortName">gt0_gtrxreset_in</obj_property>
<obj_property name="ObjectShortName">gt0_gtrxreset_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxpmareset_in">
<obj_property name="ElementShortName">gt0_rxpmareset_in</obj_property>
<obj_property name="ObjectShortName">gt0_rxpmareset_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_rxresetdone_out">
<obj_property name="ElementShortName">gt0_rxresetdone_out</obj_property>
<obj_property name="ObjectShortName">gt0_rxresetdone_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_gttxreset_in">
<obj_property name="ElementShortName">gt0_gttxreset_in</obj_property>
<obj_property name="ObjectShortName">gt0_gttxreset_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_txuserrdy_in">
<obj_property name="ElementShortName">gt0_txuserrdy_in</obj_property>
<obj_property name="ObjectShortName">gt0_txuserrdy_in</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_txdata_in">
<obj_property name="ElementShortName">gt0_txdata_in[63:0]</obj_property>
<obj_property name="ObjectShortName">gt0_txdata_in[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_gtxtxn_out">
<obj_property name="ElementShortName">gt0_gtxtxn_out</obj_property>
<obj_property name="ObjectShortName">gt0_gtxtxn_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_gtxtxp_out">
<obj_property name="ElementShortName">gt0_gtxtxp_out</obj_property>
<obj_property name="ObjectShortName">gt0_gtxtxp_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_txoutclkfabric_out">
<obj_property name="ElementShortName">gt0_txoutclkfabric_out</obj_property>
<obj_property name="ObjectShortName">gt0_txoutclkfabric_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_txoutclkpcs_out">
<obj_property name="ElementShortName">gt0_txoutclkpcs_out</obj_property>
<obj_property name="ObjectShortName">gt0_txoutclkpcs_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_txgearboxready_out">
<obj_property name="ElementShortName">gt0_txgearboxready_out</obj_property>
<obj_property name="ObjectShortName">gt0_txgearboxready_out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_txheader_in">
<obj_property name="ElementShortName">gt0_txheader_in[2:0]</obj_property>
<obj_property name="ObjectShortName">gt0_txheader_in[2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_txstartseq_in">
<obj_property name="ElementShortName">gt0_txstartseq_in</obj_property>
<obj_property name="ObjectShortName">gt0_txstartseq_in</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/gt0_txresetdone_out">
<obj_property name="ElementShortName">gt0_txresetdone_out</obj_property>
<obj_property name="ObjectShortName">gt0_txresetdone_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_QPLLLOCK_OUT">
<obj_property name="ElementShortName">GT0_QPLLLOCK_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_QPLLLOCK_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_QPLLREFCLKLOST_OUT">
<obj_property name="ElementShortName">GT0_QPLLREFCLKLOST_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_QPLLREFCLKLOST_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_QPLLOUTCLK_OUT">
<obj_property name="ElementShortName">GT0_QPLLOUTCLK_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_QPLLOUTCLK_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/GT0_QPLLOUTREFCLK_OUT">
<obj_property name="ElementShortName">GT0_QPLLOUTREFCLK_OUT</obj_property>
<obj_property name="ObjectShortName">GT0_QPLLOUTREFCLK_OUT</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Transceiver_10g_64b67b_i/sysclk_in">
<obj_property name="ElementShortName">sysclk_in</obj_property>
<obj_property name="ObjectShortName">sysclk_in</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group130">
<obj_property name="label">InterlakenRX</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/fifo_read_clk">
<obj_property name="ElementShortName">fifo_read_clk</obj_property>
<obj_property name="ObjectShortName">fifo_read_clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/reset">
<obj_property name="ElementShortName">reset</obj_property>
<obj_property name="ObjectShortName">reset</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_Data_In">
<obj_property name="ElementShortName">RX_Data_In[66:0]</obj_property>
<obj_property name="ObjectShortName">RX_Data_In[66:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_Data_Out">
<obj_property name="ElementShortName">RX_Data_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">RX_Data_Out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_Enable">
<obj_property name="ElementShortName">RX_Enable</obj_property>
<obj_property name="ObjectShortName">RX_Enable</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_SOP">
<obj_property name="ElementShortName">RX_SOP</obj_property>
<obj_property name="ObjectShortName">RX_SOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_ValidBytes">
<obj_property name="ElementShortName">RX_ValidBytes[2:0]</obj_property>
<obj_property name="ObjectShortName">RX_ValidBytes[2:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_EOP">
<obj_property name="ElementShortName">RX_EOP</obj_property>
<obj_property name="ObjectShortName">RX_EOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_FlowControl">
<obj_property name="ElementShortName">RX_FlowControl[15:0]</obj_property>
<obj_property name="ObjectShortName">RX_FlowControl[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_prog_full">
<obj_property name="ElementShortName">RX_prog_full[15:0]</obj_property>
<obj_property name="ObjectShortName">RX_prog_full[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_Channel">
<obj_property name="ElementShortName">RX_Channel[7:0]</obj_property>
<obj_property name="ObjectShortName">RX_Channel[7:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_Datavalid">
<obj_property name="ElementShortName">RX_Datavalid</obj_property>
<obj_property name="ObjectShortName">RX_Datavalid</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/CRC24_Error">
<obj_property name="ElementShortName">CRC24_Error</obj_property>
<obj_property name="ObjectShortName">CRC24_Error</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/CRC32_Error">
<obj_property name="ElementShortName">CRC32_Error</obj_property>
<obj_property name="ObjectShortName">CRC32_Error</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder_lock">
<obj_property name="ElementShortName">Decoder_lock</obj_property>
<obj_property name="ObjectShortName">Decoder_lock</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler_lock">
<obj_property name="ElementShortName">Descrambler_lock</obj_property>
<obj_property name="ObjectShortName">Descrambler_lock</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/FIFO_Full">
<obj_property name="ElementShortName">FIFO_Full</obj_property>
<obj_property name="ObjectShortName">FIFO_Full</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/FIFO_empty">
<obj_property name="ElementShortName">FIFO_empty</obj_property>
<obj_property name="ObjectShortName">FIFO_empty</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_Link_Up">
<obj_property name="ElementShortName">RX_Link_Up</obj_property>
<obj_property name="ObjectShortName">RX_Link_Up</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Bitslip">
<obj_property name="ElementShortName">Bitslip</obj_property>
<obj_property name="ObjectShortName">Bitslip</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/pres_state">
<obj_property name="ElementShortName">pres_state</obj_property>
<obj_property name="ObjectShortName">pres_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/next_state">
<obj_property name="ElementShortName">next_state</obj_property>
<obj_property name="ObjectShortName">next_state</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_FIFO_Data">
<obj_property name="ElementShortName">RX_FIFO_Data[65:0]</obj_property>
<obj_property name="ObjectShortName">RX_FIFO_Data[65:0]</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/RX_FIFO_Write">
<obj_property name="ElementShortName">RX_FIFO_Write</obj_property>
<obj_property name="ObjectShortName">RX_FIFO_Write</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/FIFO_Read_Count">
<obj_property name="ElementShortName">FIFO_Read_Count[5:0]</obj_property>
<obj_property name="ObjectShortName">FIFO_Read_Count[5:0]</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/FIFO_Write_Count">
<obj_property name="ElementShortName">FIFO_Write_Count[5:0]</obj_property>
<obj_property name="ObjectShortName">FIFO_Write_Count[5:0]</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/FIFO_prog_full">
<obj_property name="ElementShortName">FIFO_prog_full</obj_property>
<obj_property name="ObjectShortName">FIFO_prog_full</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/FIFO_prog_empty">
<obj_property name="ElementShortName">FIFO_prog_empty</obj_property>
<obj_property name="ObjectShortName">FIFO_prog_empty</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/FIFO_Data_Out">
<obj_property name="ElementShortName">FIFO_Data_Out[65:0]</obj_property>
<obj_property name="ObjectShortName">FIFO_Data_Out[65:0]</obj_property>
<obj_property name="CustomSignalColor">#808000</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_Burst_Out">
<obj_property name="ElementShortName">Data_Burst_Out[65:0]</obj_property>
<obj_property name="ObjectShortName">Data_Burst_Out[65:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_valid_Burst_Out">
<obj_property name="ElementShortName">Data_valid_Burst_Out</obj_property>
<obj_property name="ObjectShortName">Data_valid_Burst_Out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Flowcontrol">
<obj_property name="ElementShortName">Flowcontrol[15:0]</obj_property>
<obj_property name="ObjectShortName">Flowcontrol[15:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_Descrambler_Out">
<obj_property name="ElementShortName">Data_Descrambler_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Descrambler_Out[63:0]</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_valid_Descrambler_out">
<obj_property name="ElementShortName">Data_valid_Descrambler_out</obj_property>
<obj_property name="ObjectShortName">Data_valid_Descrambler_out</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_Control_Descrambler_Out">
<obj_property name="ElementShortName">Data_Control_Descrambler_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Descrambler_Out</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_Meta_Out">
<obj_property name="ElementShortName">Data_Meta_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Meta_Out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_valid_Meta_out">
<obj_property name="ElementShortName">Data_valid_Meta_out</obj_property>
<obj_property name="ObjectShortName">Data_valid_Meta_out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_control_Meta_out">
<obj_property name="ElementShortName">Data_control_Meta_out</obj_property>
<obj_property name="ObjectShortName">Data_control_Meta_out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_Decoder_Out">
<obj_property name="ElementShortName">Data_Decoder_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Decoder_Out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_Control_Decoder_Out">
<obj_property name="ElementShortName">Data_Control_Decoder_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Decoder_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Data_valid_decoder_out">
<obj_property name="ElementShortName">Data_valid_decoder_out</obj_property>
<obj_property name="ObjectShortName">Data_valid_decoder_out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Lane_Number">
<obj_property name="ElementShortName">Lane_Number[3:0]</obj_property>
<obj_property name="ObjectShortName">Lane_Number[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Error_BadSync">
<obj_property name="ElementShortName">Error_BadSync</obj_property>
<obj_property name="ObjectShortName">Error_BadSync</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Error_StateMismatch">
<obj_property name="ElementShortName">Error_StateMismatch</obj_property>
<obj_property name="ObjectShortName">Error_StateMismatch</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Error_NoSync">
<obj_property name="ElementShortName">Error_NoSync</obj_property>
<obj_property name="ObjectShortName">Error_NoSync</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Error_Decoder_Sync">
<obj_property name="ElementShortName">Error_Decoder_Sync</obj_property>
<obj_property name="ObjectShortName">Error_Decoder_Sync</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler_In_lock">
<obj_property name="ElementShortName">Descrambler_In_lock</obj_property>
<obj_property name="ObjectShortName">Descrambler_In_lock</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/PacketLength">
<obj_property name="ElementShortName">PacketLength</obj_property>
<obj_property name="ObjectShortName">PacketLength</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group658">
<obj_property name="label">Decoder</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Clk">
<obj_property name="ElementShortName">Clk</obj_property>
<obj_property name="ObjectShortName">Clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Reset">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_In">
<obj_property name="ElementShortName">Data_In[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_In[66:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Decoder_En">
<obj_property name="ElementShortName">Decoder_En</obj_property>
<obj_property name="ObjectShortName">Decoder_En</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_Valid_In">
<obj_property name="ElementShortName">Data_Valid_In</obj_property>
<obj_property name="ObjectShortName">Data_Valid_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_Valid_Out">
<obj_property name="ElementShortName">Data_Valid_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_Out">
<obj_property name="ElementShortName">Data_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_Control">
<obj_property name="ElementShortName">Data_Control</obj_property>
<obj_property name="ObjectShortName">Data_Control</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Sync_Locked">
<obj_property name="ElementShortName">Sync_Locked</obj_property>
<obj_property name="ObjectShortName">Sync_Locked</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Sync_Error">
<obj_property name="ElementShortName">Sync_Error</obj_property>
<obj_property name="ObjectShortName">Sync_Error</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Bitslip">
<obj_property name="ElementShortName">Bitslip</obj_property>
<obj_property name="ObjectShortName">Bitslip</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/pres_state">
<obj_property name="ElementShortName">pres_state</obj_property>
<obj_property name="ObjectShortName">pres_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/next_state">
<obj_property name="ElementShortName">next_state</obj_property>
<obj_property name="ObjectShortName">next_state</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_T1">
<obj_property name="ElementShortName">Data_T1[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_T1[66:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_T2">
<obj_property name="ElementShortName">Data_T2[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_T2[66:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_T3">
<obj_property name="ElementShortName">Data_T3[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_T3[66:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_Valid_P1">
<obj_property name="ElementShortName">Data_Valid_P1</obj_property>
<obj_property name="ObjectShortName">Data_Valid_P1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_Valid_P2">
<obj_property name="ElementShortName">Data_Valid_P2</obj_property>
<obj_property name="ObjectShortName">Data_Valid_P2</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_Valid_P3">
<obj_property name="ElementShortName">Data_Valid_P3</obj_property>
<obj_property name="ObjectShortName">Data_Valid_P3</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_P1">
<obj_property name="ElementShortName">Data_P1[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_P1[66:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_P2">
<obj_property name="ElementShortName">Data_P2[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_P2[66:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Data_P3">
<obj_property name="ElementShortName">Data_P3[66:0]</obj_property>
<obj_property name="ObjectShortName">Data_P3[66:0]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Sync_Transition_Location">
<obj_property name="ElementShortName">Sync_Transition_Location</obj_property>
<obj_property name="ObjectShortName">Sync_Transition_Location</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Sync_Search">
<obj_property name="ElementShortName">Sync_Search</obj_property>
<obj_property name="ObjectShortName">Sync_Search</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Sync_Counter">
<obj_property name="ElementShortName">Sync_Counter</obj_property>
<obj_property name="ObjectShortName">Sync_Counter</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Word_Counter">
<obj_property name="ElementShortName">Word_Counter</obj_property>
<obj_property name="ObjectShortName">Word_Counter</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Sync_Error_Counter">
<obj_property name="ElementShortName">Sync_Error_Counter</obj_property>
<obj_property name="ObjectShortName">Sync_Error_Counter</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Decoder/Trans_result">
<obj_property name="ElementShortName">Trans_result</obj_property>
<obj_property name="ObjectShortName">Trans_result</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group453">
<obj_property name="label">Descrambler</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Clk">
<obj_property name="ElementShortName">Clk</obj_property>
<obj_property name="ObjectShortName">Clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Reset">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_In">
<obj_property name="ElementShortName">Data_In[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_In[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Valid_In">
<obj_property name="ElementShortName">Data_Valid_In</obj_property>
<obj_property name="ObjectShortName">Data_Valid_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Control_In">
<obj_property name="ElementShortName">Data_Control_In</obj_property>
<obj_property name="ObjectShortName">Data_Control_In</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Out">
<obj_property name="ElementShortName">Data_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Valid_Out">
<obj_property name="ElementShortName">Data_Valid_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Control_Out">
<obj_property name="ElementShortName">Data_Control_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Out</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Lane_Number">
<obj_property name="ElementShortName">Lane_Number[3:0]</obj_property>
<obj_property name="ObjectShortName">Lane_Number[3:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Lock">
<obj_property name="ElementShortName">Lock</obj_property>
<obj_property name="ObjectShortName">Lock</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Error_BadSync">
<obj_property name="ElementShortName">Error_BadSync</obj_property>
<obj_property name="ObjectShortName">Error_BadSync</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Error_StateMismatch">
<obj_property name="ElementShortName">Error_StateMismatch</obj_property>
<obj_property name="ObjectShortName">Error_StateMismatch</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Error_NoSync">
<obj_property name="ElementShortName">Error_NoSync</obj_property>
<obj_property name="ObjectShortName">Error_NoSync</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/pres_state">
<obj_property name="ElementShortName">pres_state</obj_property>
<obj_property name="ObjectShortName">pres_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/next_state">
<obj_property name="ElementShortName">next_state</obj_property>
<obj_property name="ObjectShortName">next_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/MetaCounter">
<obj_property name="ElementShortName">MetaCounter</obj_property>
<obj_property name="ObjectShortName">MetaCounter</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Sync_Word_Detected">
<obj_property name="ElementShortName">Sync_Word_Detected</obj_property>
<obj_property name="ObjectShortName">Sync_Word_Detected</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Sync_Words">
<obj_property name="ElementShortName">Sync_Words</obj_property>
<obj_property name="ObjectShortName">Sync_Words</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Valid_P1">
<obj_property name="ElementShortName">Data_Valid_P1</obj_property>
<obj_property name="ObjectShortName">Data_Valid_P1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Valid_P2">
<obj_property name="ElementShortName">Data_Valid_P2</obj_property>
<obj_property name="ObjectShortName">Data_Valid_P2</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Valid">
<obj_property name="ElementShortName">Data_Valid</obj_property>
<obj_property name="ObjectShortName">Data_Valid</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Control_P1">
<obj_property name="ElementShortName">Data_Control_P1</obj_property>
<obj_property name="ObjectShortName">Data_Control_P1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Control_P2">
<obj_property name="ElementShortName">Data_Control_P2</obj_property>
<obj_property name="ObjectShortName">Data_Control_P2</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Control">
<obj_property name="ElementShortName">Data_Control</obj_property>
<obj_property name="ObjectShortName">Data_Control</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_P1">
<obj_property name="ElementShortName">Data_P1[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P1[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Data_Descrambled">
<obj_property name="ElementShortName">Data_Descrambled[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Descrambled[63:0]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Scrambler_State_Mismatch">
<obj_property name="ElementShortName">Scrambler_State_Mismatch</obj_property>
<obj_property name="ObjectShortName">Scrambler_State_Mismatch</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Sync_Word_Mismatch">
<obj_property name="ElementShortName">Sync_Word_Mismatch</obj_property>
<obj_property name="ObjectShortName">Sync_Word_Mismatch</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Poly">
<obj_property name="ElementShortName">Poly[57:0]</obj_property>
<obj_property name="ObjectShortName">Poly[57:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/Shiftreg">
<obj_property name="ElementShortName">Shiftreg[63:0]</obj_property>
<obj_property name="ObjectShortName">Shiftreg[63:0]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Descrambler/PacketLength">
<obj_property name="ElementShortName">PacketLength</obj_property>
<obj_property name="ObjectShortName">PacketLength</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group600">
<obj_property name="label">Deframing_Meta</obj_property>
<obj_property name="DisplayName">label</obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Clk">
<obj_property name="ElementShortName">Clk</obj_property>
<obj_property name="ObjectShortName">Clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Reset">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Deframer_En">
<obj_property name="ElementShortName">Deframer_En</obj_property>
<obj_property name="ObjectShortName">Deframer_En</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_In">
<obj_property name="ElementShortName">Data_In[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_In[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_Out">
<obj_property name="ElementShortName">Data_Out[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_Out[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_Control_In">
<obj_property name="ElementShortName">Data_Control_In</obj_property>
<obj_property name="ObjectShortName">Data_Control_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_Control_Out">
<obj_property name="ElementShortName">Data_Control_Out</obj_property>
<obj_property name="ObjectShortName">Data_Control_Out</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_Error">
<obj_property name="ElementShortName">CRC32_Error</obj_property>
<obj_property name="ObjectShortName">CRC32_Error</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_Valid_In">
<obj_property name="ElementShortName">Data_Valid_In</obj_property>
<obj_property name="ObjectShortName">Data_Valid_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_Valid_Out">
<obj_property name="ElementShortName">Data_Valid_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Out</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/pres_state">
<obj_property name="ElementShortName">pres_state</obj_property>
<obj_property name="ObjectShortName">pres_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/next_state">
<obj_property name="ElementShortName">next_state</obj_property>
<obj_property name="ObjectShortName">next_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Packet_Counter">
<obj_property name="ElementShortName">Packet_Counter</obj_property>
<obj_property name="ObjectShortName">Packet_Counter</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_P1">
<obj_property name="ElementShortName">Data_P1[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P1[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_P2">
<obj_property name="ElementShortName">Data_P2[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P2[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Data_P3">
<obj_property name="ElementShortName">Data_P3[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_P3[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/Diagnostic_Error">
<obj_property name="ElementShortName">Diagnostic_Error</obj_property>
<obj_property name="ObjectShortName">Diagnostic_Error</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_Value">
<obj_property name="ElementShortName">CRC32_Value[31:0]</obj_property>
<obj_property name="ObjectShortName">CRC32_Value[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/HealthLane">
<obj_property name="ElementShortName">HealthLane</obj_property>
<obj_property name="ObjectShortName">HealthLane</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/HealthInterface">
<obj_property name="ElementShortName">HealthInterface</obj_property>
<obj_property name="ObjectShortName">HealthInterface</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_In">
<obj_property name="ElementShortName">CRC32_In[63:0]</obj_property>
<obj_property name="ObjectShortName">CRC32_In[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_Out">
<obj_property name="ElementShortName">CRC32_Out[31:0]</obj_property>
<obj_property name="ObjectShortName">CRC32_Out[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_En">
<obj_property name="ElementShortName">CRC32_En</obj_property>
<obj_property name="ObjectShortName">CRC32_En</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_Rst">
<obj_property name="ElementShortName">CRC32_Rst</obj_property>
<obj_property name="ObjectShortName">CRC32_Rst</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CrcCalc">
<obj_property name="ElementShortName">CrcCalc</obj_property>
<obj_property name="ObjectShortName">CrcCalc</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_Check1">
<obj_property name="ElementShortName">CRC32_Check1</obj_property>
<obj_property name="ObjectShortName">CRC32_Check1</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_Check2">
<obj_property name="ElementShortName">CRC32_Check2</obj_property>
<obj_property name="ObjectShortName">CRC32_Check2</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Meta/CRC32_Good">
<obj_property name="ElementShortName">CRC32_Good</obj_property>
<obj_property name="ObjectShortName">CRC32_Good</obj_property>
</wvobject>
</wvobject>
<wvobject type="group" fp_name="group628">
<obj_property name="label">Deframing_Burst</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Clk">
<obj_property name="ElementShortName">Clk</obj_property>
<obj_property name="ObjectShortName">Clk</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Reset">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Deburst_En">
<obj_property name="ElementShortName">Deburst_En</obj_property>
<obj_property name="ObjectShortName">Deburst_En</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_In">
<obj_property name="ElementShortName">Data_In[63:0]</obj_property>
<obj_property name="ObjectShortName">Data_In[63:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_Control_In">
<obj_property name="ElementShortName">Data_Control_In</obj_property>
<obj_property name="ObjectShortName">Data_Control_In</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_Valid_In">
<obj_property name="ElementShortName">Data_Valid_In</obj_property>
<obj_property name="ObjectShortName">Data_Valid_In</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_Out">
<obj_property name="ElementShortName">Data_Out[65:0]</obj_property>
<obj_property name="ObjectShortName">Data_Out[65:0]</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_Valid_Out">
<obj_property name="ElementShortName">Data_Valid_Out</obj_property>
<obj_property name="ObjectShortName">Data_Valid_Out</obj_property>
<obj_property name="CustomSignalColor">#FFD700</obj_property>
<obj_property name="UseCustomSignalColor">true</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/CRC24_Error">
<obj_property name="ElementShortName">CRC24_Error</obj_property>
<obj_property name="ObjectShortName">CRC24_Error</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Flowcontrol">
<obj_property name="ElementShortName">Flowcontrol[15:0]</obj_property>
<obj_property name="ObjectShortName">Flowcontrol[15:0]</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/pres_state">
<obj_property name="ElementShortName">pres_state</obj_property>
<obj_property name="ObjectShortName">pres_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/next_state">
<obj_property name="ElementShortName">next_state</obj_property>
<obj_property name="ObjectShortName">next_state</obj_property>
</wvobject>
<wvobject type="other" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Packet_Counter">
<obj_property name="ElementShortName">Packet_Counter</obj_property>
<obj_property name="ObjectShortName">Packet_Counter</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_P1">
<obj_property name="ElementShortName">Data_P1[65:0]</obj_property>
<obj_property name="ObjectShortName">Data_P1[65:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_P2">
<obj_property name="ElementShortName">Data_P2[65:0]</obj_property>
<obj_property name="ObjectShortName">Data_P2[65:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_P3">
<obj_property name="ElementShortName">Data_P3[65:0]</obj_property>
<obj_property name="ObjectShortName">Data_P3[65:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Data_Temp">
<obj_property name="ElementShortName">Data_Temp[65:0]</obj_property>
<obj_property name="ObjectShortName">Data_Temp[65:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/CRC24_Value">
<obj_property name="ElementShortName">CRC24_Value[31:0]</obj_property>
<obj_property name="ObjectShortName">CRC24_Value[31:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/CRC24_Value_P1">
<obj_property name="ElementShortName">CRC24_Value_P1[31:0]</obj_property>
<obj_property name="ObjectShortName">CRC24_Value_P1[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/SOP">
<obj_property name="ElementShortName">SOP</obj_property>
<obj_property name="ObjectShortName">SOP</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/EOP">
<obj_property name="ElementShortName">EOP</obj_property>
<obj_property name="ObjectShortName">EOP</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/EOP_Valid">
<obj_property name="ElementShortName">EOP_Valid[2:0]</obj_property>
<obj_property name="ObjectShortName">EOP_Valid[2:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/Channel">
<obj_property name="ElementShortName">Channel[7:0]</obj_property>
<obj_property name="ObjectShortName">Channel[7:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/CRC24_In">
<obj_property name="ElementShortName">CRC24_In[63:0]</obj_property>
<obj_property name="ObjectShortName">CRC24_In[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/CRC24_Out">
<obj_property name="ElementShortName">CRC24_Out[31:0]</obj_property>
<obj_property name="ObjectShortName">CRC24_Out[31:0]</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/CRC24_En">
<obj_property name="ElementShortName">CRC24_En</obj_property>
<obj_property name="ObjectShortName">CRC24_En</obj_property>
</wvobject>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/interface/Interlaken_RX/Deframing_Burst/CRC24_Rst">
<obj_property name="ElementShortName">CRC24_Rst</obj_property>
<obj_property name="ObjectShortName">CRC24_Rst</obj_property>
</wvobject>
<wvobject type="group" fp_name="group657">
<obj_property name="label">ILA</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="isExpanded"></obj_property>
<wvobject type="logic" fp_name="/testbench_Interface_Test/uut/probe_data/clk">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/probe_data/probe0">
<obj_property name="ElementShortName">probe0[63:0]</obj_property>
<obj_property name="ObjectShortName">probe0[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/probe_data/probe1">
<obj_property name="ElementShortName">probe1[4:0]</obj_property>
<obj_property name="ObjectShortName">probe1[4:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/probe_data/probe2">
<obj_property name="ElementShortName">probe2[63:0]</obj_property>
<obj_property name="ObjectShortName">probe2[63:0]</obj_property>
</wvobject>
<wvobject type="array" fp_name="/testbench_Interface_Test/uut/probe_data/probe3">
<obj_property name="ElementShortName">probe3[4:0]</obj_property>
<obj_property name="ObjectShortName">probe3[4:0]</obj_property>
</wvobject>
</wvobject>
</wvobject>
</wave_config>
/core1990_interlaken/trunk/gateware/sources/crc/crc-24.vhd
0,0 → 1,106
--******************************************************************************
--* *
--* Calculates a CRC-24 over the data at Din, data may *
--* already arrive when Reset is high *
--* The process from Din to CRC takes 2 Clk cycles *
--* Frans Schreuder (Nikhef) franss@nikhef.nl *
--* *
--******************************************************************************
library ieee;
use ieee.std_logic_1164.all;
library work;
 
entity CRC_24 is
generic(
Nbits : positive := 64;
CRC_Width : positive := 24;
G_Poly: Std_Logic_Vector :=x"32_8B63"; --c1acf
G_InitVal: std_logic_vector:=x"ffff_ffff"
);
port(
CRC : out std_logic_vector(CRC_Width-1 downto 0);
Calc : in std_logic;
Clk : in std_logic;
DIn : in std_logic_vector(Nbits-1 downto 0);
Reset : in std_logic);
end CRC_24;
 
 
architecture rtl of CRC_24 is
 
function ToIndirectInitVal(Direct:std_logic_vector; CRC_Width: positive; Poly: std_logic_vector) return std_logic_vector is
variable InDirect: std_logic_vector(Direct'high downto Direct'low);
begin
for k in 0 to CRC_Width loop
if(k = 0) then
InDirect := Direct;
else
if(InDirect(0)='1') then
InDirect := (('0'&InDirect(CRC_Width-1 downto 1)) xor ('1'&Poly(CRC_Width-1 downto 1)));
else
InDirect := '0'&InDirect(CRC_Width-1 downto 1);
end if;
end if;
end loop;
return InDirect;
end function ToIndirectInitVal;
constant Poly: Std_Logic_Vector(CRC_Width-1 downto 0) := G_Poly;
constant InitVal: Std_Logic_Vector(CRC_Width-1 downto 0) := G_InitVal;
constant InDirectInitVal: std_logic_vector(CRC_Width-1 downto 0):=ToIndirectInitVal(InitVal, CRC_Width, Poly);
signal Reg_s : std_logic_vector(CRC_Width-1 downto 0);
begin
process (Clk)
variable Reg, Reg2: Std_Logic_Vector (CRC_Width-1 downto 0);
variable ApplyPoly: std_logic;
begin
 
if rising_Edge(Clk) then
if Reset = '1' then
if(Calc = '1') then
for k In 0 to Nbits loop
if(k = 0) then
Reg := (InDirectInitVal);--(CRC_Width-1 downto 0)&dinP(k))xor ('0'&Poly);
else
if Reg(CRC_Width-1) = '1' then
Reg := (Reg(CRC_Width-2 downto 0)&din(Nbits - k))xor (Poly);
else
Reg := Reg(CRC_Width-2 downto 0)&din(Nbits - k);
end if;
end if;
end loop;
else
Reg := InDirectInitVal;
end if;
else
if Calc = '1' then
for k In 1 to Nbits loop
if Reg(CRC_Width-1) = '1' then
Reg := (Reg(CRC_Width-2 downto 0)&din(Nbits - k))xor (Poly);
else
Reg := Reg(CRC_Width-2 downto 0)&din(Nbits - k);
end if;
end loop;
else
Reg := Reg;
end if;
end if;
Reg_s <= Reg;
Reg2 := Reg_s;
--we need one more loop to output the CRC register to the output.
for k In 1 to CRC_Width loop
if Reg2(CRC_Width-1) = '1' then
Reg2 := (Reg2(CRC_Width-2 downto 0)&'0')xor (Poly);
else
Reg2:= Reg2(CRC_Width-2 downto 0)&'0';
end if;
end loop;
CRC <= Reg2;--(CRC_width-1 downto 0);
end if;
end process;
end architecture rtl ; -- of CRC
/core1990_interlaken/trunk/gateware/sources/crc/crc-32.vhd
0,0 → 1,109
 
--******************************************************************************
--* *
--* Calculates a CRC-32 over the data at Din, data may *
--* already arrive when Reset is high *
--* The process from Din to CRC takes 2 Clk cycles *
--* Frans Schreuder (Nikhef) franss@nikhef.nl *
--* *
--******************************************************************************
 
 
library ieee;
use ieee.std_logic_1164.all;
library work;
 
entity CRC_32 is
generic(
Nbits : positive := 64;
CRC_Width : positive := 32;
G_Poly: Std_Logic_Vector :=x"1EDC_6F41"; --c1acf
G_InitVal: std_logic_vector:=x"ffff_ffff"
);
port(
CRC : out std_logic_vector(CRC_Width-1 downto 0);
Calc : in std_logic;
Clk : in std_logic;
DIn : in std_logic_vector(Nbits-1 downto 0);
Reset : in std_logic);
end CRC_32;
 
 
architecture rtl of CRC_32 is
 
function ToIndirectInitVal(Direct:std_logic_vector; CRC_Width: positive; Poly: std_logic_vector) return std_logic_vector is
variable InDirect: std_logic_vector(Direct'high downto Direct'low);
begin
for k in 0 to CRC_Width loop
if(k = 0) then
InDirect := Direct;
else
if(InDirect(0)='1') then
InDirect := (('0'&InDirect(CRC_Width-1 downto 1)) xor ('1'&Poly(CRC_Width-1 downto 1)));
else
InDirect := '0'&InDirect(CRC_Width-1 downto 1);
end if;
end if;
end loop;
return InDirect;
end function ToIndirectInitVal;
constant Poly: Std_Logic_Vector(CRC_Width-1 downto 0) := G_Poly;
constant InitVal: Std_Logic_Vector(CRC_Width-1 downto 0) := G_InitVal;
constant InDirectInitVal: std_logic_vector(CRC_Width-1 downto 0):=ToIndirectInitVal(InitVal, CRC_Width, Poly);
signal Reg_s : std_logic_vector(CRC_Width-1 downto 0);
begin
process (Clk)
variable Reg, Reg2: Std_Logic_Vector (CRC_Width-1 downto 0);
variable ApplyPoly: std_logic;
begin
 
if rising_Edge(Clk) then
if Reset = '1' then
if(Calc = '1') then
for k In 0 to Nbits loop
if(k = 0) then
Reg := (InDirectInitVal);--(CRC_Width-1 downto 0)&dinP(k))xor ('0'&Poly);
else
if Reg(CRC_Width-1) = '1' then
Reg := (Reg(CRC_Width-2 downto 0)&din(Nbits - k))xor (Poly);
else
Reg := Reg(CRC_Width-2 downto 0)&din(Nbits - k);
end if;
end if;
end loop;
else
Reg := InDirectInitVal;
end if;
else
if Calc = '1' then
for k In 1 to Nbits loop
if Reg(CRC_Width-1) = '1' then
Reg := (Reg(CRC_Width-2 downto 0)&din(Nbits - k))xor (Poly);
else
Reg := Reg(CRC_Width-2 downto 0)&din(Nbits - k);
end if;
end loop;
else
Reg := Reg;
end if;
end if;
Reg_s <= Reg;
Reg2 := Reg_s;
--we need one more loop to output the CRC register to the output.
for k In 1 to CRC_Width loop
if Reg2(CRC_Width-1) = '1' then
Reg2 := (Reg2(CRC_Width-2 downto 0)&'0')xor (Poly);
else
Reg2:= Reg2(CRC_Width-2 downto 0)&'0';
end if;
end loop;
CRC <= Reg2;--(CRC_width-1 downto 0);
end if;
end process;
end architecture rtl ; -- of CRC
/core1990_interlaken/trunk/gateware/sources/ip_cores/ILA_Data.xci
0,0 → 1,3189
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>ILA_Data</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ila" spirit:version="6.2"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADV_TRIGGER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_MULT_F">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_DIVIDE_F">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_FREQ">200</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_PERIOD">5.0</spirit:configurableElementValue>
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