URL
https://opencores.org/ocsvn/core1990_interlaken/core1990_interlaken/trunk
Subversion Repositories core1990_interlaken
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- This comparison shows the changes necessary to convert path
/core1990_interlaken/trunk/gateware/constraints
- from Rev 8 to Rev 6
- ↔ Reverse comparison
Rev 8 → Rev 6
/Core1990_Constraints.xdc
12,15 → 12,7
############################################################################### |
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## Pin locations of the transceiver and system clock |
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set_property PACKAGE_PIN AK34 [get_ports USER_CLK_IN_P] |
set_property IOSTANDARD LVDS [get_ports USER_CLK_IN_P] |
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set_property PACKAGE_PIN AJ32 [get_ports USER_SMA_CLK_OUT_P] |
set_property IOSTANDARD LVDS [get_ports USER_SMA_CLK_OUT_P] |
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set_property PACKAGE_PIN AK8 [get_ports GTREFCLK_IN_P] |
set_property PACKAGE_PIN AH8 [get_ports GTREFCLK_IN_P] |
set_property PACKAGE_PIN E19 [get_ports System_Clock_In_P] |
set_property IOSTANDARD LVDS [get_ports System_Clock_In_P] |
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31,9 → 23,6
set_property PACKAGE_PIN AM39 [get_ports Valid_out] |
set_property IOSTANDARD LVCMOS18 [get_ports Valid_out] |
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set_property PACKAGE_PIN AN39 [get_ports Lock_Out] |
set_property IOSTANDARD LVCMOS18 [get_ports Lock_Out] |
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############################################################################### |
## Timing constraints |
############################################################################### |
42,14 → 31,13
create_clock -period 8.000 -name tc_GTREFCLK_IN_P [get_ports GTREFCLK_IN_P] |
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## Clock relations |
set_max_delay -datapath_only -from [get_clocks clkout0*] -to [get_clocks clk_out1_clk_40MHz*] 25.000 |
set_max_delay -datapath_only -from [get_clocks clk_out1_clk_40MHz*] -to [get_clocks clkout0*] 25.000 |
set_max_delay -datapath_only -from [get_clocks clkout0*] -to [get_clocks clk_out2_clk_40MHz*] 8.333 |
set_max_delay -datapath_only -from [get_clocks clk_out2_clk_40MHz*] -to [get_clocks clkout0*] 8.333 |
set_max_delay -datapath_only -from [get_clocks clkout0] -to [get_clocks clk_out1_clk_40MHz*] 25.000 |
set_max_delay -datapath_only -from [get_clocks clk_out1_clk_40MHz*] -to [get_clocks clkout0] 25.000 |
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############################################################################### |
## Resets and False paths |
############################################################################### |
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set_false_path -valid_path -from [get_ports Valid_out] |
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############################################################################### |