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URL https://opencores.org/ocsvn/cryptopan_core/cryptopan_core/trunk

Subversion Repositories cryptopan_core

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Rev 1 → Rev 2

/trunk/rtl/sbox.coe
0,0 → 1,258
memory_initialization_radix=16;
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16;
/trunk/rtl/round_unit.vhd
0,0 → 1,161
--
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
use work.cryptopan.all;
 
entity round_unit is
generic (
do_mixcolumns : boolean := true);
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
 
in_en : in std_logic;
out_en : out std_logic;
 
load_en : in std_logic;
load_data : in std_logic_vector(31 downto 0);
 
load_clk : in std_logic;
clk : in std_logic;
reset : in std_logic
);
 
end round_unit;
 
architecture rtl of round_unit is
 
component mixcolumns
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
clk : in std_logic;
reset : in std_logic);
end component;
 
component subbytesshiftrows
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
clk : in std_logic;
reset : in std_logic);
end component;
signal sbsr_out : s_vector;
signal mix_out : s_vector;
 
signal round_key : s_vector;
signal round_out : s_vector;
 
signal load_counter : std_logic_vector(1 downto 0);
signal sbsr_out_en : std_logic;
signal mix_out_en : std_logic;
begin
 
bytes_out <= round_out;
 
LOAD_LOGIC : process (load_clk, reset)
begin
if reset = '1' then
for i in 0 to 15 loop
round_key(i) <= (others => '0');
end loop;
load_counter <= "00";
 
elsif load_clk'event and load_clk = '1' then
 
if load_en = '1' then
if load_counter = "00" then
round_key(12) <= load_data(7 downto 0);
round_key(8) <= load_data(15 downto 8);
round_key(4) <= load_data(23 downto 16);
round_key(0) <= load_data(31 downto 24);
elsif load_counter = "01" then
round_key(13) <= load_data(7 downto 0);
round_key(9) <= load_data(15 downto 8);
round_key(5) <= load_data(23 downto 16);
round_key(1) <= load_data(31 downto 24);
elsif load_counter = "10" then
round_key(14) <= load_data(7 downto 0);
round_key(10) <= load_data(15 downto 8);
round_key(6) <= load_data(23 downto 16);
round_key(2) <= load_data(31 downto 24);
elsif load_counter = "11" then
round_key(15) <= load_data(7 downto 0);
round_key(11) <= load_data(15 downto 8);
round_key(7) <= load_data(23 downto 16);
round_key(3) <= load_data(31 downto 24);
end if;
load_counter <= load_counter + 1;
else
load_counter <= "00";
end if;
end if;
end process LOAD_LOGIC;
 
SBSR0 : subbytesshiftrows
port map (
bytes_in => bytes_in,
bytes_out => sbsr_out,
in_en => in_en,
out_en => sbsr_out_en,
clk => clk,
reset => reset);
 
out_en <= mix_out_en;
 
GENMIXCOLUMNS : if do_mixcolumns = true generate
MIX0 : mixcolumns
port map (
bytes_in => sbsr_out,
bytes_out => mix_out,
in_en => sbsr_out_en,
out_en => mix_out_en,
clk => clk,
reset => reset);
 
end generate GENMIXCOLUMNS;
 
NO_GENMIXCOLUMNS : if do_mixcolumns = false generate
mix_out <= sbsr_out;
mix_out_en <= sbsr_out_en;
end generate NO_GENMIXCOLUMNS;
 
 
ROUND_XOR : for i in 0 to 15 generate
round_out(i) <= round_key(i) xor mix_out(i);
end generate ROUND_XOR;
 
 
end rtl;
/trunk/rtl/subbytesshiftrows.vhd
0,0 → 1,134
--
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.cryptopan.all;
 
entity subbytesshiftrows is
 
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
 
in_en : in std_logic;
out_en : out std_logic;
 
clk : in std_logic;
reset : in std_logic
);
 
end subbytesshiftrows;
 
 
architecture rtl of subbytesshiftrows is
 
component dual_bram_256x8
port (
addra : IN std_logic_VECTOR(7 downto 0);
addrb : IN std_logic_VECTOR(7 downto 0);
clka : IN std_logic;
clkb : IN std_logic;
douta : OUT std_logic_VECTOR(7 downto 0);
doutb : OUT std_logic_VECTOR(7 downto 0));
end component;
component sbox
port (
clk : in std_logic;
reset : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0));
end component;
 
signal subbytes_out : s_vector;
 
signal in_en_int : std_logic;
 
begin -- rtl
 
out_en <= in_en_int;
 
CLKLOGIC : process (clk, reset)
begin
if reset = '1' then
in_en_int <= '0';
elsif clk'event and clk = '1' then
in_en_int <= in_en;
end if;
end process CLKLOGIC;
 
USE_BRAM_GEN : if use_bram = true generate
GEN_SBOX_BRAM : for i in 0 to 7 generate
 
SBOX_i: dual_bram_256x8
port map (
addra => bytes_in(i),
addrb => bytes_in(i+8),
clka => clk,
clkb => clk,
douta => subbytes_out(i),
doutb => subbytes_out(i+8));
end generate GEN_SBOX_BRAM;
end generate USE_BRAM_GEN;
 
NO_BRAM_GEN : if use_bram = false generate
GEN_SBOX_NOBRAM : for i in 0 to 15 generate
SBOX_i : sbox
port map (
clk => clk,
reset => reset,
addra => bytes_in(i),
douta => subbytes_out(i) );
 
end generate GEN_SBOX_NOBRAM;
end generate NO_BRAM_GEN;
 
bytes_out(0) <= subbytes_out(0);
bytes_out(1) <= subbytes_out(1);
bytes_out(2) <= subbytes_out(2);
bytes_out(3) <= subbytes_out(3);
 
bytes_out(4) <= subbytes_out(5);
bytes_out(5) <= subbytes_out(6);
bytes_out(6) <= subbytes_out(7);
bytes_out(7) <= subbytes_out(4);
 
bytes_out(8) <= subbytes_out(10);
bytes_out(9) <= subbytes_out(11);
bytes_out(10) <= subbytes_out(8);
bytes_out(11) <= subbytes_out(9);
 
bytes_out(12) <= subbytes_out(15);
bytes_out(13) <= subbytes_out(12);
bytes_out(14) <= subbytes_out(13);
bytes_out(15) <= subbytes_out(14);
 
 
 
end rtl;
/trunk/rtl/cryptopan_package.vhd
0,0 → 1,40
--
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
 
package cryptopan is
 
type s_vector is array(0 to 15) of std_logic_vector(7 downto 0);
 
constant use_bram : boolean := true;
 
end cryptopan;
 
package body cryptopan is
 
end cryptopan;
/trunk/rtl/aes_encrypt_unit.vhd
0,0 → 1,370
--
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
use work.cryptopan.all;
 
entity aes_encrypt_unit is
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
 
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
 
clk : in std_logic;
reset : in std_logic
);
 
end aes_encrypt_unit;
 
architecture rtl of aes_encrypt_unit is
 
component round_unit
generic (
do_mixcolumns : boolean);
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
in_en : in std_logic;
out_en : out std_logic;
load_en : in std_logic;
load_data : in std_logic_vector(31 downto 0);
load_clk : in std_logic;
clk : in std_logic;
reset : in std_logic);
end component;
 
component dual_bram_256x8
port (
addra : IN std_logic_VECTOR(7 downto 0);
addrb : IN std_logic_VECTOR(7 downto 0);
clka : IN std_logic;
clkb : IN std_logic;
douta : OUT std_logic_VECTOR(7 downto 0);
doutb : OUT std_logic_VECTOR(7 downto 0));
end component;
component sbox
port (
clk : in std_logic;
reset : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0));
end component;
signal cipher_key : s_vector;
signal input : s_vector;
 
type states is (INIT, KEY_EXP_INIT, KEY_EXP, LOADED);
signal state : states;
 
signal key_exp_counter : std_logic_vector(1 downto 0);
--signal round_onehot_counter : std_logic_vector(9 downto 0);
signal round_shift_counter : std_logic_vector(9 downto 0);
signal rcon : std_logic_vector(7 downto 0);
signal subword : std_logic_vector(31 downto 0);
signal subword_xor_rcon : std_logic_vector(31 downto 0);
 
signal cur_w : std_logic_vector(31 downto 0);
signal cur_w_rot : std_logic_vector(31 downto 0);
signal w0 : std_logic_vector(31 downto 0);
signal w1 : std_logic_vector(31 downto 0);
signal w2 : std_logic_vector(31 downto 0);
 
signal load_bit : std_logic;
 
type s_vector_array is array (0 to 10) of s_vector;
signal round_bytes : s_vector_array;
signal round_en : std_logic_vector(0 to 10);
signal round_load_en : std_logic_vector(0 to 9);
 
signal sbox_clk : std_logic;
 
signal slow_clk : std_logic;
signal clk_counter : std_logic_vector(1 downto 0);
 
signal key_wren_int : std_logic;
signal key_wren_counter : std_logic_vector(2 downto 0);
begin -- rtl
 
SLOWCLK_LOGIC: process (clk, reset)
begin
if reset = '1' then
clk_counter <= (others => '0');
elsif clk'event and clk = '1' then
clk_counter <= clk_counter + 1;
end if;
end process SLOWCLK_LOGIC;
 
slow_clk <= clk_counter(1);
sbox_clk <= not slow_clk;
 
cur_w_rot <= cur_w(23 downto 0) & cur_w(31 downto 24);
subword_xor_rcon <= (rcon xor subword(31 downto 24)) & subword(23 downto 0);
 
GEN_BRAM: if use_bram=true generate
GEN_SBOX_BRAM: for i in 0 to 1 generate
SBOX_i: dual_bram_256x8
port map (
addra => cur_w_rot((8*i)+7 downto (8*i)),
addrb => cur_w_rot((8*i)+23 downto (8*i)+16),
clka => sbox_clk,
clkb => sbox_clk,
douta => subword((8*i)+7 downto (8*i)),
doutb => subword((8*i)+23 downto (8*i)+16)
);
end generate GEN_SBOX_BRAM;
end generate GEN_BRAM;
 
GEN_NO_BRAM: if use_bram=false generate
GEN_SBOX_NO_BRAM: for i in 0 to 3 generate
SBOX_i: sbox
port map (
clk => sbox_clk,
reset => reset,
addra => cur_w_rot((8*i)+7 downto (8*i)),
douta => subword((8*i)+7 downto (8*i)) );
end generate GEN_SBOX_NO_BRAM;
end generate GEN_NO_BRAM;
 
 
round_en(0) <= data_wren;
data_dv <= round_en(10);
 
data_out(127 downto 120) <= round_bytes(10)(0);
data_out(119 downto 112) <= round_bytes(10)(4);
data_out(111 downto 104) <= round_bytes(10)(8);
data_out(103 downto 96) <= round_bytes(10)(12);
data_out(95 downto 88) <= round_bytes(10)(1);
data_out(87 downto 80) <= round_bytes(10)(5);
data_out(79 downto 72) <= round_bytes(10)(9);
data_out(71 downto 64) <= round_bytes(10)(13);
data_out(63 downto 56) <= round_bytes(10)(2);
data_out(55 downto 48) <= round_bytes(10)(6);
data_out(47 downto 40) <= round_bytes(10)(10);
data_out(39 downto 32) <= round_bytes(10)(14);
data_out(31 downto 24) <= round_bytes(10)(3);
data_out(23 downto 16) <= round_bytes(10)(7);
data_out(15 downto 8) <= round_bytes(10)(11);
data_out(7 downto 0) <= round_bytes(10)(15);
input(0) <= data_in(127 downto 120);
input(4) <= data_in(119 downto 112);
input(8) <= data_in(111 downto 104);
input(12) <= data_in(103 downto 96);
input(1) <= data_in(95 downto 88);
input(5) <= data_in(87 downto 80);
input(9) <= data_in(79 downto 72);
input(13) <= data_in(71 downto 64);
input(2) <= data_in(63 downto 56);
input(6) <= data_in(55 downto 48);
input(10) <= data_in(47 downto 40);
input(14) <= data_in(39 downto 32);
input(3) <= data_in(31 downto 24);
input(7) <= data_in(23 downto 16);
input(11) <= data_in(15 downto 8);
input(15) <= data_in(7 downto 0);
 
FIRST_ROUND_INPUT : for i in 0 to 15 generate
round_bytes(0)(i) <= cipher_key(i) xor input(i);
end generate FIRST_ROUND_INPUT;
 
KEYWREN_LOGIC: process (clk, reset)
begin
if reset = '1' then
key_wren_counter <= (others => '0');
elsif clk'event and clk = '1' then
if key_wren='1' then
key_wren_counter <= "100";
elsif key_wren_counter(2)='1' then
key_wren_counter <= key_wren_counter + 1;
end if;
end if;
end process KEYWREN_LOGIC;
key_wren_int <= key_wren_counter(2);
CLKLOGIC : process (slow_clk, reset)
begin
if reset = '1' then
for i in 0 to 15 loop
cipher_key(i) <= (others => '0');
end loop;
state <= INIT;
ready <= '0';
elsif slow_clk'event and slow_clk = '1' then
 
if key_wren_int = '1' then
cipher_key(0) <= key_in(127 downto 120);
cipher_key(4) <= key_in(119 downto 112);
cipher_key(8) <= key_in(111 downto 104);
cipher_key(12) <= key_in(103 downto 96);
cipher_key(1) <= key_in(95 downto 88);
cipher_key(5) <= key_in(87 downto 80);
cipher_key(9) <= key_in(79 downto 72);
cipher_key(13) <= key_in(71 downto 64);
cipher_key(2) <= key_in(63 downto 56);
cipher_key(6) <= key_in(55 downto 48);
cipher_key(10) <= key_in(47 downto 40);
cipher_key(14) <= key_in(39 downto 32);
cipher_key(3) <= key_in(31 downto 24);
cipher_key(7) <= key_in(23 downto 16);
cipher_key(11) <= key_in(15 downto 8);
cipher_key(15) <= key_in(7 downto 0);
 
state <= KEY_EXP_INIT;
end if;
 
if state = KEY_EXP_INIT then
state <= KEY_EXP;
end if;
 
if state = KEY_EXP then
if round_shift_counter(9) = '1' and key_exp_counter = "11" then
state <= LOADED;
end if;
end if;
 
if state = LOADED then
ready <= '1';
else
ready <= '0';
end if;
end if;
end process CLKLOGIC;
 
with round_shift_counter select
rcon <=
X"02" when "0000000010",
X"04" when "0000000100",
X"08" when "0000001000",
X"10" when "0000010000",
X"20" when "0000100000",
X"40" when "0001000000",
X"80" when "0010000000",
X"1b" when "0100000000",
X"36" when "1000000000",
X"01" when others;
 
with state select
load_bit <=
'1' when KEY_EXP,
'0' when others;
 
 
ROUNTER_CNT_LOGIC : process (slow_clk, reset)
begin
if reset = '1' then
key_exp_counter <= (others => '0');
--round_onehot_counter <= "0000000001";
round_shift_counter <= "0000000001";
w0 <= (others => '0');
w1 <= (others => '0');
w2 <= (others => '0');
cur_w <= (others => '0');
 
 
elsif slow_clk'event and slow_clk = '1' then
if key_wren_int = '1' then
w0 <= key_in(127 downto 96);
w1 <= key_in(95 downto 64);
w2 <= key_in(63 downto 32);
cur_w <= key_in(31 downto 0);
 
elsif state = KEY_EXP then
 
w0 <= w1;
w1 <= w2;
w2 <= cur_w;
 
if key_exp_counter = "00" then
cur_w <= subword_xor_rcon xor w0;
else
cur_w <= cur_w xor w0;
end if;
 
key_exp_counter <= key_exp_counter + 1;
 
if key_exp_counter = "11" then
round_shift_counter <= round_shift_counter(8 downto 0) & round_shift_counter(9);
end if;
 
end if;
end if;
end process ROUNTER_CNT_LOGIC;
 
 
ROUND_GEN : for i in 0 to 8 generate
ROUND_I : round_unit
generic map (
do_mixcolumns => true )
port map (
bytes_in => round_bytes(i),
bytes_out => round_bytes(i+1),
in_en => round_en(i),
out_en => round_en(i+1),
load_en => round_load_en(i),
load_data => cur_w,
load_clk => slow_clk,
clk => clk,
reset => reset);
end generate ROUND_GEN;
 
ROUND9 : round_unit
generic map (
do_mixcolumns => false)
port map (
bytes_in => round_bytes(9),
bytes_out => round_bytes(10),
in_en => round_en(9),
out_en => round_en(10),
load_en => round_load_en(9),
load_data => cur_w,
load_clk => slow_clk,
clk => clk,
reset => reset);
 
LOAD_EN_DELAY : process (slow_clk, reset)
begin
if reset = '1' then
round_load_en <= (others => '0');
elsif slow_clk'event and slow_clk = '1' then
for i in 0 to 9 loop
round_load_en(i) <= round_shift_counter(i) and load_bit;
end loop;
end if;
end process LOAD_EN_DELAY;
 
end rtl;
/trunk/rtl/sbox.vhd
0,0 → 1,322
--
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.cryptopan.all;
 
entity sbox is
 
port (
clk : in std_logic;
reset : in std_logic;
addra : in std_logic_vector(7 downto 0);
douta : out std_logic_vector(7 downto 0));
 
end sbox;
 
architecture rtl of sbox is
signal data : std_logic_vector(7 downto 0);
 
attribute syn_romstyle : string;
attribute syn_romstyle of data : signal is "logic";
begin
 
CLKLOGIC : process (clk, reset)
begin
if reset = '1' then
douta <= (others => '0');
elsif clk'event and clk = '1' then
douta <= data;
end if;
end process CLKLOGIC;
 
DATALOGIC : process (addra)
begin
case addra is
 
when "00000000" => data <= X"63";
when "00000001" => data <= X"7C";
when "00000010" => data <= X"77";
when "00000011" => data <= X"7B";
when "00000100" => data <= X"F2";
when "00000101" => data <= X"6B";
when "00000110" => data <= X"6F";
when "00000111" => data <= X"C5";
when "00001000" => data <= X"30";
when "00001001" => data <= X"01";
when "00001010" => data <= X"67";
when "00001011" => data <= X"2B";
when "00001100" => data <= X"FE";
when "00001101" => data <= X"D7";
when "00001110" => data <= X"AB";
when "00001111" => data <= X"76";
when "00010000" => data <= X"CA";
when "00010001" => data <= X"82";
when "00010010" => data <= X"C9";
when "00010011" => data <= X"7D";
when "00010100" => data <= X"FA";
when "00010101" => data <= X"59";
when "00010110" => data <= X"47";
when "00010111" => data <= X"F0";
when "00011000" => data <= X"AD";
when "00011001" => data <= X"D4";
when "00011010" => data <= X"A2";
when "00011011" => data <= X"AF";
when "00011100" => data <= X"9C";
when "00011101" => data <= X"A4";
when "00011110" => data <= X"72";
when "00011111" => data <= X"C0";
when "00100000" => data <= X"B7";
when "00100001" => data <= X"FD";
when "00100010" => data <= X"93";
when "00100011" => data <= X"26";
when "00100100" => data <= X"36";
when "00100101" => data <= X"3F";
when "00100110" => data <= X"F7";
when "00100111" => data <= X"CC";
when "00101000" => data <= X"34";
when "00101001" => data <= X"A5";
when "00101010" => data <= X"E5";
when "00101011" => data <= X"F1";
when "00101100" => data <= X"71";
when "00101101" => data <= X"D8";
when "00101110" => data <= X"31";
when "00101111" => data <= X"15";
when "00110000" => data <= X"04";
when "00110001" => data <= X"C7";
when "00110010" => data <= X"23";
when "00110011" => data <= X"C3";
when "00110100" => data <= X"18";
when "00110101" => data <= X"96";
when "00110110" => data <= X"05";
when "00110111" => data <= X"9A";
when "00111000" => data <= X"07";
when "00111001" => data <= X"12";
when "00111010" => data <= X"80";
when "00111011" => data <= X"E2";
when "00111100" => data <= X"EB";
when "00111101" => data <= X"27";
when "00111110" => data <= X"B2";
when "00111111" => data <= X"75";
when "01000000" => data <= X"09";
when "01000001" => data <= X"83";
when "01000010" => data <= X"2C";
when "01000011" => data <= X"1A";
when "01000100" => data <= X"1B";
when "01000101" => data <= X"6E";
when "01000110" => data <= X"5A";
when "01000111" => data <= X"A0";
when "01001000" => data <= X"52";
when "01001001" => data <= X"3B";
when "01001010" => data <= X"D6";
when "01001011" => data <= X"B3";
when "01001100" => data <= X"29";
when "01001101" => data <= X"E3";
when "01001110" => data <= X"2F";
when "01001111" => data <= X"84";
when "01010000" => data <= X"53";
when "01010001" => data <= X"D1";
when "01010010" => data <= X"00";
when "01010011" => data <= X"ED";
when "01010100" => data <= X"20";
when "01010101" => data <= X"FC";
when "01010110" => data <= X"B1";
when "01010111" => data <= X"5B";
when "01011000" => data <= X"6A";
when "01011001" => data <= X"CB";
when "01011010" => data <= X"BE";
when "01011011" => data <= X"39";
when "01011100" => data <= X"4A";
when "01011101" => data <= X"4C";
when "01011110" => data <= X"58";
when "01011111" => data <= X"CF";
when "01100000" => data <= X"D0";
when "01100001" => data <= X"EF";
when "01100010" => data <= X"AA";
when "01100011" => data <= X"FB";
when "01100100" => data <= X"43";
when "01100101" => data <= X"4D";
when "01100110" => data <= X"33";
when "01100111" => data <= X"85";
when "01101000" => data <= X"45";
when "01101001" => data <= X"F9";
when "01101010" => data <= X"02";
when "01101011" => data <= X"7F";
when "01101100" => data <= X"50";
when "01101101" => data <= X"3C";
when "01101110" => data <= X"9F";
when "01101111" => data <= X"A8";
when "01110000" => data <= X"51";
when "01110001" => data <= X"A3";
when "01110010" => data <= X"40";
when "01110011" => data <= X"8F";
when "01110100" => data <= X"92";
when "01110101" => data <= X"9D";
when "01110110" => data <= X"38";
when "01110111" => data <= X"F5";
when "01111000" => data <= X"BC";
when "01111001" => data <= X"B6";
when "01111010" => data <= X"DA";
when "01111011" => data <= X"21";
when "01111100" => data <= X"10";
when "01111101" => data <= X"FF";
when "01111110" => data <= X"F3";
when "01111111" => data <= X"D2";
when "10000000" => data <= X"CD";
when "10000001" => data <= X"0C";
when "10000010" => data <= X"13";
when "10000011" => data <= X"EC";
when "10000100" => data <= X"5F";
when "10000101" => data <= X"97";
when "10000110" => data <= X"44";
when "10000111" => data <= X"17";
when "10001000" => data <= X"C4";
when "10001001" => data <= X"A7";
when "10001010" => data <= X"7E";
when "10001011" => data <= X"3D";
when "10001100" => data <= X"64";
when "10001101" => data <= X"5D";
when "10001110" => data <= X"19";
when "10001111" => data <= X"73";
when "10010000" => data <= X"60";
when "10010001" => data <= X"81";
when "10010010" => data <= X"4F";
when "10010011" => data <= X"DC";
when "10010100" => data <= X"22";
when "10010101" => data <= X"2A";
when "10010110" => data <= X"90";
when "10010111" => data <= X"88";
when "10011000" => data <= X"46";
when "10011001" => data <= X"EE";
when "10011010" => data <= X"B8";
when "10011011" => data <= X"14";
when "10011100" => data <= X"DE";
when "10011101" => data <= X"5E";
when "10011110" => data <= X"0B";
when "10011111" => data <= X"DB";
when "10100000" => data <= X"E0";
when "10100001" => data <= X"32";
when "10100010" => data <= X"3A";
when "10100011" => data <= X"0A";
when "10100100" => data <= X"49";
when "10100101" => data <= X"06";
when "10100110" => data <= X"24";
when "10100111" => data <= X"5C";
when "10101000" => data <= X"C2";
when "10101001" => data <= X"D3";
when "10101010" => data <= X"AC";
when "10101011" => data <= X"62";
when "10101100" => data <= X"91";
when "10101101" => data <= X"95";
when "10101110" => data <= X"E4";
when "10101111" => data <= X"79";
when "10110000" => data <= X"E7";
when "10110001" => data <= X"C8";
when "10110010" => data <= X"37";
when "10110011" => data <= X"6D";
when "10110100" => data <= X"8D";
when "10110101" => data <= X"D5";
when "10110110" => data <= X"4E";
when "10110111" => data <= X"A9";
when "10111000" => data <= X"6C";
when "10111001" => data <= X"56";
when "10111010" => data <= X"F4";
when "10111011" => data <= X"EA";
when "10111100" => data <= X"65";
when "10111101" => data <= X"7A";
when "10111110" => data <= X"AE";
when "10111111" => data <= X"08";
when "11000000" => data <= X"BA";
when "11000001" => data <= X"78";
when "11000010" => data <= X"25";
when "11000011" => data <= X"2E";
when "11000100" => data <= X"1C";
when "11000101" => data <= X"A6";
when "11000110" => data <= X"B4";
when "11000111" => data <= X"C6";
when "11001000" => data <= X"E8";
when "11001001" => data <= X"DD";
when "11001010" => data <= X"74";
when "11001011" => data <= X"1F";
when "11001100" => data <= X"4B";
when "11001101" => data <= X"BD";
when "11001110" => data <= X"8B";
when "11001111" => data <= X"8A";
when "11010000" => data <= X"70";
when "11010001" => data <= X"3E";
when "11010010" => data <= X"B5";
when "11010011" => data <= X"66";
when "11010100" => data <= X"48";
when "11010101" => data <= X"03";
when "11010110" => data <= X"F6";
when "11010111" => data <= X"0E";
when "11011000" => data <= X"61";
when "11011001" => data <= X"35";
when "11011010" => data <= X"57";
when "11011011" => data <= X"B9";
when "11011100" => data <= X"86";
when "11011101" => data <= X"C1";
when "11011110" => data <= X"1D";
when "11011111" => data <= X"9E";
when "11100000" => data <= X"E1";
when "11100001" => data <= X"F8";
when "11100010" => data <= X"98";
when "11100011" => data <= X"11";
when "11100100" => data <= X"69";
when "11100101" => data <= X"D9";
when "11100110" => data <= X"8E";
when "11100111" => data <= X"94";
when "11101000" => data <= X"9B";
when "11101001" => data <= X"1E";
when "11101010" => data <= X"87";
when "11101011" => data <= X"E9";
when "11101100" => data <= X"CE";
when "11101101" => data <= X"55";
when "11101110" => data <= X"28";
when "11101111" => data <= X"DF";
when "11110000" => data <= X"8C";
when "11110001" => data <= X"A1";
when "11110010" => data <= X"89";
when "11110011" => data <= X"0D";
when "11110100" => data <= X"BF";
when "11110101" => data <= X"E6";
when "11110110" => data <= X"42";
when "11110111" => data <= X"68";
when "11111000" => data <= X"41";
when "11111001" => data <= X"99";
when "11111010" => data <= X"2D";
when "11111011" => data <= X"0F";
when "11111100" => data <= X"B0";
when "11111101" => data <= X"54";
when "11111110" => data <= X"BB";
when "11111111" => data <= X"16";
when others => null;
end case;
end process DATALOGIC;
end rtl;
/trunk/rtl/dual_bram_256x8.mif
0,0 → 1,256
01100011
01111100
01110111
01111011
11110010
01101011
01101111
11000101
00110000
00000001
01100111
00101011
11111110
11010111
10101011
01110110
11001010
10000010
11001001
01111101
11111010
01011001
01000111
11110000
10101101
11010100
10100010
10101111
10011100
10100100
01110010
11000000
10110111
11111101
10010011
00100110
00110110
00111111
11110111
11001100
00110100
10100101
11100101
11110001
01110001
11011000
00110001
00010101
00000100
11000111
00100011
11000011
00011000
10010110
00000101
10011010
00000111
00010010
10000000
11100010
11101011
00100111
10110010
01110101
00001001
10000011
00101100
00011010
00011011
01101110
01011010
10100000
01010010
00111011
11010110
10110011
00101001
11100011
00101111
10000100
01010011
11010001
00000000
11101101
00100000
11111100
10110001
01011011
01101010
11001011
10111110
00111001
01001010
01001100
01011000
11001111
11010000
11101111
10101010
11111011
01000011
01001101
00110011
10000101
01000101
11111001
00000010
01111111
01010000
00111100
10011111
10101000
01010001
10100011
01000000
10001111
10010010
10011101
00111000
11110101
10111100
10110110
11011010
00100001
00010000
11111111
11110011
11010010
11001101
00001100
00010011
11101100
01011111
10010111
01000100
00010111
11000100
10100111
01111110
00111101
01100100
01011101
00011001
01110011
01100000
10000001
01001111
11011100
00100010
00101010
10010000
10001000
01000110
11101110
10111000
00010100
11011110
01011110
00001011
11011011
11100000
00110010
00111010
00001010
01001001
00000110
00100100
01011100
11000010
11010011
10101100
01100010
10010001
10010101
11100100
01111001
11100111
11001000
00110111
01101101
10001101
11010101
01001110
10101001
01101100
01010110
11110100
11101010
01100101
01111010
10101110
00001000
10111010
01111000
00100101
00101110
00011100
10100110
10110100
11000110
11101000
11011101
01110100
00011111
01001011
10111101
10001011
10001010
01110000
00111110
10110101
01100110
01001000
00000011
11110110
00001110
01100001
00110101
01010111
10111001
10000110
11000001
00011101
10011110
11100001
11111000
10011000
00010001
01101001
11011001
10001110
10010100
10011011
00011110
10000111
11101001
11001110
01010101
00101000
11011111
10001100
10100001
10001001
00001101
10111111
11100110
01000010
01101000
01000001
10011001
00101101
00001111
10110000
01010100
10111011
00010110
/trunk/rtl/cryptopan_unit.vhd
0,0 → 1,220
--
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
use work.cryptopan.all;
 
entity cryptopan_unit is
 
port (
clk : in std_logic;
reset : in std_logic;
ready : out std_logic;
key : in std_logic_vector(255 downto 0);
key_wren : in std_logic;
ip_in : in std_logic_vector(31 downto 0);
ip_wren : in std_logic;
ip_out : out std_logic_vector(31 downto 0);
ip_dv : out std_logic
);
 
end cryptopan_unit;
 
architecture rtl of cryptopan_unit is
 
component aes_encrypt_unit
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
clk : in std_logic;
reset : in std_logic);
end component;
 
signal aes_din, aes_dout : std_logic_vector(127 downto 0);
signal aes_din_wren, aes_dout_dv : std_logic;
signal ready_int : std_logic;
signal m_pad : std_logic_vector(127 downto 0);
 
signal ip_reg : std_logic_vector(31 downto 0);
signal read_ip_reg : std_logic_vector(31 downto 0);
 
type states is (INIT, INITWAIT, IDLE, BUSY);
signal state : states;
 
type read_states is (INIT, IDLE, BUSY);
signal read_state : read_states;
 
type output_states is (IDLE, BUSY);
signal output_state : output_states;
 
-- signal shift_counter : std_logic_vector(31 downto 0);
signal output_counter : std_logic_vector(4 downto 0);
signal first4bytes_pad : std_logic_vector(31 downto 0);
signal first4bytes_input : std_logic_vector(31 downto 0);
 
signal mask_onehot : std_logic_vector(31 downto 0);
signal mask_onehot_inv : std_logic_vector(31 downto 0);
 
signal ip_out_int : std_logic_vector(31 downto 0);
begin
 
mask_onehot_inv <= not mask_onehot;
 
with state select
ready <=
'1' when IDLE,
'0' when others;
 
first4bytes_pad <= m_pad(127 downto 96);
first4bytes_input <= (ip_reg and mask_onehot_inv) or (first4bytes_pad and mask_onehot);
 
 
LOAD_UNIT_LOGIC : process (clk, reset)
begin
if reset = '1' then
state <= INIT;
aes_din_wren <= '0';
aes_din <= (others => '0');
mask_onehot <= (others => '0');
ip_reg <= (others => '0');
elsif clk'event and clk = '1' then
mask_onehot <= (others => '1');
aes_din_wren <= '0';
 
if state = INIT and ready_int = '1' then
aes_din <= key(255 downto 128);
aes_din_wren <= '1';
state <= INITWAIT;
elsif state = INITWAIT and aes_dout_dv = '1' then
state <= IDLE;
elsif state = IDLE and ip_wren = '1' then
state <= BUSY;
ip_reg <= ip_in;
elsif state = BUSY then
 
if mask_onehot(0) = '1' then
aes_din_wren <= '1';
aes_din <= first4bytes_input & m_pad(95 downto 0);
else
state <= IDLE;
end if;
 
mask_onehot(31) <= '0';
for i in 30 downto 0 loop
mask_onehot(i) <= mask_onehot(i+1);
end loop;
 
end if;
 
end if;
end process LOAD_UNIT_LOGIC;
 
READ_UNIT_LOGIC : process (clk, reset)
begin
if reset = '1' then
m_pad <= (others => '0');
 
read_state <= INIT;
ip_out <= (others => '0');
ip_dv <= '0';
output_state <= IDLE;
read_ip_reg <= (others => '0');
output_counter <= (others => '1');
elsif clk'event and clk = '1' then
 
ip_dv <= '0';
if read_state = INIT then
if aes_dout_dv = '1' then
m_pad <= aes_dout;
read_state <= IDLE;
end if;
 
 
elsif read_state = IDLE then
 
if aes_dout_dv = '1' then
if output_counter = "11111" then
read_ip_reg <= ip_reg;
end if;
output_counter <= output_counter - 1;
 
ip_out_int <= ip_out_int(30 downto 0) & aes_dout(127);
end if;
if output_counter = "00000" then
output_state <= BUSY;
end if;
 
end if;
 
if output_state = BUSY then
output_state <= IDLE;
ip_dv <= '1';
ip_out <= ip_out_int xor read_ip_reg;
end if;
 
end if;
end process READ_UNIT_LOGIC;
 
-- OUTPUT_UNIT_LOGIC : process (clk, reset)
-- begin
-- if reset = '1' then
-- ip_out <= (others => '0');
-- ip_dv <= '0';
-- output_state <= IDLE;
-- elsif clk'event and clk = '1' then
 
-- end if;
-- end process OUTPUT_UNIT_LOGIC;
 
AES0 : aes_encrypt_unit
port map (
key_in => key(127 downto 0),
key_wren => key_wren,
ready => ready_int,
data_in => aes_din,
data_wren => aes_din_wren,
data_dv => aes_dout_dv,
data_out => aes_dout,
clk => clk,
reset => reset);
 
 
 
end rtl;
/trunk/rtl/mixcolumns.vhd
0,0 → 1,105
--
-- This file is part of the Crypto-PAn core.
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.cryptopan.all;
 
entity mixcolumns is
 
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
 
in_en : in std_logic;
out_en : out std_logic;
 
clk : in std_logic;
reset : in std_logic
);
 
end mixcolumns;
 
architecture rtl of mixcolumns is
signal reg : s_vector;
signal en_reg : std_logic;
 
function transform(p : std_logic_vector(31 downto 0) ) return std_logic_vector is
variable result : std_logic_vector(7 downto 0);
variable m, n : std_logic_vector(7 downto 0);
begin
if(p(7) = '1') then
m := (p(30 downto 24) & '0') xor "00011011";
else
m := (p(30 downto 24) & '0');
end if;
if(p(7) = '1') then
n := (p(22 downto 16) & '0') xor "00011011" xor p(23 downto 16);
else
n := (p(22 downto 16) & '0') xor p(23 downto 16);
end if;
result := m xor n xor p(15 downto 8) xor p(7 downto 0);
return result;
end function transform;
 
begin
 
REGGEN: process (clk, reset)
begin
if reset = '1' then
reg <= (others => (others => '0'));
en_reg <= '0';
elsif clk'event and clk = '1' then
reg <= bytes_in;
en_reg <= in_en;
end if;
end process REGGEN;
 
out_en <= en_reg;
bytes_out(0) <= transform(reg(0) & reg(4) & reg(8) & reg(12));
bytes_out(1) <= transform(reg(1) & reg(5) & reg(9) & reg(13));
bytes_out(2) <= transform(reg(2) & reg(6) & reg(10) & reg(14));
bytes_out(3) <= transform(reg(3) & reg(7) & reg(11) & reg(15));
 
bytes_out(4) <= transform(reg(4) & reg(8) & reg(12) & reg(0));
bytes_out(5) <= transform(reg(5) & reg(9) & reg(13) & reg(1));
bytes_out(6) <= transform(reg(6) & reg(10) & reg(14) & reg(2));
bytes_out(7) <= transform(reg(7) & reg(11) & reg(15) & reg(3));
 
bytes_out(8) <= transform(reg(8) & reg(12) & reg(0) & reg(4));
bytes_out(9) <= transform(reg(9) & reg(13) & reg(1) & reg(5));
bytes_out(10) <= transform(reg(10) & reg(14) & reg(2) & reg(6));
bytes_out(11) <= transform(reg(11) & reg(15) & reg(3) & reg(7));
 
bytes_out(12) <= transform(reg(12) & reg(0) & reg(4) & reg(8));
bytes_out(13) <= transform(reg(13) & reg(1) & reg(5) & reg(9));
bytes_out(14) <= transform(reg(14) & reg(2) & reg(6) & reg(10));
bytes_out(15) <= transform(reg(15) & reg(3) & reg(7) & reg(11));
 
end rtl;
/trunk/.riviera_project
0,0 → 1,9
[DesignBrowserState]
Current %22cryptopan%22
Properties %22work%22 [ expanded=0 ]
Properties %22work%22%7c%22Design%20Units%22 [ expanded=1 ]
Properties %22work%22%7c%22Source%20Files%22 [ expanded=1 ]
Properties %22work%22%7c%22Verification%20Units%22 [ expanded=1 ]
Properties %2e%2frtl [ expanded=1 ]
Properties %2e%2ftb [ expanded=1 ]
Properties %2fhome%2famb33%2fcryptopan [ expanded=1 ]
/trunk/synth/cryptopan_unit.ucf
0,0 → 1,105
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 4 ns HIGH 50 %;
NET "AES0/clk_counter_c(1)" TNM_NET = "AES0/clk_counter_c(1)";
TIMESPEC "TS_AES0_clk_counter_c_1_" = PERIOD "AES0/clk_counter_c(1)" 16 ns HIGH 50 %;
 
NET "ip_in(31)" LOC="G10";
NET "ip_out(31)" LOC="H10";
NET "ip_in(30)" LOC="D10";
NET "ip_out(30)" LOC="C10";
NET "ip_in(29)" LOC="F10";
NET "ip_out(29)" LOC="F9";
NET "ip_in(28)" LOC="H9";
NET "ip_out(28)" LOC="J9";
NET "ip_in(27)" LOC="F11";
NET "ip_out(27)" LOC="E11";
NET "ip_in(26)" LOC="D9";
NET "ip_out(26)" LOC="E9";
NET "ip_in(25)" LOC="D12";
NET "ip_out(25)" LOC="D11";
NET "ip_in(24)" LOC="C9";
NET "ip_out(24)" LOC="C8";
NET "ip_in(23)" LOC="C13";
NET "ip_out(23)" LOC="C12";
NET "ip_in(22)" LOC="E8";
NET "ip_out(22)" LOC="F8";
NET "ip_in(21)" LOC="J11";
NET "ip_out(21)" LOC="J10";
NET "ip_in(20)" LOC="G8";
NET "ip_out(20)" LOC="H8";
NET "ip_in(19)" LOC="G12";
NET "ip_out(19)" LOC="G11";
NET "ip_in(18)" LOC="J7";
NET "ip_out(18)" LOC="K7";
NET "ip_in(17)" LOC="K11";
NET "ip_out(17)" LOC="L11";
NET "ip_in(16)" LOC="G7";
NET "ip_out(16)" LOC="H7";
NET "ip_in(15)" LOC="J12";
NET "ip_out(15)" LOC="H12";
NET "ip_in(14)" LOC="E7";
NET "ip_out(14)" LOC="E6";
NET "ip_in(13)" LOC="E13";
NET "ip_out(13)" LOC="E12";
NET "ip_in(12)" LOC="K9";
NET "ip_out(12)" LOC="K8";
NET "ip_in(11)" LOC="E14";
NET "ip_out(11)" LOC="D14";
NET "ip_in(10)" LOC="C7";
NET "ip_out(10)" LOC="D7";
NET "ip_in(9)" LOC="C15";
NET "ip_out(9)" LOC="C14";
NET "ip_in(8)" LOC="F6";
NET "ip_out(8)" LOC="G6";
NET "ip_in(7)" LOC="D16";
NET "ip_out(7)" LOC="D15";
NET "ip_in(6)" LOC="D6";
NET "ip_out(6)" LOC="C5";
NET "ip_in(5)" LOC="K13";
NET "ip_out(5)" LOC="K12";
NET "ip_in(5)" LOC="D5";
NET "ip_out(5)" LOC="D4";
NET "ip_in(4)" LOC="M13";
NET "ip_out(4)" LOC="L13";
NET "ip_in(3)" LOC="E4";
NET "ip_out(3)" LOC="E3";
NET "ip_in(2)" LOC="M12";
NET "ip_out(2)" LOC="M11";
NET "ip_in(1)" LOC="C4";
NET "ip_out(1)" LOC="C3";
NET "ip_in(0)" LOC="L9";
NET "ip_out(0)" LOC="L8";
 
 
 
# Start of Constraints extracted by Floorplanner from the Design
INST "AES0/ROUND9" AREA_GROUP = "AG_AES0/ROUND9" ;
AREA_GROUP "AG_AES0/ROUND9" RANGE = SLICE_X60Y219:SLICE_X100Y208 ;
AREA_GROUP "AG_AES0/ROUND9" RANGE = RAMB16_X4Y26:RAMB16_X4Y27, RAMB16_X5Y26:RAMB16_X5Y27, RAMB16_X6Y26:RAMB16_X6Y27, RAMB16_X7Y26:RAMB16_X7Y27 ;
INST "AES0/ROUND_GEN.8.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.8.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.8.ROUND_I" RANGE = SLICE_X60Y207:SLICE_X100Y192 ;
AREA_GROUP "AG_AES0/ROUND_GEN.8.ROUND_I" RANGE = RAMB16_X4Y24:RAMB16_X4Y25, RAMB16_X5Y24:RAMB16_X5Y25, RAMB16_X6Y24:RAMB16_X6Y25, RAMB16_X7Y24:RAMB16_X7Y25 ;
INST "AES0/ROUND_GEN.7.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.7.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.7.ROUND_I" RANGE = SLICE_X60Y191:SLICE_X100Y176 ;
AREA_GROUP "AG_AES0/ROUND_GEN.7.ROUND_I" RANGE = RAMB16_X4Y22:RAMB16_X4Y23, RAMB16_X5Y22:RAMB16_X5Y23, RAMB16_X6Y22:RAMB16_X6Y23, RAMB16_X7Y22:RAMB16_X7Y23 ;
INST "AES0/ROUND_GEN.6.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.6.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.6.ROUND_I" RANGE = SLICE_X60Y175:SLICE_X100Y160 ;
AREA_GROUP "AG_AES0/ROUND_GEN.6.ROUND_I" RANGE = RAMB16_X4Y20:RAMB16_X4Y21, RAMB16_X5Y20:RAMB16_X5Y21, RAMB16_X6Y20:RAMB16_X6Y21, RAMB16_X7Y20:RAMB16_X7Y21 ;
INST "AES0/ROUND_GEN.5.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.5.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.5.ROUND_I" RANGE = SLICE_X60Y159:SLICE_X100Y144 ;
AREA_GROUP "AG_AES0/ROUND_GEN.5.ROUND_I" RANGE = RAMB16_X4Y18:RAMB16_X4Y19, RAMB16_X5Y18:RAMB16_X5Y19, RAMB16_X6Y18:RAMB16_X6Y19, RAMB16_X7Y18:RAMB16_X7Y19 ;
INST "AES0/ROUND_GEN.4.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.4.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.4.ROUND_I" RANGE = SLICE_X60Y143:SLICE_X100Y128 ;
AREA_GROUP "AG_AES0/ROUND_GEN.4.ROUND_I" RANGE = RAMB16_X4Y16:RAMB16_X4Y17, RAMB16_X5Y16:RAMB16_X5Y17, RAMB16_X6Y16:RAMB16_X6Y17, RAMB16_X7Y16:RAMB16_X7Y17 ;
INST "AES0/ROUND_GEN.3.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.3.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.3.ROUND_I" RANGE = SLICE_X60Y127:SLICE_X100Y112 ;
AREA_GROUP "AG_AES0/ROUND_GEN.3.ROUND_I" RANGE = RAMB16_X4Y14:RAMB16_X4Y15, RAMB16_X5Y14:RAMB16_X5Y15, RAMB16_X6Y14:RAMB16_X6Y15, RAMB16_X7Y14:RAMB16_X7Y15 ;
INST "AES0/ROUND_GEN.2.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.2.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.2.ROUND_I" RANGE = SLICE_X60Y111:SLICE_X100Y96 ;
AREA_GROUP "AG_AES0/ROUND_GEN.2.ROUND_I" RANGE = RAMB16_X4Y12:RAMB16_X4Y13, RAMB16_X5Y12:RAMB16_X5Y13, RAMB16_X6Y12:RAMB16_X6Y13, RAMB16_X7Y12:RAMB16_X7Y13 ;
INST "AES0/ROUND_GEN.1.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.1.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.1.ROUND_I" RANGE = SLICE_X60Y95:SLICE_X100Y80 ;
AREA_GROUP "AG_AES0/ROUND_GEN.1.ROUND_I" RANGE = RAMB16_X4Y10:RAMB16_X4Y11, RAMB16_X5Y10:RAMB16_X5Y11, RAMB16_X6Y10:RAMB16_X6Y11, RAMB16_X7Y10:RAMB16_X7Y11 ;
INST "AES0/ROUND_GEN.0.ROUND_I" AREA_GROUP = "AG_AES0/ROUND_GEN.0.ROUND_I" ;
AREA_GROUP "AG_AES0/ROUND_GEN.0.ROUND_I" RANGE = SLICE_X60Y79:SLICE_X100Y64 ;
AREA_GROUP "AG_AES0/ROUND_GEN.0.ROUND_I" RANGE = RAMB16_X4Y8:RAMB16_X4Y9, RAMB16_X5Y8:RAMB16_X5Y9, RAMB16_X6Y8:RAMB16_X6Y9, RAMB16_X7Y8:RAMB16_X7Y9 ;
/trunk/synth/virtex4_timing
0,0 → 1,13
------------------------------------------------------------------------------------------------------
Constraint | Requested | Actual | Logic | Absolute |Number of
| | | Levels | Slack |errors
------------------------------------------------------------------------------------------------------
TS_clk = PERIOD TIMEGRP "clk" 4 ns HIGH 5 | 4.000ns | 3.982ns | 0 | 0.018ns | 0
0% | | | | |
------------------------------------------------------------------------------------------------------
TS_AES0_clk_counter_c_1_ = PERIOD TIMEGRP | 16.000ns | 11.908ns | 2 | 4.092ns | 0
"AES0/clk_counter_c(1)" 16 ns HIGH | | | | |
50% | | | | |
------------------------------------------------------------------------------------------------------
 
All constraints were met.
/trunk/synth/virtex4_area
0,0 → 1,36
Resource Usage Report for cryptopan_unit
 
Mapping to part: xc4vfx60ff1152-11
Cell usage:
FDC 1249 uses
FDCE 1899 uses
FDE 32 uses
FDPE 6 uses
GND 1 use
MUXCY_L 4 uses
MUXF5 6 uses
VCC 1 use
XORCY 4 uses
dual_bram_256x8 82 uses
LUT1 6 uses
LUT2 709 uses
LUT3 980 uses
LUT4 1315 uses
 
I/O ports: 326
I/O primitives: 325
IBUF 291 uses
OBUF 34 uses
 
BUFG 1 use
 
BUFGP 1 use
 
I/O Register bits: 0
Register bits not including I/Os: 3186 (5%)
 
Global Clock Buffers: 2 of 32 (6%)
 
 
Mapping Summary:
Total LUTs: 3010 (5%)
/trunk/tb/aes_encrypt_unit_tb.vhd
0,0 → 1,134
--
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
 
entity aes_encrypt_unit_tb is
end aes_encrypt_unit_tb;
 
architecture tb of aes_encrypt_unit_tb is
 
component aes_encrypt_unit
port (
key_in : in std_logic_vector(127 downto 0);
key_wren : in std_logic;
ready : out std_logic;
data_in : in std_logic_vector(127 downto 0);
data_wren : in std_logic;
data_dv : out std_logic;
data_out : out std_logic_vector(127 downto 0);
clk : in std_logic;
reset : in std_logic);
end component;
signal clk : std_logic;
signal reset : std_logic;
 
signal key_in : std_logic_vector(127 downto 0);
signal key_wren : std_logic;
signal ready : std_logic;
signal data_in : std_logic_vector(127 downto 0);
signal data_wren : std_logic;
signal data_dv : std_logic;
signal data_out : std_logic_vector(127 downto 0);
 
begin
 
CLKGEN: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
 
CRYPT0: aes_encrypt_unit
port map (
key_in => key_in,
key_wren => key_wren,
ready => ready,
data_in => data_in,
data_wren => data_wren,
data_dv => data_dv,
data_out => data_out,
clk => clk,
reset => reset);
 
TESTBENCH: process
begin
reset <= '1';
data_in <= (others => '0');
key_in <= (others => '0');
data_wren <= '0';
key_wren <= '0';
wait for 50 ns;
reset <= '0';
wait for 20 ns;
key_in <= X"2b7e151628aed2a6abf7158809cf4f3c";
key_wren <= '1';
wait for 10 ns;
key_wren <= '0';
 
wait until ready='1';
wait for 40 ns;
 
data_in <= X"3243f6a8885a308d313198a2e0370734";
data_wren <= '1';
wait for 10 ns;
data_in <= X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
wait for 10 ns;
data_in <= X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB";
wait for 10 ns;
data_in <= X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
wait for 10 ns;
data_in <= X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD";
wait for 10 ns;
data_in <= X"3243f6a8885a308d313198a2e0370734";
wait for 10 ns;
data_in <= X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
wait for 10 ns;
data_in <= X"BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB";
wait for 10 ns;
data_in <= X"CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC";
wait for 10 ns;
data_in <= X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD";
wait for 10 ns;
data_in <= X"3243f6a8885a308d313198a2e0370734";
wait for 10 ns;
data_wren <= '0';
data_in <= (others => '0');
wait until data_dv='1';
wait;
end process TESTBENCH;
 
end tb;
/trunk/tb/cryptopan_unit_tb.vhd
0,0 → 1,180
--
-- This file is part of the Crypto-PAn core (www.opencores.org).
--
-- Copyright (c) 2007 The University of Waikato, Hamilton, New Zealand.
-- Authors: Anthony Blake (tonyb33@opencores.org)
--
-- All rights reserved.
--
-- This code has been developed by the University of Waikato WAND
-- research group. For further information please see http://www.wand.net.nz/
--
-- This source file is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with libtrace; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
 
 
entity cryptopan_unit_tb is
 
end cryptopan_unit_tb;
 
architecture tb of cryptopan_unit_tb is
 
component cryptopan_unit
port (
clk : in std_logic;
reset : in std_logic;
ready : out std_logic;
key : in std_logic_vector(255 downto 0);
key_wren : in std_logic;
ip_in : in std_logic_vector(31 downto 0);
ip_wren : in std_logic;
ip_out : out std_logic_vector(31 downto 0);
ip_dv : out std_logic);
end component;
 
signal clk : std_logic;
signal reset : std_logic;
 
signal key : std_logic_vector(255 downto 0);
signal key_wren : std_logic;
signal ready : std_logic;
signal ip_in, ip_out : std_logic_vector(31 downto 0);
signal ip_wren, ip_dv : std_logic;
 
type char_file is file of character;
file bin_file_raw : char_file is in "sim/trace_bin_raw";
file bin_file_anon : char_file is in "sim/trace_bin_anon";
 
signal ip_in_int : std_logic_vector(31 downto 0);
signal ip_out_int : std_logic_vector(31 downto 0);
 
begin
 
CLKGEN : process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
 
DUT : cryptopan_unit
port map (
clk => clk,
reset => reset,
ready => ready,
key => key,
key_wren => key_wren,
ip_in => ip_in,
ip_wren => ip_wren,
ip_out => ip_out,
ip_dv => ip_dv);
 
GEN_IPS : process
variable my_char : character;
begin -- process GEN_IPS
-- file_open(bin_file_raw, "sim/trace_bin_raw", read_mode);
 
ip_in_int <= (others => '0');
ip_wren <= '0';
wait until ready = '1';
wait for 50 ns;
 
while not endfile(bin_file_raw) loop
 
 
read(bin_file_raw, my_char);
ip_in_int(31 downto 24) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_raw, my_char);
ip_in_int(23 downto 16) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_raw, my_char);
ip_in_int(15 downto 8) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_raw, my_char);
ip_in_int(7 downto 0) <= conv_std_logic_vector(character'pos(my_char), 8);
wait for 10 ns;
ip_wren <= '1';
 
wait for 10 ns;
 
ip_wren <= '0';
 
wait until ready = '1';
end loop;
report "TEST COMPLETED" severity note;
 
end process GEN_IPS;
 
IP_OUT_INT_LOGIC : process
variable my_char : character;
begin -- process IP_OUT_INT_LOGIC
--ip_out_int <= (others => '0');
wait until ip_dv = '1';
read(bin_file_anon, my_char);
ip_out_int(31 downto 24) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_anon, my_char);
ip_out_int(23 downto 16) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_anon, my_char);
ip_out_int(15 downto 8) <= conv_std_logic_vector(character'pos(my_char), 8);
read(bin_file_anon, my_char);
ip_out_int(7 downto 0) <= conv_std_logic_vector(character'pos(my_char), 8);
 
end process IP_OUT_INT_LOGIC;
 
DV_LOGIC : process(clk)
variable my_char : character;
begin -- process DV_LOGIC
if clk'event and clk = '1' then
if ip_dv = '1' then
assert ip_out_int = ip_out report "TEST FAILED" severity error;
end if;
end if;
end process DV_LOGIC;
 
 
ip_in <= ip_in_int;
 
TESTBENCH : process
begin
reset <= '1';
-- ip_in <= (others => '0');
key <= (others => '0');
-- ip_wren <= '0';
key_wren <= '0';
wait for 50 ns;
reset <= '0';
wait for 20 ns;
key <= X"d8988f837979652762574c2d2a8422021522178d33a4cf80130a5b1649907d10";
key_wren <= '1';
wait for 10 ns;
key_wren <= '0';
-- wait until ready='1';
-- wait for 40 ns;
-- ip_in <= X"18050050";
-- ip_wren <= '1';
-- wait for 10 ns;
-- ip_wren <= '0';
-- wait until ready='1';
wait;
end process TESTBENCH;
 
 
 
end tb;
/trunk/tb/sbsr_tb.vhd
0,0 → 1,109
library ieee;
use ieee.std_logic_1164.all;
 
use work.cryptopan.all;
 
 
entity sbsr_tb is
end sbsr_tb;
 
 
architecture tb of sbsr_tb is
component subbytesshiftrows
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
clk : in std_logic;
reset : in std_logic);
end component;
 
component mixcolumns
port (
bytes_in : in s_vector;
bytes_out : out s_vector;
clk : in std_logic;
reset : in std_logic);
end component;
signal clk : std_logic;
signal reset : std_logic;
 
signal bytes_in : s_vector;
signal bytes_out : s_vector;
signal mix_bytes_out : s_vector;
begin -- tb
 
CLKGEN: process
begin -- process CLKGEN
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
 
 
SUBBYTESSHIFTROWS0: subbytesshiftrows
port map (
bytes_in => bytes_in,
bytes_out => bytes_out,
clk => clk,
reset => reset);
MIX0: mixcolumns
port map (
bytes_in => bytes_out,
bytes_out => mix_bytes_out,
clk => clk,
reset => reset);
 
TB: process
begin -- process TB
reset <= '1';
wait for 55 ns;
 
reset <= '0';
 
wait for 20 ns;
bytes_in(0) <= X"19";
bytes_in(1) <= X"A0";
bytes_in(2) <= X"9A";
bytes_in(3) <= X"E9";
bytes_in(4) <= X"3D";
bytes_in(5) <= X"F4";
bytes_in(6) <= X"C6";
bytes_in(7) <= X"F8";
bytes_in(8) <= X"E3";
bytes_in(9) <= X"E2";
bytes_in(10) <= X"8D";
bytes_in(11) <= X"48";
bytes_in(12) <= X"BE";
bytes_in(13) <= X"2B";
bytes_in(14) <= X"2A";
bytes_in(15) <= X"08";
wait for 10 ns;
bytes_in(0) <= X"A4";
bytes_in(1) <= X"68";
bytes_in(2) <= X"6B";
bytes_in(3) <= X"02";
bytes_in(4) <= X"9C";
bytes_in(5) <= X"9F";
bytes_in(6) <= X"5B";
bytes_in(7) <= X"6A";
bytes_in(8) <= X"7F";
bytes_in(9) <= X"35";
bytes_in(10) <= X"EA";
bytes_in(11) <= X"50";
bytes_in(12) <= X"F2";
bytes_in(13) <= X"2B";
bytes_in(14) <= X"43";
bytes_in(15) <= X"49";
wait for 10 ns;
 
wait;
end process TB;
end tb;
/trunk/COPYING
0,0 → 1,340
GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
 
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
 
Preamble
 
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Library General Public License instead.) You can apply it to
your programs, too.
 
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
in new free programs; and that you know you can do these things.
 
To protect your rights, we need to make restrictions that forbid
anyone to deny you these rights or to ask you to surrender the rights.
These restrictions translate to certain responsibilities for you if you
distribute copies of the software, or if you modify it.
 
For example, if you distribute copies of such a program, whether
gratis or for a fee, you must give the recipients all the rights that
you have. You must make sure that they, too, receive or can get the
source code. And you must show them these terms so they know their
rights.
 
We protect your rights with two steps: (1) copyright the software, and
(2) offer you this license which gives you legal permission to copy,
distribute and/or modify the software.
 
Also, for each author's protection and ours, we want to make certain
that everyone understands that there is no warranty for this free
software. If the software is modified by someone else and passed on, we
want its recipients to know that what they have is not the original, so
that any problems introduced by others will not reflect on the original
authors' reputations.
 
Finally, any free program is threatened constantly by software
patents. We wish to avoid the danger that redistributors of a free
program will individually obtain patent licenses, in effect making the
program proprietary. To prevent this, we have made it clear that any
patent must be licensed for everyone's free use or not licensed at all.
 
The precise terms and conditions for copying, distribution and
modification follow.
GNU GENERAL PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
 
0. This License applies to any program or other work which contains
a notice placed by the copyright holder saying it may be distributed
under the terms of this General Public License. The "Program", below,
refers to any such program or work, and a "work based on the Program"
means either the Program or any derivative work under copyright law:
that is to say, a work containing the Program or a portion of it,
either verbatim or with modifications and/or translated into another
language. (Hereinafter, translation is included without limitation in
the term "modification".) Each licensee is addressed as "you".
 
Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope. The act of
running the Program is not restricted, and the output from the Program
is covered only if its contents constitute a work based on the
Program (independent of having been made by running the Program).
Whether that is true depends on what the Program does.
 
1. You may copy and distribute verbatim copies of the Program's
source code as you receive it, in any medium, provided that you
conspicuously and appropriately publish on each copy an appropriate
copyright notice and disclaimer of warranty; keep intact all the
notices that refer to this License and to the absence of any warranty;
and give any other recipients of the Program a copy of this License
along with the Program.
 
You may charge a fee for the physical act of transferring a copy, and
you may at your option offer warranty protection in exchange for a fee.
 
2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy and
distribute such modifications or work under the terms of Section 1
above, provided that you also meet all of these conditions:
 
a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.
 
b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any
part thereof, to be licensed as a whole at no charge to all third
parties under the terms of this License.
 
c) If the modified program normally reads commands interactively
when run, you must cause it, when started running for such
interactive use in the most ordinary way, to print or display an
announcement including an appropriate copyright notice and a
notice that there is no warranty (or else, saying that you provide
a warranty) and that users may redistribute the program under
these conditions, and telling the user how to view a copy of this
License. (Exception: if the Program itself is interactive but
does not normally print such an announcement, your work based on
the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
and can be reasonably considered independent and separate works in
themselves, then this License, and its terms, do not apply to those
sections when you distribute them as separate works. But when you
distribute the same sections as part of a whole which is a work based
on the Program, the distribution of the whole must be on the terms of
this License, whose permissions for other licensees extend to the
entire whole, and thus to each and every part regardless of who wrote it.
 
Thus, it is not the intent of this section to claim rights or contest
your rights to work written entirely by you; rather, the intent is to
exercise the right to control the distribution of derivative or
collective works based on the Program.
 
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
a storage or distribution medium does not bring the other work under
the scope of this License.
 
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
 
a) Accompany it with the complete corresponding machine-readable
source code, which must be distributed under the terms of Sections
1 and 2 above on a medium customarily used for software interchange; or,
 
b) Accompany it with a written offer, valid for at least three
years, to give any third party, for a charge no more than your
cost of physically performing source distribution, a complete
machine-readable copy of the corresponding source code, to be
distributed under the terms of Sections 1 and 2 above on a medium
customarily used for software interchange; or,
 
c) Accompany it with the information you received as to the offer
to distribute corresponding source code. (This alternative is
allowed only for noncommercial distribution and only if you
received the program in object code or executable form with such
an offer, in accord with Subsection b above.)
 
The source code for a work means the preferred form of the work for
making modifications to it. For an executable work, complete source
code means all the source code for all modules it contains, plus any
associated interface definition files, plus the scripts used to
control compilation and installation of the executable. However, as a
special exception, the source code distributed need not include
anything that is normally distributed (in either source or binary
form) with the major components (compiler, kernel, and so on) of the
operating system on which the executable runs, unless that component
itself accompanies the executable.
 
If distribution of executable or object code is made by offering
access to copy from a designated place, then offering equivalent
access to copy the source code from the same place counts as
distribution of the source code, even though third parties are not
compelled to copy the source along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program
except as expressly provided under this License. Any attempt
otherwise to copy, modify, sublicense or distribute the Program is
void, and will automatically terminate your rights under this License.
However, parties who have received copies, or rights, from you under
this License will not have their licenses terminated so long as such
parties remain in full compliance.
 
5. You are not required to accept this License, since you have not
signed it. However, nothing else grants you permission to modify or
distribute the Program or its derivative works. These actions are
prohibited by law if you do not accept this License. Therefore, by
modifying or distributing the Program (or any work based on the
Program), you indicate your acceptance of this License to do so, and
all its terms and conditions for copying, distributing or modifying
the Program or works based on it.
 
6. Each time you redistribute the Program (or any work based on the
Program), the recipient automatically receives a license from the
original licensor to copy, distribute or modify the Program subject to
these terms and conditions. You may not impose any further
restrictions on the recipients' exercise of the rights granted herein.
You are not responsible for enforcing compliance by third parties to
this License.
 
7. If, as a consequence of a court judgment or allegation of patent
infringement or for any other reason (not limited to patent issues),
conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot
distribute so as to satisfy simultaneously your obligations under this
License and any other pertinent obligations, then as a consequence you
may not distribute the Program at all. For example, if a patent
license would not permit royalty-free redistribution of the Program by
all those who receive copies directly or indirectly through you, then
the only way you could satisfy both it and this License would be to
refrain entirely from distribution of the Program.
 
If any portion of this section is held invalid or unenforceable under
any particular circumstance, the balance of the section is intended to
apply and the section as a whole is intended to apply in other
circumstances.
 
It is not the purpose of this section to induce you to infringe any
patents or other property right claims or to contest validity of any
such claims; this section has the sole purpose of protecting the
integrity of the free software distribution system, which is
implemented by public license practices. Many people have made
generous contributions to the wide range of software distributed
through that system in reliance on consistent application of that
system; it is up to the author/donor to decide if he or she is willing
to distribute software through any other system and a licensee cannot
impose that choice.
 
This section is intended to make thoroughly clear what is believed to
be a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in
certain countries either by patents or by copyrighted interfaces, the
original copyright holder who places the Program under this License
may add an explicit geographical distribution limitation excluding
those countries, so that distribution is permitted only in or among
countries not thus excluded. In such case, this License incorporates
the limitation as if written in the body of this License.
 
9. The Free Software Foundation may publish revised and/or new versions
of the General Public License from time to time. Such new versions will
be similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
 
Each version is given a distinguishing version number. If the Program
specifies a version number of this License which applies to it and "any
later version", you have the option of following the terms and conditions
either of that version or of any later version published by the Free
Software Foundation. If the Program does not specify a version number of
this License, you may choose any version ever published by the Free Software
Foundation.
 
10. If you wish to incorporate parts of the Program into other free
programs whose distribution conditions are different, write to the author
to ask for permission. For software which is copyrighted by the Free
Software Foundation, write to the Free Software Foundation; we sometimes
make exceptions for this. Our decision will be guided by the two goals
of preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
 
NO WARRANTY
 
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
REPAIR OR CORRECTION.
 
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
 
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
 
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it
free software which everyone can redistribute and change under these terms.
 
To do so, attach the following notices to the program. It is safest
to attach them to the start of each source file to most effectively
convey the exclusion of warranty; and each file should have at least
the "copyright" line and a pointer to where the full notice is found.
 
<one line to give the program's name and a brief idea of what it does.>
Copyright (C) 19yy <name of author>
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
 
Also add information on how to contact you by electronic and paper mail.
 
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
 
Gnomovision version 69, Copyright (C) 19yy name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
 
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
 
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
 
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
 
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
 
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Library General
Public License instead of this License.
/trunk/sim/trace_bin_raw
0,0 → 1,8
+Ͳ&CkMX&CDͲ&C  @vȫe ! ͼͼؔϼ-@'ߍl#ٲʈOe +?d$ʈ^,Oeʈ @"u̸ \ No newline at end of file
/trunk/sim/trace_bin_anon
0,0 → 1,2
 
 
/trunk/sim/waveform.vcd
0,0 → 1,27
$version
Export to VCD from ASDB format v0.8.275
$end
 
$date
Wed Feb 14 16:42:56 2007
$end
 
$timescale
1 ps
$end
 
$scope module top $end
$scope module DUT $end
$var wire 32 ! first4bytes_pad $end
$upscope $end
$upscope $end
 
$enddefinitions $end
 
#0
$dumpvars
b0 !
$end
#1990000
b10001101010100010001010010010110 !
#10000000
/trunk/sim/sample_trace_raw
0,0 → 1,100
24.5.0.80
24.13.62.231
208.234.120.210
209.238.72.3
192.102.249.13
24.5.0.80
24.5.0.80
24.0.250.221
207.105.49.5
209.68.60.238
207.135.65.238
198.51.77.238
24.5.0.80
24.5.0.80
192.215.32.125
129.118.74.4
192.233.80.103
202.49.198.20
212.146.8.236
209.12.231.7
141.233.145.108
63.195.241.44
24.5.0.80
24.5.0.80
192.41.57.43
198.26.132.101
63.14.55.111
205.245.121.43
165.247.96.84
198.36.213.5
198.26.132.101
208.52.56.122
207.155.9.214
207.155.9.214
141.223.7.43
209.85.249.6
212.204.172.118
209.246.74.109
212.120.124.31
192.102.249.13
24.14.213.138
216.184.159.48
141.233.145.108
216.254.18.172
212.206.130.201
192.102.249.13
152.163.225.39
216.157.30.252
24.7.198.88
128.11.68.132
212.186.227.154
198.200.171.101
203.12.160.252
199.217.79.101
204.29.20.4
192.102.249.13
199.217.79.101
216.157.30.252
208.147.89.59
63.97.7.140
207.25.71.27
63.97.7.140
192.102.249.13
205.178.38.67
166.107.77.190
4.3.88.225
38.15.67.68
205.178.38.67
203.12.160.252
204.29.20.4
203.12.160.252
203.12.160.252
64.14.118.196
198.200.171.101
203.12.160.252
207.33.151.131
203.12.160.252
205.188.147.153
205.188.248.25
216.148.237.145
207.188.7.45
64.39.15.238
193.150.244.223
141.233.145.108
216.35.217.178
156.29.3.236
204.202.136.230
208.28.185.184
199.217.79.101
216.227.10.221
195.205.63.100
198.36.213.5
204.202.136.230
24.94.26.44
199.217.79.101
130.132.252.244
204.202.136.230
216.32.132.250
64.34.154.117
204.184.162.189
/trunk/sim/sample_trace_anon
0,0 → 1,100
100.9.15.210
100.2.192.247
227.154.67.17
226.6.119.243
252.138.62.131
100.9.15.210
100.9.15.210
100.15.198.226
241.118.205.138
226.184.220.233
241.202.129.222
249.18.186.254
100.9.15.210
100.9.15.210
252.43.47.189
134.136.186.123
252.25.108.8
245.206.7.234
228.19.4.234
226.243.167.8
141.129.237.235
95.179.238.44
100.9.15.210
100.9.15.210
252.222.221.184
249.36.123.202
95.9.215.7
242.21.121.163
162.9.99.234
249.7.21.132
249.36.123.202
227.8.63.165
241.220.250.22
241.220.250.22
141.167.8.160
226.170.70.6
228.71.195.169
226.22.124.76
228.135.163.231
252.138.62.131
100.1.42.141
235.96.225.78
141.129.237.235
235.7.16.162
228.69.242.193
252.138.62.131
151.140.114.167
235.89.31.26
100.10.6.25
135.242.180.132
228.59.98.98
249.199.68.213
244.248.163.4
248.38.184.213
243.33.20.123
252.138.62.131
248.38.184.213
235.89.31.26
227.237.98.191
95.97.9.123
241.33.119.156
95.97.9.123
252.138.62.131
242.108.198.51
160.132.178.185
124.60.155.63
64.3.66.187
242.108.198.51
244.248.163.4
243.33.20.123
244.248.163.4
244.248.163.4
0.255.183.58
249.199.68.213
244.248.163.4
241.1.233.131
244.248.163.4
242.96.16.101
242.96.88.27
235.84.194.111
241.255.249.220
0.219.7.41
253.169.52.216
141.129.237.235
235.195.157.81
147.225.12.42
243.178.4.198
227.39.94.90
248.38.184.213
235.28.253.36
255.186.223.5
249.7.21.132
243.178.4.198
100.88.228.35
248.38.184.213
133.68.164.234
243.178.4.198
235.192.139.38
0.221.154.117
243.192.77.90
/trunk/sim/trace_hex_raw
0,0 → 1,100
18 05 00 50
18 0d 3e e7
d0 ea 78 d2
d1 ee 48 03
c0 66 f9 0d
18 05 00 50
18 05 00 50
18 00 fa dd
cf 69 31 05
d1 44 3c ee
cf 87 41 ee
c6 33 4d ee
18 05 00 50
18 05 00 50
c0 d7 20 7d
81 76 4a 04
c0 e9 50 67
ca 31 c6 14
d4 92 08 ec
d1 0c e7 07
8d e9 91 6c
3f c3 f1 2c
18 05 00 50
18 05 00 50
c0 29 39 2b
c6 1a 84 65
3f 0e 37 6f
cd f5 79 2b
a5 f7 60 54
c6 24 d5 05
c6 1a 84 65
d0 34 38 7a
cf 9b 09 d6
cf 9b 09 d6
8d df 07 2b
d1 55 f9 06
d4 cc ac 76
d1 f6 4a 6d
d4 78 7c 1f
c0 66 f9 0d
18 0e d5 8a
d8 b8 9f 30
8d e9 91 6c
d8 fe 12 ac
d4 ce 82 c9
c0 66 f9 0d
98 a3 e1 27
d8 9d 1e fc
18 07 c6 58
80 0b 44 84
d4 ba e3 9a
c6 c8 ab 65
cb 0c a0 fc
c7 d9 4f 65
cc 1d 14 04
c0 66 f9 0d
c7 d9 4f 65
d8 9d 1e fc
d0 93 59 3b
3f 61 07 8c
cf 19 47 1b
3f 61 07 8c
c0 66 f9 0d
cd b2 26 43
a6 6b 4d be
04 03 58 e1
26 0f 43 44
cd b2 26 43
cb 0c a0 fc
cc 1d 14 04
cb 0c a0 fc
cb 0c a0 fc
40 0e 76 c4
c6 c8 ab 65
cb 0c a0 fc
cf 21 97 83
cb 0c a0 fc
cd bc 93 99
cd bc f8 19
d8 94 ed 91
cf bc 07 2d
40 27 0f ee
c1 96 f4 df
8d e9 91 6c
d8 23 d9 b2
9c 1d 03 ec
cc ca 88 e6
d0 1c b9 b8
c7 d9 4f 65
d8 e3 0a dd
c3 cd 3f 64
c6 24 d5 05
cc ca 88 e6
18 5e 1a 2c
c7 d9 4f 65
82 84 fc f4
cc ca 88 e6
d8 20 84 fa
40 22 9a 75
cc b8 a2 bd
/trunk/sim/trace_hex_anon
0,0 → 1,100
64 09 0f d2
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/trunk/cryptopan.prj
0,0 → 1,68
#-- Synplicity, Inc.
#-- Version Synplify Pro 8.6.2
#-- Project file /home/amb33/cryptopan/cryptopan.prj
#-- Written on Thu Feb 15 11:59:26 2007
 
 
#add_file options
add_file -vhdl -lib work "rtl/dual_bram_256x8.vhd"
add_file -vhdl -lib work "rtl/cryptopan_package.vhd"
add_file -vhdl -lib work "rtl/sbox.vhd"
add_file -vhdl -lib work "rtl/subbytesshiftrows.vhd"
add_file -vhdl -lib work "rtl/mixcolumns.vhd"
add_file -vhdl -lib work "rtl/round_unit.vhd"
add_file -vhdl -lib work "rtl/aes_encrypt_unit.vhd"
add_file -vhdl -lib work "rtl/cryptopan_unit.vhd"
 
 
#implementation: "rev_1"
impl -add rev_1 -type fpga
 
#device options
set_option -technology VIRTEX4
set_option -part XC4VFX60
set_option -package FF1152
set_option -speed_grade -11
 
#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
 
#map options
set_option -frequency 250.000
set_option -run_prop_extract 1
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -modular 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fixgatedclocks 0
 
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
 
#VIF options
set_option -write_vif 1
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_file "rev_1/cryptopan_unit.edf"
 
#
#implementation attributes
 
set_option -vlog_std v2001
set_option -project_relative_includes 1
 
#par_1 attributes
set_option -job par_1 -add par
set_option -job par_1 -option run_backannotation 0
impl -active "rev_1"
/trunk/README
0,0 → 1,93
 
 
Crypto-PAn core
---------------
http://www.opencores.org/projects.cgi/web/cryptopan_core/
 
 
1. Introduction
---------------
This project is a hardware implementation of the Crypto-PAn technique for
cryptography based prefix preserving anonymization of IP addresses, described in
[1]. A highly pipelined implementation of the AES cipher (Rijndael) [2] is used
as the underlying pseudorandom function.
 
For every bit of the input IP address, a 128-bit AES block encrypt is
required. To be capable of high line rates, a fully pipelined AES engine
capable of 32Gbit/s throughput on a Xilinx Virtex-4 FPGA was implemented.
 
The AES engine has a few options for the implementation of the S-boxes, which
affects area and timing performance. It is possible to use a logic
implementation by setting the 'use_bram' constant in 'cryptopan_package' to
'false' and 'syn_romstyle' attribute in 'sbox' to 'logic'. If 'syn_romstyle'
isn't set then block rams may be inferred. Alternatively, if
block rams are present, as in the Xilinx Virtex FPGA's, eight dual port
18Kbit B-RAMs may be used as ROM's by setting 'use_bram' to 'true'.
 
2. Simulation/Synthesis results
-------------------------------
This core has been simulated using Aldec Riviera 200602, using a compiled
version of the XilinxCoreLib from Xilinx ISE 8.2.
 
Synthesis for the Virtex-4 FX60 FPGA was carried out using Synplicity Synplify
Pro, and Xilinx ISE 8.2 for map, floorplanning, and place & route. To meet
timing at 250MHz floorplanning constraints were required. The constraints
used for the FX60 part are included in the synth directory as an example.
3. Files
--------
README This file.
COPYING GNU General public license.
 
rtl/cryptopan_package.vhd A package which provides some global functions,
types and constants.
rtl/mixcolumns.vhd Performs the 'Mix Columns' step of the Rijndael
cipher.
rtl/subbytesshiftrows.vhd Performs the 'Sub bytes' and 'Shift rows' steps of
the Rijndael cipher.
rtl/round_unit.vhd Implements the transformations for a whole round
of the Rijndael cipher.
rtl/sbox.vhd The Rijndael S-box.
rtl/aes_encrypt_unit.vhd A fully pipelined implementation of AES, using
128-bit keys and blocks. Supports online loading
of keys.
rtl/cryptopan_unit.vhd Uses aes_encrypt_unit to perform the Crypto-PAn
technique on IP adresses.
rtl/sbox.coe Coefficiants file for S-Box ROM.
rtl/dual_bram_256x8.vhd Memory init file for dual block ram as in Virtex
FPGAs.
 
tb/sbsr_tb.vhd Testbench for the subbytesshiftrows unit.
tb/cryptopan_unit_tb.vhd Testbench for the cryptopan_unit.
tb/aes_encrypt_unit_tb.vhd Testbench for the aes_encrypt_unit.
 
synth/virtex4_area Area usage information for the Xilinx V4 FX60.
synth/virtex4_timing Timing report for the Xilinx V4 FX60.
synth/cryptopan_unit.ucf Timing and floorplan constraints Xilinx V4 FX60 to
run at 250MHz. This gives the AES engine a
throughput of 32Gbit/s.
sim/sample_trace_raw Test vectors from C++ implementation by Jinliang
Fan.
sim/sample_trace_anon Anonymized output from test vectors.
sim/trace_raw_bin Test vectors from C++ implementation by Jinliang
Fan in binary format for easy testbenching.
sim/trace_anon_bin Anonymized output from test vectors in binary
format for easy testbenching.
sim/waveform.vcd Waveform showing initialization and then
anonymization of a stream of IP addresses.
4. References
-------------
[1] J. Fan, J. Xu, M. H. Ammar, S. B. Moon, "Prefix-preserving IP address
anonymization: measurement-based security evaluation and a new
cryptography-based scheme", Computer Networks, Volume 46, Issue 2, 7
October 2004, Pages 253-272, Elsevier
[2] J.Daemen, V. Rijmen, "AES proposal: Rijndael", Technical report, Computer
Security Resource Center, National Institute of Standards and
Technology, February 2001
 
5. Contact
----------
Please contact Anthony Blake (tonyb33@opencores.org) if you have any questions
about the core. Your comments are highly appreciated.

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