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Rev 17 → Rev 18

/tags/arelease/HashChain.vhd File deleted \ No newline at end of file
/trunk/search.vhd File deleted \ No newline at end of file
/trunk/HashChain.vhd File deleted
/trunk/hashkey.vhd File deleted \ No newline at end of file
/trunk/.cvspass File deleted
/deflatecore/trunk/search.vhd
0,0 → 1,245
--------------------------------------------------------------------------------
-- Create Date: Open source, from 12c core hosted at www.opencores.org
-- Design Name:
-- Module Name: Log function base 2
-- Project Name: Deflate
-- Target Device:
-- Dependencies:
--
-- Revision: NA
-- Additional Comments:
-- Use this to convert the memeory lengths to the 2^x values
-- to dynamically assign the widths of the address
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
--Function to find the log of a number
--Is used to convert the addresses
package mat is
function log2(v: in natural) return natural;
end package mat;
 
--Function definition
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
 
package body mat is
 
function log2(v: in natural) return natural is
variable n: natural;
variable logn: natural;
begin
n := 1;
for i in 0 to 128 loop
logn := i;
exit when (n>=v);
n := n * 2;
end loop;
return logn;
end function log2;
end package body mat;
--End of the package
 
 
 
 
--------------------------------------------------------------------------------
-- Create Date: 17:24:38 20/05/2006
-- Design Name:
-- Module Name:
-- Project Name: Deflate
-- Target Device:
-- Dependencies: hahskey.vhdl
--
-- Revision:
-- Revision 0.50 - Works but not optimised
-- Additional Comments:
-- This componenet controls the data input and stores the data alongwith
-- the source in 32k buffers ,
-- It recieves the data directly and then on finding a minimum match
-- Drives its match output high along with the match address on the address output
-- and the current offset on the next clock cycle
-- waits for the next +ve edge on the Active data input
-- to go high before resuming, the output/ input is +ve edge triggered
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mat.all;
 
entity input_process is
Generic
(
-- Number of bits in the key
Hash_Width : natural := 32;
-- Data bus width
Data_Width : natural := 8;
-- Buffer allocated to the hash table and the source buffer = 32k tables
-- The key buffer has to be equal to the Hash_Width above and
-- the source buffer of Dat width
-- Start address for the memory bank at which the hash keys need to be stored
-- The end address is calculated by adding the length of the table to that address
Length_of_Table : natural := 32768
);
Port
(
--Outputs to read/write the key values.
hash_tbl_dat : inout std_logic_vector ( Hash_Width - 1 downto 0);
--Port to read/write data values
source_buff_dat : inout std_logic_vector ( Data_Width - 1 downto 0);
-- Matching 4 bytes fond for the last 4 inputs
Match,
-- Ready for crunching
Ready,
-- The sync signals to the memory, read write operations
-- done simultaneously on both memry banks
-- The design will currently work with SRAM and will need a wrapper to
-- work with DRAM
-- Active data on output
Act_data_out,
--Read or write operation 0 = read, 1 = write
RW : out bit ;
-- Current address in buffers
Curr_addres : out std_logic_vector (log2 ( Length_of_Table ) - 1 downto 0);
--******
--Input signals
--Data in
source_dat : inout std_logic_vector ( Data_Width - 1 downto 0);
-- Input Data Clock
Act_dat,
-- Clock
Src_clk,
-- Reset
Reset : in bit
);
end input_process;
 
architecture mealy_machine of input_process is
component hash_key is
generic
(
hash_width: natural := 32;
data_width: natural := 8);
port
(
data_in: in std_logic_vector(data_width -1 downto 0);
hash_out: out std_logic_vector (hash_width -1 downto 0);
Clock,
reset,
start : in bit;
ready,
busy: out bit);
end component;
-- Buffer address start for the key table
Signal key_address,
buffer_address: std_logic_vector (log2 ( Length_of_Table ) - 1 downto 0);
-- Accept a 32 bit hash input
signal hg1: std_logic_vector ( (Hash_Width -1) downto 0);
-- 8 bit io buffer
signal Buffer_1 : std_logic_vector (Data_Width-1 downto 0);
--Component signals from the key algorithm
signal Algo_start,
Algo_clk,
Algo_rst,
Algo_op,
Algo_bsy, -- Algorithm sync aignals
Search_done,
Busy,
red_rst,
red_opr,
val_match: bit := '0'; --Internal sync sgnals
signal mode,
store_count :integer;
 
begin
 
--Unlike the sub components this module has a slightly complex reset cycle
--It resets the offset counters to 0, uses the next 7 clock cyces to read the
--start addresses for the data and key buffer
 
resetter: process (Src_Clk)
variable tmp: integer;
variable red: bit :='0';
Begin
if Src_Clk'event and Src_Clk = '1' then
if mode /= 0 then
red_rst <= '0';
tmp := 0;
else
case tmp is
when 0 =>
buffer_address (7 downto 0) <= source_dat;
when 1 =>
buffer_address (14 downto 8) <= source_dat (6 downto 0);
when 2 =>
key_address (7 downto 0) <= source_dat;
when 3 =>
key_address (14 downto 8) <= source_dat (6 downto 0);
when 4 =>
red_rst <= '1';
when others =>
red_rst <= '0';
end case;
end if;
end if;
end process resetter;
 
--The main input mealy machine is defined below
-- It has 6 states of operation
-- Mode 0 : Reset
-- Mode 1 : Wait
-- Mode 2 : Active data input generationg a key for it and the last 3 bytes
-- Mode 3 : Storing the key and the input data
-- Mode 4 : Searching the hash buffer for a 4 byte match
-- Mode 5 : Match found, on the next clock cycle output current buffer offet
-- and on the second clock cycle output the match offset
input_control : process (Act_dat, Src_Clk, Reset )
begin
--+ Ve edge triggered
if Src_Clk'event and Src_Clk = '1' then
-- Mealy machine
If Reset = '1' or ( mode = 0 and red_rst ='0' ) then
mode <= 0;
elsif mode < 2 and Act_dat = '1' then
mode <= 2;
elsif mode = 2 and Algo_bsy = '0' and store_count < 3 then
mode <= 3;
elsif mode = 2 and Algo_bsy = '0' then
mode <= 4;
elsif mode = 4 and Search_done = '1' and val_match = '1' then
mode <= 5;
elsif mode = 4 and Search_done = '1' then
mode <= 3;
elsif ( mode = 5 or mode = 3 ) and Busy = '0' then
mode <= 1;
else
mode <= mode;
end if;
end if;
end process input_control;
--************************************************
-- Algorithm component addition
Key_Gen: hash_key port map
(
data_in => Buffer_1,
hash_out => hg1,
Clock => Algo_clk,
reset => Algo_rst,
start => Algo_start,
ready => Algo_op,
busy => Algo_bsy
);
-- ************************************************
Ready <= red_rst or red_opr;
end mealy_machine;
/deflatecore/trunk/hashkey.vhd
0,0 → 1,168
--------------------------------------------------------------------------------
-- Create Date: 15:24:38 11/05/2006
-- Design Name:
-- Module Name: Hash key
-- Project Name: Deflate
-- Target Device:
-- Dependencies: Hashchain.vhdl
--
-- Revision:
-- Revision 0.50 - Works but not optimised
-- Additional Comments:
-- A wrapper for the DJB2 algorithm has a 3 byte buffer and uses an extra input byte generate
-- to generate 4 byte hash keys
--
--------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mat.all;
use work.all;
 
entity hash_key is
--generic definitions, data bus widths.
generic
(
hash_width: natural := 32;
data_width: natural := 8);
port
(
data_in: in std_logic_vector(data_width -1 downto 0);
hash_out: out std_logic_vector (hash_width -1 downto 0);
Clock,
reset,
start : in bit;
ready, -- Not used
busy: out bit);
end hash_key;
 
architecture genhash of hash_key is
component HashChain
Generic (
Data_Width : natural := 8; -- Data Bus width
Hash_Width : natural := 32 -- Width of the hash key generated
);
Port(
Hash_o : out std_logic_vector (Hash_Width - 1 downto 0); -- Hash key
Data_in : in std_logic_vector (Data_Width -1 downto 0); -- Data input from byte stream
Busy, -- Busy
Done: out bit; -- Key generated
Clock, -- Clock
Reset, -- Reset
Start, -- Start the hash key generation
O_E : in bit -- Output Enable
);
end component;
 
signal hg1: std_logic_vector ( (Hash_Width -1) downto 0); -- Accept a 32 bit hash input
signal Datain, Buffer_1, Buffer_2, Buffer_3 : std_logic_vector (Data_Width-1 downto 0); -- 8 bit io buffers
signal Algo_start, Algo_clk,Algo_rst,Algo_op, Algo_bsy, Key_done: bit; -- Algorithm interface aignals
signal mode, buff_count, proc_count :integer;
 
begin
glink:HashChain port map (Hash_O => hg1,
Data_in => Datain,
Clock => Algo_clk,
Reset => Algo_rst,
Start => Algo_start,
O_E => Algo_op,
Busy => Algo_bsy,
Done => Key_done);
-- 3 byte input buffer
-- Stores the last 3 bytes used to generate a hash key to keep the hash keys current
-- The hash algorightm is reset after every 4 byte key is generated
-- to ensure that the matches are of 4 byte lengths
Buffer_1 <= X"00" when mode = 0 else
Buffer_2 when mode = 2 else
Buffer_1;
 
Buffer_2 <= X"00" when mode = 0 else
Buffer_3 when mode = 2 else
Buffer_2;
 
Buffer_3 <= X"00" when mode = 0 else
Data_in when mode = 2 else
Buffer_3;
 
--Common Clock
Algo_clk <= Clock;
 
-- Reset the hash algorithm when reset
Algo_rst <= '1' when mode = 0 or mode = 1else
'0';
 
--Sync signals
busy <= '1' when mode > 1 else
'0';
 
--Send a start for every input byte.
Algo_start <= '1' when mode = 2 and buff_count = 3 else -- the 3 byte buffer is empty
'1' when mode = 4 else -- 3 byte buffer is full and one byte has been processed
'0';
 
-- 4 bytes sent one after the other to the hashing algorithm
Datain <= X"00" when mode = 0 or mode = 1 else
Buffer_1 when mode = 2 and buff_count = 3 else
Buffer_1 when mode = 4 and buff_count = 3 and proc_count = 1 else
Buffer_2 when mode = 4 and buff_count = 3 and proc_count = 2 else
Buffer_3 when mode = 4 and buff_count = 3 and proc_count = 3 else
X"00";
 
-- Enabling hash algo output
Algo_op <= '1' when proc_count > 2 else
'0';
 
--Buffer counter
buffer_counter: process (mode)
begin
if mode = 0 then
buff_count <= 0; -- Reset
elsif mode = 2 and buff_count < 3 then
buff_count <= buff_count + 1; -- 1 byte added to buffer
else
buff_count <= buff_count; -- BUffer is full keep the buffered values and the count
end if;
end process buffer_counter;
 
-- Procesed bytes counter
processed_counter: process (mode)
begin
if (mode = 2 and buff_count = 3) or mode = 4 then
proc_count <= proc_count + 1 ;
elsif mode = 3 then
proc_count <= proc_count;
else
proc_count <= 0;
end if;
end process processed_counter;
 
 
-- mealy machine, sends 4 bytes sequentially to the hashing algorithm
-- Waits for the buffer to get filled, on the first +ve clock edge afer the start input
-- is made 1 it sends the bytes to the DJB algorithm.
 
mealy_mach: process (Clock, Reset, Start)
Begin
-- +ve clock
if Clock'event and Clock = '1' then
if Reset = '1' then -- Reset
mode <= 0;
--Start either fill the buffer or Process the first byte in buffer
elsif Start = '1' and mode < 2 then
mode <= 2;
-- Buffer is still processing first byte
-- wait while algorithm finishes generating hash
elsif (mode = 2 and buff_count = 3) or (mode > 1 and Algo_bsy = '1') then
mode <= 3;
-- To hash the next 3 bytes
elsif mode = 3 and proc_count < 4 then
mode <= 4;
-- Wait
else
mode <= 1;
end if;
end if;
end process mealy_mach;
end genhash;
/deflatecore/trunk/HashChain.vhd
0,0 → 1,91
--------------------------------------------------------------------------------
-- Create Date: 03:46:54 10/31/05
-- Design Name:
-- Module Name: Hash - Behavioral
-- Project Name: Deflate
-- Revision:
-- Revision 0.25 - Only one hash algorithm
-- Additional Comments:
-- The remarked comments for synchronous reser result in the use of more 192 slices witn a maximum frequency of 129 Mhz
-- But if the code is commented as it is now the number of slices utlised is 5 without a known clock , need to specifiy that as a compile time constraint.
-- TO DO:
-- Wishbone interface
-- Concurrent Hashkey generation
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HashChain is
Generic
( -- Data bus width currently set at 8
Data_Width : natural := 8; -- Width of the hash key generated now at 32 bits
Hash_Width : natural := 32
);
Port ( Hash_O : inout std_logic_vector (Hash_Width - 1 downto 0); -- Hash value of previous data
Data_in : in std_logic_vector (Data_Width-1 downto 0); -- Data input from byte stream
Clock, -- Clock
Reset,
Start, -- Reset
O_E : in bit ; -- Output Enable
Busy,
Done : out bit -- Enabled when the hash key has been generated
);
end HashChain;
--An algorithm produced by Professor Daniel J. Bernstein and
--shown first to the world on the usenet newsgroup comp.lang.c.
--It is one of the most efficient hash functions ever published
--Actual function hash(i) = hash(i - 1) * 33 + str[i];
--Function now implemented using XOR hash(i) = hash(i - 1) * 33 ^ str[i];
architecture DJB2 of HashChain is
signal mode: integer := 0;
signal tempval, hash:std_logic_vector (Hash_Width - 1 downto 0):= X"00000000" ;
signal multiplier:std_logic_vector (39 downto 0):= X"0000000000" ;
begin
 
 
mealymachine: process (Clock)
begin
if Reset = '1' and Clock = '1' then -- Reset
mode <= 0;
elsif start = '1' and Clock = '1' then -- Start
mode <= 1; -- Multiply previous key by 33 ( Clock = 1 )
elsif mode = 1 then
mode <= 2; -- Ex-OR input with existing key ( Clock = 0 )
elsif mode = 2 then
mode <= 3; -- Latch output ( Clock = 1 )
else
mode <= 4;
end if;
end process mealymachine;
 
hash <= X"000016c7" when mode = 0 else --initialise the hash key to 5831
multiplier(31 downto 0) xor tempval when mode = 2 else --Ex or with the current input
hash; --keep current value
 
multiplier <= hash * X"21" when mode = 1 else --Multiply by 33
X"0000000000";
 
tempval <= X"00000000" when mode /= 1 else --Temporary value to be able to Exor the input with the hash key
tempval+ Data_in;
 
busy <= '1' when mode > 0 and mode < 3 else --Indicates that the key is being generated
'0' ;
 
 
Hash_O <= hash when mode = 3 and O_E = '1' else --Output buffer
Hash_O; --Hash op bufffer
 
done <= '1' when mode = 3 else --1 after hash key has been calculated
'0';
 
 
end DJB2;
 
Configuration djb2_hash of hashchain is
for djb2
end for;
end djb2_hash;
/deflatecore/trunk/.cvspass
0,0 → 1,91
:pserver:smallcode@cvs.opencores.org:/cvsroot/smallcode ARyeew1_
deflatecore/trunk Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: deflatecore/web_uploads =================================================================== --- deflatecore/web_uploads (nonexistent) +++ deflatecore/web_uploads (revision 18)
deflatecore/web_uploads Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: deflatecore/branches =================================================================== --- deflatecore/branches (nonexistent) +++ deflatecore/branches (revision 18)
deflatecore/branches Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ## Index: deflatecore/tags/arelease/.cvspass =================================================================== --- deflatecore/tags/arelease/.cvspass (nonexistent) +++ deflatecore/tags/arelease/.cvspass (revision 18) @@ -0,0 +1 @@ +:pserver:smallcode@cvs.opencores.org:/cvsroot/smallcode ARyeew1_ Index: deflatecore/tags/arelease/HashChain.vhd =================================================================== --- deflatecore/tags/arelease/HashChain.vhd (nonexistent) +++ deflatecore/tags/arelease/HashChain.vhd (revision 18) @@ -0,0 +1,135 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- Create Date: 03:46:54 10/31/05 +-- Design Name: +-- Module Name: Hash - Behavioral +-- Project Name: Deflate +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +use IEEE.std_logic_unsigned.all; +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity HashChain is + Port ( Data_in : in std_logic_vector (7 downto 0); -- Data input from byte stream + Hash_o : out real; -- Hash value of previous data + Clock, -- Clock + Reset, -- Reset + Output_E : in bit -- Output Enable + ); +end HashChain; + + +--From Robert Sedgwicks Algorithms in C +architecture RSHash of HashChain is +signal mode, + data : integer; + +begin +mode <= 0 when clock = '1' and reset = '0' and Output_E = '1' else -- Active data being latched to output + 1 when clock = '0' and reset = '0' and Output_E = '1' else -- No change to output till thge next clock + 2 when clock = '1' and reset = '1' and Output_E = '1' else -- Reset active + 2 when clock = '1' and reset = '1' and Output_E = '0' else -- Reset active + 3 when clock = '1' and reset = '0' and Output_E = '0' else -- Disable output + 4; +--data <= Data_in; --Need to convert the input standard logic input to a form that can be processed using arthimetic +Process (mode) +variable a, b, hash : real ; -- Variables for calculating the output +begin +case mode is +when 0 => --Calculate the hash key of the current input value using the Data on the input vector + hash := hash * a; + hash := hash + data; + a := a * b; +when 2 => + hash := 0.0; -- Reset + a:=378551.0; -- Reset + b:=63689.0; -- Reset +when 3=> -- Need to implement a disable output section + +when OTHERS => -- Do nothing + +End case; +hash_o<= hash; -- Assign the clculated hash value to the output +end process; +end RSHash; + +--An algorithm produced by Professor Daniel J. Bernstein and +--shown first to the world on the usenet newsgroup comp.lang.c. +--It is one of the most efficient hash functions ever published +--Actual function hash(i) = hash(i - 1) * 33 + str[i]; +--Function now implemented using XOR hash(i) = hash(i - 1) * 33 ^ str[i]; +architecture DJB of HashChain is +signal mode, + data : integer; + +begin +mode <= 0 when clock = '1' and reset = '0' and Output_E = '1' else -- Active data being latched to output + 1 when clock = '0' and reset = '0' and Output_E = '1' else -- No change to output till thge next clock + 2 when clock = '1' and reset = '1' and Output_E = '1' else -- Reset active + 2 when clock = '1' and reset = '1' and Output_E = '0' else -- Reset active + 3 when clock = '1' and reset = '0' and Output_E = '0' else -- Disable output + 4; +--data <= Data_in; --Need to convert the input standard logic input to a form that can be processed using arthimetic +Process (mode) +variable a, b, hash : real ; -- Variables for calculating the output +begin +case mode is +when 0 => --Calculate the hash key of the current input value using the Data on the input vector + a := hash * 33.0; + hash := a + hash + data; +when 2 => + hash := 5831.0; -- Reset +when 3=> -- Need to implement a disable output section + +when OTHERS => -- Do nothing + +End case; +hash_o<= hash; -- Assign the clculated hash value to the output +end process; +end DJB; + + +--This algorithm was created for sdbm (a public-domain reimplementation of ndbm) database library. +--it was found to do well in scrambling bits, causing better distribution of the keys and fewer splits. +--it also happens to be a good general hashing function with good distribution. +--the actual function is hash(i) = hash(i - 1) * 65599 + str[i]; +architecture sdbm of HashChain is +signal mode, + data : integer; + +begin +mode <= 0 when clock = '1' and reset = '0' and Output_E = '1' else -- Active data being latched to output + 1 when clock = '0' and reset = '0' and Output_E = '1' else -- No change to output till thge next clock + 2 when clock = '1' and reset = '1' and Output_E = '1' else -- Reset active + 2 when clock = '1' and reset = '1' and Output_E = '0' else -- Reset active + 3 when clock = '1' and reset = '0' and Output_E = '0' else -- Disable output + 4; +--data <= Data_in; --Need to convert the input standard logic input to a form that can be processed using arthimetic +Process (mode) +variable a, b, hash : real ; -- Variables for calculating the output +begin +case mode is +when 0 => --Calculate the hash key of the current input value using the Data on the input vector + a := hash * 65599.0; + hash := a + hash + data; +when 2 => + hash := 0.0; -- Reset +when 3=> -- Need to implement a disable output section + +when OTHERS => -- Do nothing + +End case; +hash_o<= hash; -- Assign the clculated hash value to the output +end process; +end sdbm; \ No newline at end of file Index: deflatecore/tags =================================================================== --- deflatecore/tags (nonexistent) +++ deflatecore/tags (revision 18)
deflatecore/tags Property changes : Added: svn:mergeinfo ## -0,0 +0,0 ##

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