URL
https://opencores.org/ocsvn/fixed_point_arithmetic_parameterized/fixed_point_arithmetic_parameterized/trunk
Subversion Repositories fixed_point_arithmetic_parameterized
Compare Revisions
- This comparison shows the changes necessary to convert path
/fixed_point_arithmetic_parameterized/trunk
- from Rev 1 to Rev 2
- ↔ Reverse comparison
Rev 1 → Rev 2
/implementation/top.v
0,0 → 1,39
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 14:00:23 08/25/2011 |
// Design Name: |
// Module Name: top |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module top( |
input [31:0] a, |
input [31:0] b, |
output [31:0] c, |
input clk, |
input start |
); |
// Inputs |
reg [31:0] a_sig; |
reg [31:0] b_sig; |
|
// Outputs |
reg [31:0] c_sig; |
|
// Instantiate the Unit Under Test (UUT) |
// qadd #(23,32) uut (a, b, c); |
// qmult #(23,32) uut (a, b, c); |
qdiv #(15,32) uut (a, b, start, clk, c); |
endmodule |
/src/qtwosComp.v
0,0 → 1,50
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 13:44:20 08/24/2011 |
// Design Name: |
// Module Name: twosComp |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module qtwosComp( |
input [N-2:0] a, |
output [2*N-1:0] b |
); |
reg [2*N-1:0] data; |
reg [2*N-1:0] flip; |
reg [2*N-1:0] out; |
|
//Parameterized values |
parameter Q = 15; |
parameter N = 32; |
|
assign b = out; |
|
always @(a) |
begin |
data <= a; //if you dont put the value into a 64b register, when you flip the bits it wont work right |
end |
|
always @(data) |
begin |
flip <= ~a; |
end |
|
always @(flip) |
begin |
out <= flip + 1; |
end |
|
endmodule |
/src/qmult.v
0,0 → 1,79
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 11:21:14 08/24/2011 |
// Design Name: |
// Module Name: q15_mult |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module qmult( |
input [N-1:0] a, |
input [N-1:0] b, |
output [N-1:0] c |
); |
|
wire [2*N-1:0] a_ext; |
wire [2*N-1:0] b_ext; |
wire [2*N-1:0] r_ext; |
|
reg [2*N-1:0] a_mult; |
reg [2*N-1:0] b_mult; |
reg [2*N-1:0] result; |
reg [N-1:0] retVal; |
|
//Parameterized values |
parameter Q = 15; |
parameter N = 32; |
|
qtwosComp #(Q,N) comp_a (a[30:0], a_ext); |
|
qtwosComp #(Q,N) comp_b (b[30:0], b_ext); |
|
qtwosComp #(Q,N) comp_r (result[N-2+Q:Q], r_ext); |
|
assign c = retVal; |
|
always @(a_ext,b_ext) |
begin |
if(a[N-1] == 1) |
a_mult <= a_ext; |
else |
a_mult <= a; |
|
if(b[N-1] == 1) |
b_mult <= b_ext; |
else |
b_mult <= b; |
end |
|
always @(a_mult,b_mult) |
begin |
result <= a_mult * b_mult; |
end; |
|
always @(result,r_ext) |
begin |
//sign |
if((a[N-1] == 1 && b[N-1] == 0) || (a[N-1] == 0 && b[N-1] == 1)) begin |
retVal[N-1] <= 1; |
retVal[N-2:0] <= r_ext[N-2:0]; |
end |
else begin |
retVal[N-1] <= 0; |
retVal[N-2:0] <= result[N-2+Q:Q]; |
end |
end |
|
endmodule |
/src/qdiv.v
0,0 → 1,87
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 19:39:14 08/24/2011 |
// Design Name: |
// Module Name: divider |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
|
module qdiv( |
input [N-1:0] dividend, |
input [N-1:0] divisor, |
input start, |
input clk, |
output [N-1:0] quotient_out, |
output complete |
); |
|
//Parameterized values |
parameter Q = 15; |
parameter N = 32; |
|
reg [N-1:0] quotient; |
reg [N-1:0] dividend_copy; |
reg [2*(N-1)-1:0] divider_copy; |
|
reg [5:0] bit; |
reg done; |
|
initial done = 1; |
|
assign quotient_out = quotient; |
assign complete = done; |
|
always @( posedge clk ) |
begin |
if( done && start ) begin |
|
done <= 1'b0; |
bit <= N+Q-2; |
quotient <= 0; |
dividend_copy <= {1'b0,dividend[N-2:0]}; |
|
divider_copy[2*(N-1)-1] <= 0; |
divider_copy[2*(N-1)-2:N-2] <= divisor[N-2:0]; |
divider_copy[N-3:0] <= 0; |
|
//set sign bit |
if((dividend[N-1] == 1 && divisor[N-1] == 0) || (dividend[N-1] == 0 && divisor[N-1] == 1)) |
quotient[N-1] <= 1; |
else |
quotient[N-1] <= 0; |
end |
else if(!done) begin |
|
//compare divisor/dividend |
if(dividend_copy >= divider_copy) begin |
//subtract |
dividend_copy <= dividend_copy - divider_copy; |
//set quotient |
quotient[bit] <= 1'b1; |
end |
|
//reduce divisor |
divider_copy <= divider_copy >> 1; |
|
//reduce bit counter |
bit <= bit - 1; |
|
//stop condition |
if(dividend_copy == 0) |
done <= 1'b1; |
end |
end |
endmodule |
/src/qadd.v
0,0 → 1,74
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 09:28:18 08/24/2011 |
// Design Name: |
// Module Name: q15_add |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module qadd( |
input [N-1:0] a, |
input [N-1:0] b, |
output [N-1:0] c |
); |
//sign+16.15 |
|
//Parameterized values |
parameter Q = 15; |
parameter N = 32; |
|
reg [N-1:0] res; |
|
assign c = res; |
|
always @(a,b) |
begin |
//both negative |
if(a[N-1] == 1 && b[N-1] == 1) begin |
//sign |
res[N-1] = 1; |
//whole |
res[N-2:0] = a[N-2:0] + b[N-2:0]; |
end |
//both positive |
else if(a[N-1] == 0 && b[N-1] == 0) begin |
//sign |
res[N-1] = 0; |
//whole |
res[N-2:0] = a[N-2:0] + b[N-2:0]; |
end |
//subtract a-b |
else if(a[N-1] == 0 && b[N-1] == 1) begin |
//sign |
if(a[N-2:0] > b[N-2:0]) |
res[N-1] = 1; |
else |
res[N-1] = 0; |
//whole |
res[N-2:0] = a[N-2:0] - b[N-2:0]; |
end |
//subtract b-a |
else begin |
//sign |
if(a[N-2:0] < b[N-2:0]) |
res[N-1] = 1; |
else |
res[N-1] = 0; |
//whole |
res[N-2:0] = b[N-2:0] - a[N-2:0]; |
end |
end |
|
endmodule |
/testfixtures/qmult_tf.v
0,0 → 1,56
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 13:57:25 08/24/2011 |
// Design Name: q15_mult |
// Module Name: C:/Documents and Settings/samskalicky/Desktop/PLE/q15_mult_tf.v |
// Project Name: PLE |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: q15_mult |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module qmult_tf; |
|
// Inputs |
reg [31:0] a; |
reg [31:0] b; |
|
// Outputs |
wire [31:0] c; |
|
// Instantiate the Unit Under Test (UUT) |
//module Params Name Signals |
qmult #(23,32) uut (a, b, c); |
|
initial begin |
// Initialize Inputs |
a[31] = 0; |
a[30:23] = 64; |
a[22:0] = 1048576;//1048576;//4096; |
|
b[31] = 1; |
b[30:23] = 0; |
b[22:0] = 6291456;//6291456;//24576; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
|
end |
|
endmodule |
|
/testfixtures/qdiv_tf.v
0,0 → 1,65
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 19:41:28 08/24/2011 |
// Design Name: divider |
// Module Name: C:/Documents and Settings/samskalicky/Desktop/PLE/divider_tf.v |
// Project Name: PLE |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: divider |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module qdiv_tf; |
|
// Inputs |
reg [31:0] dividend; |
reg [31:0] divisor; |
reg start; |
reg clk; |
|
// Outputs |
wire [31:0] quotient; |
|
// Instantiate the Unit Under Test (UUT) |
//module Params Name Signals |
qdiv #(15,32) uut (dividend, divisor, start, clk, quotient); |
|
initial begin |
// Initialize Inputs |
dividend[31] = 0; |
dividend[30:15] = 64; |
dividend[14:0] = 4096;//1048576;//4096; |
|
divisor[31] = 0; |
divisor[30:15] = 2; |
divisor[14:0] = 0; |
start = 1; |
clk = 0; |
|
// Wait 100 ns for global reset to finish |
#100; |
|
// Add stimulus here |
start = 0; |
end |
|
always |
begin |
#5 clk = ~clk; |
end |
|
endmodule |
|
/testfixtures/qadd_tf.v
0,0 → 1,78
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Company: |
// Engineer: |
// |
// Create Date: 09:36:47 08/24/2011 |
// Design Name: q15_add |
// Module Name: C:/Documents and Settings/samskalicky/Desktop/PLE/q_15_add_tf.v |
// Project Name: PLE |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: q15_add |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module qadd_tf; |
|
// Inputs |
reg [31:0] a; |
reg [31:0] b; |
|
// Outputs |
wire [31:0] c; |
|
// Instantiate the Unit Under Test (UUT) |
qadd #(23,32) uut (a, b, c); |
|
initial begin |
// Initialize Inputs |
a = 0; |
b = 0; |
|
#100; |
|
a = 1; |
b = 0; |
|
#100; |
|
a = 0; |
b = 1; |
|
#100; |
|
a = 1; |
b = 1; |
|
#100; |
|
a[31:23] = 64; |
a[22:0] = 125; |
b[31:23] = 0; |
b[22:0] = 75; |
|
#100; |
|
a[30]=0; |
a[30:23] = 64; |
a[22:0] = 1048576; |
b[31]=1; |
b[30:23] = 0; //-1 |
b[22:0] = 6291456; |
|
// Add stimulus here |
#100; |
end |
|
endmodule |
|