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URL https://opencores.org/ocsvn/highload/highload/trunk

Subversion Repositories highload

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Rev 3 → Rev 2

/highload/trunk/lc_use.vhd
14,8 → 14,7
generic (
DATA_WIDTH : positive := 128;
ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
NUM_ROWS: positive := 6; -- Input pins
ADD_PIPL_FF : boolean := false
NUM_ROWS: positive := 6 -- Input pins
);
port
(
28,7 → 27,7
 
architecture rtl of lc_use is
type TArr is array (natural range <>) of unsigned(127 downto 0);
signal arr : TArr(0 to 3*NUM_ROWS) := (others => (others => '0'));
signal arr : TArr(0 to 2*NUM_ROWS) := (others => (others => '0'));
 
begin
 
39,28 → 38,18
if rising_edge(clk) then
arr(0)(DATA_WIDTH-1 downto 0) <= unsigned(inputs);
for i in 0 to NUM_ROWS-1 loop
arr(3*i+1) <= arr(3*i) xor (arr(3*i) rol 1) xor (arr(3*i) rol 2) xor (arr(3*i) rol 3);
arr(2*i+1) <= arr(2*i) xor (arr(2*i) rol 1) xor (arr(2*i) rol 2) xor (arr(2*i) rol 3);
for j in 0 to DATA_WIDTH/ARITH_SIZE-1 loop
arr(3*i+2)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) <=
arr(3*i+0)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) +
arr(3*i+1)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE);
arr(2*i+2)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) <=
arr(2*i+0)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE) +
arr(2*i+1)((j+1)*ARITH_SIZE - 1 downto j*ARITH_SIZE);
end loop;
if ADD_PIPL_FF then
arr(3*i+3) <= arr(3*i+2);
end if;
end loop;
dataout <= std_logic_vector(arr(3*NUM_ROWS));
dataout <= std_logic_vector(arr(2*NUM_ROWS));
 
end if;
 
end process;
 
no_ff_gen: if not ADD_PIPL_FF generate
ff_loop_gen: for i in 0 to NUM_ROWS-1 generate
arr(3*i+3) <= arr(3*i+2);
end generate;
end generate;
 
 
end rtl;
/highload/trunk/high_load.vhd
64,8 → 64,7
generic (
DATA_WIDTH : positive := 128;
ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
NUM_ROWS: positive := 6; -- Input pins
ADD_PIPL_FF : boolean := false
NUM_ROWS: positive := 6 -- Input pins
);
port
(
210,8 → 209,7
generic map (
DATA_WIDTH => 128,
ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
NUM_ROWS => 6, -- Input pins
ADD_PIPL_FF => true
NUM_ROWS => 6 -- Input pins
)
port map
(

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