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URL https://opencores.org/ocsvn/highload/highload/trunk

Subversion Repositories highload

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Rev 4 → Rev 3

/highload/trunk/lc_use.vhd
12,7 → 12,6
 
entity lc_use is
generic (
RECURSION_IDX : positive := 1; -- 1 = stop recursion
DATA_WIDTH : positive := 128;
ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
NUM_ROWS: positive := 6; -- Input pins
30,9 → 29,7
architecture rtl of lc_use is
type TArr is array (natural range <>) of unsigned(127 downto 0);
signal arr : TArr(0 to 3*NUM_ROWS) := (others => (others => '0'));
signal dataout_i: std_logic_vector(DATA_WIDTH-1 downto 0);
 
 
begin
 
assert DATA_WIDTH mod ARITH_SIZE = 0 report "ARITH_SIZE should be divider of DATA_WIDTH" severity error;
53,7 → 50,7
end if;
end loop;
dataout_i <= std_logic_vector(arr(3*NUM_ROWS));
dataout <= std_logic_vector(arr(3*NUM_ROWS));
 
end if;
 
65,25 → 62,5
end generate;
end generate;
 
gen_rec1: if RECURSION_IDX = 1 generate
dataout <= dataout_i;
end generate;
 
gen_recN: if RECURSION_IDX > 1 generate
lc_i: entity work.lc_use
generic map (
RECURSION_IDX => RECURSION_IDX-1,
DATA_WIDTH => 128,
ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
NUM_ROWS => 6, -- Input pins
ADD_PIPL_FF => true
)
port map
(
clk => clk,
inputs => dataout_i,
dataout=> dataout
);
end generate;
 
end rtl;
/highload/trunk/high_load.vhd
9,7 → 9,7
--
-- It can operate at 200 MHz in Cyclone 5E FPGA
--
-- 1 LC core is about 1500 LUT4/FF (with default parameters)
-- 1 LC core is about 1500 LUT4/FF (with default parameters)
-- 1 DSP core is 7 DSP 18*18.
-- Each LC core also demands 4*N RAM block (32 bits width)
 
33,7 → 33,6
NUM_IN : positive := 3*14; -- Input pins
NUM_OUT : positive := 1; -- Output pins
NUM_LC : positive := 16; -- Number of LC cores
LC_RECURSION : positive := 1; -- 1 = no recursion
NUM_DSP : positive := 9; -- Number of DSP cores
RAM_DEPTH_LOG2 : integer range 4 to 30 := 10 -- RAM depth
);
63,7 → 62,6
 
component lc_use is
generic (
RECURSION_IDX : positive := 1; -- 1 = stop recursion
DATA_WIDTH : positive := 128;
ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
NUM_ROWS: positive := 6; -- Input pins
210,7 → 208,6
-- );
lc_i: lc_use
generic map (
RECURSION_IDX => LC_RECURSION,
DATA_WIDTH => 128,
ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
NUM_ROWS => 6, -- Input pins

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