URL
https://opencores.org/ocsvn/lpffir/lpffir/trunk
Subversion Repositories lpffir
Compare Revisions
- This comparison shows the changes necessary to convert path
/lpffir/trunk/rtl
- from Rev 2 to Rev 7
- ↔ Reverse comparison
Rev 2 → Rev 7
/lpffir_axis.sv
0,0 → 1,77
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Low Pass Filter FIR with AXI-Stream Interface //// |
//// //// |
//// This file is part of the LPFFIR project //// |
//// https://opencores.org/projects/lpffir //// |
//// //// |
//// Description //// |
//// Implementation of AXI-Stream (AXIS) protocol rapper //// |
/// of LPFFIR IP core according to //// |
//// LPFFIR IP core specification document. //// |
//// //// |
//// To Do: //// |
//// - //// |
//// //// |
//// Author: //// |
//// - Vladimir Armstrong, vladimirarmstrong@opencores.org //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2019 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
module lpffir_axis ( |
input aclk_i, |
input aresetn_i, |
// AXI-Stream RX interface |
input rx_tlast_i, |
input rx_tvalid_i, |
output logic rx_tready_o, |
input [15:0] rx_tdate_i, |
// AXI-Stream TX interface |
output logic tx_tlast_o, |
output reg tx_tvalid_o, |
input tx_tready_i, |
output logic [15:0] tx_tdate_o |
); |
|
logic lpffir_en = rx_tvalid_i && tx_tready_i; |
|
// AXI-Stream interface |
assign rx_tready_o = lpffir_en; |
assign tx_tvalid_o = lpffir_en; |
assign tx_tlast_o = rx_tlast_i; |
|
// LPFFIR |
lpffir_core lpffir_core( |
.clk_i(aclk_i), |
.rstn_i(aresetn_i), |
.en_i(lpffir_en), |
.x_i(rx_tdate_i), |
.y_o(tx_tdate_o) |
); |
|
endmodule |
/lpffir_core.sv
43,27 → 43,29
////////////////////////////////////////////////////////////////////// |
|
module lpffir_core ( |
input [15:0] x_i, |
input clk_i, |
output logic [15:0] y_o |
); |
input clk_i, |
input rstn_i, |
input en_i, |
input [15:0] x_i, |
output logic [15:0] y_o |
); |
|
reg [15:0] x1; |
reg [15:0] x2; |
reg [15:0] x3; |
reg [15:0] x4; |
reg [15:0] x5; |
reg [15:0] x1; |
reg [15:0] x2; |
reg [15:0] x3; |
reg [15:0] x4; |
reg [15:0] x5; |
|
logic [15:0] h0; |
logic [15:0] h1; |
logic [15:0] h2; |
logic [15:0] h01; |
logic [15:0] h0; |
logic [15:0] h1; |
logic [15:0] h2; |
logic [15:0] h01; |
|
logic co0; |
logic co1; |
logic co2; |
logic co3; |
logic co4; |
logic co0; |
logic co1; |
logic co2; |
logic co3; |
logic co4; |
|
// Linear-phase FIR structure |
rca rca_inst0 (.a(x_i),.b(x5),.ci(0),.co(co0),.s(h0)); |
72,13 → 74,22
rca rca_inst3 (.a(h0),.b(h1),.ci(0),.co(co3),.s(h01)); |
rca rca_inst4 (.a(h01),.b(h2),.ci(0),.co(co4),.s(y_o)); |
|
always_ff @(posedge clk_i) |
begin |
x1 <= x_i; |
x2 <= x1; |
x3 <= x2; |
x4 <= x3; |
x5 <= x4; |
end |
always_ff @(posedge clk_i or posedge rstn_i) |
if(!rstn_i) |
begin |
x1 <= 0; |
x2 <= 0; |
x3 <= 0; |
x4 <= 0; |
x5 <= 0; |
end |
else if (en_i) |
begin |
x1 <= x_i; |
x2 <= x1; |
x3 <= x2; |
x4 <= x3; |
x5 <= x4; |
end |
|
endmodule |