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URL https://opencores.org/ocsvn/lpffir/lpffir/trunk

Subversion Repositories lpffir

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Rev 1 → Rev 2

/trunk/bench/systemc/main.cpp
0,0 → 1,84
//////////////////////////////////////////////////////////////////////
//// ////
//// Low Pass Filter FIR IP Core ////
//// ////
//// This file is part of the LPFFIR project ////
//// https://opencores.org/projects/lpffir ////
//// ////
//// Description ////
//// Implementation of LPFFIR IP core according to ////
//// LPFFIR IP core specification document. ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author: ////
//// - Vladimir Armstrong, vladimirarmstrong@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// SystemC Test Bench
#include "systemc.h"
#include "verilated_vcd_sc.h"
#include "Vbench.h"
 
#define TRACE
 
int sc_main(int argc, char * argv[])
{
 
#ifdef TRACE
// Verilator trace file
Verilated::traceEverOn(true);
VerilatedVcdSc* tfp = new VerilatedVcdSc;
#endif
 
sc_time T(10,SC_NS);
sc_time Tsim = T * 15 ;
sc_clock clk("clk",T);
sc_signal<bool> rst("rst");
Vbench uut("top");
uut.clk (clk);
uut.rst(rst);
 
#ifdef TRACE
// Verilator trace file, depth
uut.trace(tfp, 10);
tfp->open("simu.vcd");
#endif
 
rst = 1;
sc_start(10*T);
rst = 0;
sc_start(Tsim);
 
#ifdef TRACE
tfp->close();
#endif
return 0;
}
/trunk/bench/verilog/bench.sv
0,0 → 1,78
//////////////////////////////////////////////////////////////////////
//// ////
//// Low Pass Filter FIR IP Core ////
//// ////
//// This file is part of the LPFFIR project ////
//// https://opencores.org/projects/lpffir ////
//// ////
//// Description ////
//// Implementation of LPFFIR IP core according to ////
//// LPFFIR IP core specification document. ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author: ////
//// - Vladimir Armstrong, vladimirarmstrong@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
// Verilog test bench
module bench (
input clk,
input rst
);
 
// Test case #1: check impulse response of low-pass filter.
logic [15:0] in = (count == 1) ? 1:0;
logic [15:0] out;
reg [31:0] count;
 
always_ff @(posedge clk or posedge rst)
if (rst)
count <= 0;
else
count <= count + 1;
 
// unit under test(UUT)
lpffir_core lpffir_core(.x_i(in),.clk_i(clk),.y_o(out));
 
// Test case log
initial begin
$display("Test Case #1:");
$display("Check impulse response of low-pass filter.");
$display("RTL simulation results:");
$display("Input Output");
$display("----- ------");
end
 
always_ff @(posedge clk or posedge rst)
if(!rst)
$display(" %0d %0d", in, out);
 
endmodule
/trunk/doc/src/lpffir_design.docx Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/doc/src/lpffir_design.docx
trunk/doc/src/lpffir_design.docx Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/lpffir_specification.docx =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/lpffir_specification.docx =================================================================== --- trunk/doc/src/lpffir_specification.docx (nonexistent) +++ trunk/doc/src/lpffir_specification.docx (revision 2)
trunk/doc/src/lpffir_specification.docx Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/lpffir_verification.docx =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/lpffir_verification.docx =================================================================== --- trunk/doc/src/lpffir_verification.docx (nonexistent) +++ trunk/doc/src/lpffir_verification.docx (revision 2)
trunk/doc/src/lpffir_verification.docx Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/matlab_responsePlots.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/matlab_responsePlots.png =================================================================== --- trunk/doc/src/matlab_responsePlots.png (nonexistent) +++ trunk/doc/src/matlab_responsePlots.png (revision 2)
trunk/doc/src/matlab_responsePlots.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/doc/src/rtl_impulseResponse.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/rtl_impulseResponse.png =================================================================== --- trunk/doc/src/rtl_impulseResponse.png (nonexistent) +++ trunk/doc/src/rtl_impulseResponse.png (revision 2)
trunk/doc/src/rtl_impulseResponse.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/fa.sv =================================================================== --- trunk/rtl/fa.sv (nonexistent) +++ trunk/rtl/fa.sv (revision 2) @@ -0,0 +1,62 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Low Pass Filter FIR IP Core //// +//// //// +//// This file is part of the LPFFIR project //// +//// https://opencores.org/projects/lpffir //// +//// //// +//// Description //// +//// Implementation of LPFFIR IP core according to //// +//// LPFFIR IP core specification document. //// +//// //// +//// To Do: //// +//// - //// +//// //// +//// Author: //// +//// - Vladimir Armstrong, vladimirarmstrong@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2019 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// Full Adder: adds three 1-bit numbers +module fa( + input a, + input b, + input ci, // Carry Input + + output logic co, // Carry Output + output logic s // Sum + ); + + logic d,e,f; + + xor(s,a,b,ci); + and(d,a,b); + and(e,b,ci); + and(f,a,ci); + or(co,d,e,f); +endmodule Index: trunk/rtl/lpffir_core.sv =================================================================== --- trunk/rtl/lpffir_core.sv (nonexistent) +++ trunk/rtl/lpffir_core.sv (revision 2) @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Low Pass Filter FIR IP Core //// +//// //// +//// This file is part of the LPFFIR project //// +//// https://opencores.org/projects/lpffir //// +//// //// +//// Description //// +//// Implementation of LPFFIR IP core according to //// +//// LPFFIR IP core specification document. //// +//// //// +//// To Do: //// +//// - //// +//// //// +//// Author: //// +//// - Vladimir Armstrong, vladimirarmstrong@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2019 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +module lpffir_core ( + input [15:0] x_i, + input clk_i, + output logic [15:0] y_o + ); + + reg [15:0] x1; + reg [15:0] x2; + reg [15:0] x3; + reg [15:0] x4; + reg [15:0] x5; + + logic [15:0] h0; + logic [15:0] h1; + logic [15:0] h2; + logic [15:0] h01; + + logic co0; + logic co1; + logic co2; + logic co3; + logic co4; + + // Linear-phase FIR structure + rca rca_inst0 (.a(x_i),.b(x5),.ci(0),.co(co0),.s(h0)); + rca rca_inst1 (.a(x1),.b(x4),.ci(0),.co(co1),.s(h1)); + rca rca_inst2 (.a(x2),.b(x3),.ci(0),.co(co2),.s(h2)); + rca rca_inst3 (.a(h0),.b(h1),.ci(0),.co(co3),.s(h01)); + rca rca_inst4 (.a(h01),.b(h2),.ci(0),.co(co4),.s(y_o)); + + always_ff @(posedge clk_i) + begin + x1 <= x_i; + x2 <= x1; + x3 <= x2; + x4 <= x3; + x5 <= x4; + end + +endmodule Index: trunk/rtl/rca.sv =================================================================== --- trunk/rtl/rca.sv (nonexistent) +++ trunk/rtl/rca.sv (revision 2) @@ -0,0 +1,95 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// Low Pass Filter FIR IP Core //// +//// //// +//// This file is part of the LPFFIR project //// +//// https://opencores.org/projects/lpffir //// +//// //// +//// Description //// +//// Implementation of LPFFIR IP core according to //// +//// LPFFIR IP core specification document. //// +//// //// +//// To Do: //// +//// - //// +//// //// +//// Author: //// +//// - Vladimir Armstrong, vladimirarmstrong@opencores.org //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2019 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// + +// Ripple Carry Adder: adds two 16-bit numbers +module rca( + input [15:0] a, + input [15:0] b, + input ci, // Carry Input + + output logic co, // Carry Output + output logic [15:0] s // Sum + ); + + logic a0,a1,a2,a3,a4,a5,a6,a7; + logic a8,a9,a10,a11,a12,a13,a14,a15; + logic b0,b1,b2,b3,b4,b5,b6,b7; + logic b8,b9,b10,b11,b12,b13,b14,b15; + logic c0,c1,c2,c3,c4,c5,c6,c7; + logic c8,c9,c10,c11,c12,c13,c14; + logic s0,s1,s2,s3,s4,s5,s6,s7; + logic s8,s9,s10,s11,s12,s13,s14,s15; + + assign a0 = a[0], a1 = a[1], a2 = a[2], a3 = a[3]; + assign a4 = a[4], a5 = a[5], a6 = a[6], a7 = a[7]; + assign a8 = a[8], a9 = a[9], a10 = a[10]; + assign a11 = a[11], a12 = a[12], a13 = a[13]; + assign a14 = a[14], a15 = a[15]; + assign b0 = b[0], b1 = b[1], b2 = b[2], b3 = b[3]; + assign b4 = b[4], b5 = b[5], b6 = b[6], b7 = b[7]; + assign b8 = b[8], b9 = b[9], b10 = b[10], b11 = b[11]; + assign b12 = b[12], b13 = b[13], b14 = b[14], b15 = b[15]; + assign s[0] = s0, s[1] = s1, s[2] = s2, s[3] = s3; + assign s[4] = s4, s[5] = s5,s[6] = s6, s[7] = s7; + assign s[8] = s8, s[9] = s9, s[10] = s10, s[11] = s11; + assign s[12] = s12, s[13] = s13, s[14] = s14, s[15] = s15; + + fa fa_inst0(.a(a0),.b(b0),.ci(ci),.co(c0),.s(s0)); + fa fa_inst1(.a(a1),.b(b1),.ci(c0),.co(c1),.s(s1)); + fa fa_inst2(.a(a2),.b(b2),.ci(c1),.co(c2),.s(s2)); + fa fa_inst3(.a(a3),.b(b3),.ci(c2),.co(c3),.s(s3)); + fa fa_inst4(.a(a4),.b(b4),.ci(c3),.co(c4),.s(s4)); + fa fa_inst5(.a(a5),.b(b5),.ci(c4),.co(c5),.s(s5)); + fa fa_inst6(.a(a6),.b(b6),.ci(c5),.co(c6),.s(s6)); + fa fa_inst7(.a(a7),.b(b7),.ci(c6),.co(c7),.s(s7)); + fa fa_inst8(.a(a8),.b(b8),.ci(c7),.co(c8),.s(s8)); + fa fa_inst9(.a(a9),.b(b9),.ci(c8),.co(c9),.s(s9)); + fa fa_inst10(.a(a10),.b(b10),.ci(c9),.co(c10),.s(s10)); + fa fa_inst11(.a(a11),.b(b11),.ci(c10),.co(c11),.s(s11)); + fa fa_inst12(.a(a12),.b(b12),.ci(c11),.co(c12),.s(s12)); + fa fa_inst13(.a(a13),.b(b13),.ci(c12),.co(c13),.s(s13)); + fa fa_inst14(.a(a14),.b(b14),.ci(c13),.co(c14),.s(s14)); + fa fa_inst15(.a(a15),.b(b15),.ci(c14),.co(co),.s(s15)); + +endmodule Index: trunk/sim/matlab_sim/out/matlab_impulseResponse.txt =================================================================== --- trunk/sim/matlab_sim/out/matlab_impulseResponse.txt (nonexistent) +++ trunk/sim/matlab_sim/out/matlab_impulseResponse.txt (revision 2) @@ -0,0 +1,8 @@ +1 +1 +1 +1 +1 +1 +0 +0 Index: trunk/sim/matlab_sim/out/matlab_responsePlots.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sim/matlab_sim/out/matlab_responsePlots.png =================================================================== --- trunk/sim/matlab_sim/out/matlab_responsePlots.png (nonexistent) +++ trunk/sim/matlab_sim/out/matlab_responsePlots.png (revision 2)
trunk/sim/matlab_sim/out/matlab_responsePlots.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sim/matlab_sim/run/OCTAVE_README.txt =================================================================== --- trunk/sim/matlab_sim/run/OCTAVE_README.txt (nonexistent) +++ trunk/sim/matlab_sim/run/OCTAVE_README.txt (revision 2) @@ -0,0 +1 @@ +For GNU Octave, version 4.2.2 users please install and add "pkg load signal" line to your "~/.octaverc" file. Index: trunk/sim/matlab_sim/run/lpf_response.m =================================================================== --- trunk/sim/matlab_sim/run/lpf_response.m (nonexistent) +++ trunk/sim/matlab_sim/run/lpf_response.m (revision 2) @@ -0,0 +1,72 @@ +% ////////////////////////////////////////////////////////////////////// +% //// //// +% //// Low Pass Filter FIR IP Core //// +% //// //// +% //// This file is part of the LPFFIR project //// +% //// https://opencores.org/projects/lpffir //// +% //// //// +% //// Description //// +% //// Implementation of LPFFIR IP core according to //// +% //// LPFFIR IP core specification document. //// +% //// //// +% //// To Do: //// +% //// - //// +% //// //// +% //// Author: //// +% //// - Vladimir Armstrong, vladimirarmstrong@opencores.org //// +% //// //// +% ////////////////////////////////////////////////////////////////////// +% //// //// +% //// Copyright (C) 2019 Authors and OPENCORES.ORG //// +% //// //// +% //// This source file may be used and distributed without //// +% //// restriction provided that this copyright statement is not //// +% //// removed from the file and that any derivative work contains //// +% //// the original copyright notice and the associated disclaimer. //// +% //// //// +% //// This source file is free software; you can redistribute it //// +% //// and/or modify it under the terms of the GNU Lesser General //// +% //// Public License as published by the Free Software Foundation; //// +% //// either version 2.1 of the License, or (at your option) any //// +% //// later version. //// +% //// //// +% //// This source is distributed in the hope that it will be //// +% //// useful, but WITHOUT ANY WARRANTY; without even the implied //// +% //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +% //// PURPOSE. See the GNU Lesser General Public License for more //// +% //// details. //// +% //// //// +% //// You should have received a copy of the GNU Lesser General //// +% //// Public License along with this source; if not, download it //// +% //// from http://www.opencores.org/lgpl.shtml //// +% //// //// +% ////////////////////////////////////////////////////////////////////// + +% Cleanup +clear;clc;close all; + +% Difference equation of low-pass filter +b = [1, 1, 1, 1, 1, 1]; a = [1]; + +% Response +n = [0:7]; +h = impz(b,a,8); +[H,w] = freqz(b,a,100); +magH = abs(H); phaH = angle(H); + +% Plot +subplot(4,1,1); stem(n,h); +title('Impulse Response'); xlabel('n'); ylabel('h(n)') +subplot(4,1,2);zplane(b,a);grid +title('Pole-Zero Plot') +subplot(4,1,3);plot(w/pi,magH);grid +xlabel('Frequency in \pi units'); ylabel('Magnitude'); +title('Magnitude Response') +subplot(4,1,4);plot(w/pi,phaH/pi);grid +xlabel('Frequency in \pi units'); ylabel('Phase in \pi units'); +title('Phase Response') + +% Write Tabular Impulse Response Data to Text File +fileID = fopen('matlab_impulseResponse.txt','w'); +fprintf(fileID,'%1.1d\n',h); +fclose(fileID); \ No newline at end of file Index: trunk/sim/rtl_sim/out/rtl_impulseResponse.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/sim/rtl_sim/out/rtl_impulseResponse.png =================================================================== --- trunk/sim/rtl_sim/out/rtl_impulseResponse.png (nonexistent) +++ trunk/sim/rtl_sim/out/rtl_impulseResponse.png (revision 2)
trunk/sim/rtl_sim/out/rtl_impulseResponse.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/sim/rtl_sim/out/rtl_impulseResponse.txt =================================================================== --- trunk/sim/rtl_sim/out/rtl_impulseResponse.txt (nonexistent) +++ trunk/sim/rtl_sim/out/rtl_impulseResponse.txt (revision 2) @@ -0,0 +1,22 @@ + SystemC 2.3.2-Accellera --- Apr 28 2018 13:46:26 + Copyright (c) 1996-2017 by all Contributors, + ALL RIGHTS RESERVED +Test Case #1: +Check impulse response of low-pass filter. +RTL simulation results: +Input Output +----- ------ + 0 0 + 1 1 + 0 1 + 0 1 + 0 1 + 0 1 + 0 1 + 0 0 + 0 0 + 0 0 + 0 0 + 0 0 + 0 0 + 0 0 Index: trunk/sim/rtl_sim/run/Makefile =================================================================== --- trunk/sim/rtl_sim/run/Makefile (nonexistent) +++ trunk/sim/rtl_sim/run/Makefile (revision 2) @@ -0,0 +1,32 @@ +export SYSTEMC ?= /opt/tools/SystemC/current/ +export SYSTEMC_ARCH = linux64 + +TOP_RTL = bench +TOP_RTL_FILE = $(patsubst %,%.sv,$(TOP_RTL)) +RTL_PATH = ../../../rtl +BENCH_PATH = ../../../bench/verilog +SC_TB_FILE = ../../../bench/systemc/main.cpp +OBJ_DIR = obj_dir +EXE = simu + +VERILATOR_OPT = -sc --trace -y $(RTL_PATH) -y $(BENCH_PATH) -exe -o ../$(EXE) + +.PHONY: gen exe all clean wave + +all: + make gen + make exe + +gen: + verilator $(VERILATOR_OPT) $(TOP_RTL_FILE) $(SC_TB_FILE) + +exe: + make -C $(OBJ_DIR) -f $(patsubst %,V%.mk, $(TOP_RTL)) + +wave: + gtkwave wave.gtkw + +clean: + rm -f *.vcd + rm -fr $(OBJ_DIR) + rm -f $(EXE) Index: trunk/sim/rtl_sim/run/wave.gtkw =================================================================== --- trunk/sim/rtl_sim/run/wave.gtkw (nonexistent) +++ trunk/sim/rtl_sim/run/wave.gtkw (revision 2) @@ -0,0 +1,25 @@ +[*] +[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI +[*] Sun Dec 30 18:25:07 2018 +[*] +[dumpfile] "/home/vlad/opencore/lpffir/trunk/sim/rtl_sim/run/simu.vcd" +[dumpfile_mtime] "Sun Dec 30 17:30:49 2018" +[dumpfile_size] 38184 +[savefile] "/home/vlad/opencore/lpffir/trunk/sim/rtl_sim/run/wave.gtkw" +[timestart] 96600 +[size] 2426 847 +[pos] -2397 579 +*-13.116134 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +[treeopen] top. +[treeopen] top.bench. +[sst_width] 229 +[signals_width] 202 +[sst_expanded] 1 +[sst_vpaned_height] 227 +@28 +top.bench.lpffir_core.clk_i +@22 +top.bench.lpffir_core.x_i[15:0] +top.bench.lpffir_core.y_o[15:0] +[pattern_trace] 1 +[pattern_trace] 0 Index: trunk/sw/out/check_impulseResponse.txt =================================================================== --- trunk/sw/out/check_impulseResponse.txt (nonexistent) +++ trunk/sw/out/check_impulseResponse.txt (revision 2) @@ -0,0 +1 @@ +Impulse Response Test: PASS \ No newline at end of file Index: trunk/sw/run/rtlMatlabCheck_impulseResponse.py =================================================================== --- trunk/sw/run/rtlMatlabCheck_impulseResponse.py (nonexistent) +++ trunk/sw/run/rtlMatlabCheck_impulseResponse.py (revision 2) @@ -0,0 +1,92 @@ +#!/usr/bin/python3 +# Python version: 3.6.7 +import re + +# ////////////////////////////////////////////////////////////////////// +# //// //// +# //// Low Pass Filter FIR IP Core //// +# //// //// +# //// This file is part of the LPFFIR project //// +# //// https://opencores.org/projects/lpffir //// +# //// //// +# //// Description //// +# //// Implementation of LPFFIR IP core according to //// +# //// LPFFIR IP core specification document. //// +# //// //// +# //// To Do: //// +# //// - //// +# //// //// +# //// Author: //// +# //// - Vladimir Armstrong, vladimirarmstrong@opencores.org //// +# //// //// +# ////////////////////////////////////////////////////////////////////// +# //// //// +# //// Copyright (C) 2019 Authors and OPENCORES.ORG //// +# //// //// +# //// This source file may be used and distributed without //// +# //// restriction provided that this copyright statement is not //// +# //// removed from the file and that any derivative work contains //// +# //// the original copyright notice and the associated disclaimer. //// +# //// //// +# //// This source file is free software; you can redistribute it //// +# //// and/or modify it under the terms of the GNU Lesser General //// +# //// Public License as published by the Free Software Foundation; //// +# //// either version 2.1 of the License, or (at your option) any //// +# //// later version. //// +# //// //// +# //// This source is distributed in the hope that it will be //// +# //// useful, but WITHOUT ANY WARRANTY; without even the implied //// +# //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +# //// PURPOSE. See the GNU Lesser General Public License for more //// +# //// details. //// +# //// //// +# //// You should have received a copy of the GNU Lesser General //// +# //// Public License along with this source; if not, download it //// +# //// from http://www.opencores.org/lgpl.shtml //// +# //// //// +# ////////////////////////////////////////////////////////////////////// + +# path +rtl_path = '../../sim/rtl_sim/out/rtl_impulseResponse.txt' +check_path = '../out/check_impulseResponse.txt' + +# open +rtl_file = open(rtl_path,'r') +check_file = open(check_path,'w') + +# read +rtl_list = rtl_file.readlines() + +# remove header text +del rtl_list[0:9] + +# remove newlines +rtl_list2 = [x.replace('\n', '') for x in rtl_list] + +# Expected from MATLAB, first 0:5 index is one +oneCount = 0 +for index in range(6): + searchObj = re.search( r'1$', rtl_list2[index]) + if searchObj: + oneCount += 1 + +# Expected from MATLAB, last 6:$ index is zero +zeroCount = 0 +for index in range(6,len(rtl_list2)): + searchObj = re.search( r'0$', rtl_list2[index]) + if searchObj: + zeroCount += 1 + +# check RTL match MATLAB expected +if oneCount == 6 and zeroCount == 7: + checkResult = "Impulse Response Test: PASS"; +else: + checkResult = "Impulse Response Test: FAIL"; + +# Log +print (checkResult); +check_file.write(checkResult) + +# close +rtl_file.close() +check_file.close()
trunk/sw/run/rtlMatlabCheck_impulseResponse.py Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/README.txt =================================================================== --- trunk/README.txt (nonexistent) +++ trunk/README.txt (revision 2) @@ -0,0 +1,32 @@ + LPFFIR Project README + +DIRECTORY STRUCTURE: +── bench Top level test bench +│ ├── systemc For SystemC sources +│ └── verilog For verilog sources +│ +├── doc Specification, design, verification and other PDF documents +│ └── src Source version of all documents (Microsoft Word, Microsoft Visio) +│ +├── rtl Verilog RTL sources +│ +├── sim Top level simulations +│ ├── matlab_sim MATLAB simulations +│ │ ├── out Useful output from MATLAB simulation +│ │ └── run MATLAB sources and for running MATLAB simulations +│ │ +│ └── rtl_sim RTL simulations +│ ├── out Useful output from RTL simulation +│ └── run For running RTL simulations +│ +└── sw Software sources for Python script utilities + ├── out Useful output from Python script utilities + └── run Python sources and for running Python script utilities + +OPEN-SOURCE TOOLS: +1. Ubuntu 18.04 LTS Linux OS development platform +2. SystemC 2.3.2-Accellera SystemC test bench simulator +3. Verilator Verilog simulator +4. GTKWave Verilog simulation waveform viewer +5. GNU Octave Octave syntax is largely compatible with MATLAB +6. Python RTL-simulation vs. MATLAB-expected check script

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