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URL https://opencores.org/ocsvn/m32632/m32632/trunk

Subversion Repositories m32632

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 48 to Rev 47
    Reverse comparison

Rev 48 → Rev 47

/m32632/trunk/rtl/DATENPFAD.v
4,16 → 4,13
// http://opencores.org/project,m32632
//
// Filename: DATENPFAD.v
// Project: M32632
// Version: 3.1 bug fix of 25 February 2019
// History: 3.0 Cache Interface reworked
// 2.1 bug fix of 26 November 2016
// Version: 3.0 Cache Interface reworked
// History: 2.1 bug fix of 26 November 2016
// 1.1 bug fix of 7 October 2015
// 1.0 first release of 30 Mai 2015
// Author: Udo Moeller
// Date: 8 July 2017
// Date: 2 December 2018
//
// Copyright (C) 2019 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
46,7 → 43,7
module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX,
IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE,
WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO,
ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, IVAR_MUX, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG,
DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT);
 
input BCLK;
99,7 → 96,6
output [3:0] CINV;
output [63:0] DP_Q;
output [1:0] IVAR;
output IVAR_MUX;
output [3:0] MCR;
output [3:0] PACKET;
output [31:0] PC_NEW;
149,6 → 145,7
wire [31:0] I_OUT;
wire [31:0] FP_OUT;
wire DOWR;
wire [31:0] DEST1,DEST2;
wire ENWR;
wire [3:0] OVF_BCD;
wire [3:0] DSR;
328,7 → 325,6
.CFG(CFG),
.CINV(CINV),
.IVAR(IVAR),
.IVAR_MUX(IVAR_MUX),
.Y_INIT(Y_INIT),
.MCR(MCR),
.DBG_TRAPS(TRAPS[5:3]),
/m32632/trunk/rtl/ICACHE.v
4,15 → 4,12
// http://opencores.org/project,m32632
//
// Filename: ICACHE.v
// Project: M32632
// Version: 3.1 bug fix of 25 February 2019
// History: 3.0 Cache Interface reworked
// 2.0 50 MHz release of 14 August 2016
// Version: 3.0 Cache Interface reworked
// History: 2.0 50 MHz release of 14 August 2016
// 1.0 first release of 30 Mai 2015
// Author: Udo Moeller
// Date: 8 July 2017
// Date: 2 December 2018
//
// Copyright (C) 2019 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
43,7 → 40,7
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 
module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, IVAR_MUX, VADR_D, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR_I,
KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR,
INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
 
66,12 → 63,10
input [1:0] IC_SIGS;
input [31:0] IO_Q;
input [1:0] IVAR;
input IVAR_MUX;
input [31:12] VADR_D;
input [28:4] KOLLI_A;
input [3:0] MCR_FLAGS;
input [23:0] MMU_DIN;
input [31:0] VADR_I;
input [31:0] VADR;
input INHIBIT;
input ENA_HK;
input ENDRAM;
97,10 → 92,9
reg DFF_HDFF1;
reg DFF_IRD_REG;
 
wire [31:0] VADR;
wire [4:0] A_CV;
wire [4:0] A_CV;
wire ACOK;
wire [4:0] ACV;
wire [4:0] ACV;
wire AUX_DAT;
wire CA_HIT;
wire CA_SET;
218,9 → 212,6
 
assign ICTODC[3] = USER;
 
assign VADR[31:12] = IVAR_MUX ? VADR_D : VADR_I[31:12];
assign VADR[11:0] = VADR_I[11:0];
 
always @(posedge BCLK) VADR_R <= VADR;
 
always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
/m32632/trunk/rtl/M32632.v
4,17 → 4,14
// http://opencores.org/project,m32632
//
// Filename: M32632.v
// Project: M32632
// Version: 3.1 bug fix of 25 February 2019
// History: 3.0 Cache Interface reworked
// 2.1 bug fix of 26 November 2016
// Version: 3.0 Cache Interface reworked
// History: 2.1 bug fix of 26 November 2016
// 2.0 50 MHz release of 14 August 2016
// 1.1 bug fix of 7 October 2015
// 1.0 first release of 30 Mai 2015
// Author: Udo Moeller
// Date: 8 July 2017
// Date: 2 December 2018
//
// Copyright (C) 2019 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
116,7 → 113,6
wire [3:0] ICTODC;
wire [6:0] INFO_AU;
wire [1:0] IVAR;
wire IVAR_MUX;
wire KDET;
wire [28:4] KOLLI_A;
wire [3:0] MCR;
286,7 → 282,6
.CINV(CINV),
.DP_Q(DP_Q),
.IVAR(IVAR),
.IVAR_MUX(IVAR_MUX),
.MCR(MCR),
.PACKET(PACKET),
.PC_NEW(PC_NEW),
328,12 → 323,10
.IC_SIGS(IC_SIGS),
.IO_Q(IO_Q),
.IVAR(IVAR),
.IVAR_MUX(IVAR_MUX),
.VADR_D(VADR[31:12]),
.KOLLI_A(KOLLI_A),
.MCR_FLAGS(MCR),
.MMU_DIN(MMU_DIN),
.VADR_I(PC_ICACHE),
.VADR(PC_ICACHE),
.INHIBIT(IC_INHIBIT),
.DRAM_ACC(IC_ACC),
.IO_RD(I_IORD),
/m32632/trunk/rtl/REGISTERS.v
4,13 → 4,11
// http://opencores.org/project,m32632
//
// Filename: REGISTERS.v
// Project: M32632
// Version: 3.1 bug fix of 25 February 2019
// Version: 3.0
// History: 1.0 first release of 30 Mai 2015
// Author: Udo Moeller
// Date: 8 July 2017
// Date: 2 December 2018
//
// Copyright (C) 2019 Udo Moeller
// Copyright (C) 2018 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
48,7 → 46,7
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ,
CFG, MCR, PTB_WR, PTB_SEL, IVAR, IVAR_MUX, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN );
 
input BCLK,BRESET;
input WREN,LD_OUT;
66,7 → 64,6
output PTB_WR;
output PTB_SEL;
output [1:0] IVAR;
output IVAR_MUX;
output [3:0] CINV;
output Y_INIT;
output [3:0] DSR;
100,8 → 97,7
if (!BRESET) MCR <= 4'h0;
else if (ld_mcr) MCR <= SRC1[3:0];
 
assign IVAR_MUX = op_ok & (WRADR[5:1] == 5'd7) & WREN; // IVAR0/1 = Reg. Nr. 14/15
always @(posedge BCLK) ivarreg <= IVAR_MUX;
always @(posedge BCLK) ivarreg <= op_ok & (WRADR[5:1] == 5'd7) & WREN; // IVAR0/1 = Reg. Nr. 14/15
assign IVAR = {ivarreg,PTB_SEL};
always @(posedge BCLK) PTB_WR <= op_ok & (WRADR[5:1] == 5'd6) & WREN; // PTB0/1 = Reg. Nr. 12/13

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